JPH07135615A - Digital signal demodulator - Google Patents

Abstract

PURPOSE:To allow the demodulator to track sufficiently carrier frequency fluctuation and to avoid a pseudo synchronization state. CONSTITUTION:A synchronization detection circuit 10 applies synchronization detection to an intermediate frequency signal based on a carrier signal. An error correction circuit 15 in a data recovery circuit 14 outputs a pseudo synchronization detection signal representing whether or not the state is the pseudo synchronization state. An error detection circuit 20 outputs an AFC signal used to control the oscillated frequency of a local oscillation circuit 8 and outputs a synchronization detection signal representing whether or not the state is the synchronization state. An adder 21 superimposes a sweep signal on the AFC signal. A switch circuit 25 controls the pseudo synchronization detection signal based on the synchronization detection signal delayed by a delay circuit 26. A switch circuit 24 stops superimposition only when the synchronization detection signal indicates the synchronization state and the pseudo synchronization detection signal indicates the state not in the pseudo synchronization state.

Description

Detailed Description of the Invention

[0001]

The present invention relates to MSK (Minimum Sh
ift Keying) modulation, QPSK (Quadature Phase Sh)
ift Keing) modulation, QAM (Quadrature Amplitude)
The present invention relates to a digital signal demodulating device that is suitable for use in a receiver or the like that receives a digitally modulated digital signal such as mode modulation.

[0002]

2. Description of the Related Art An MSK received using a synchronous detection method
In a digital signal demodulating device for demodulating a digitally modulated digital signal such as modulation, QPSK modulation or QAM modulation, it is known that a quasi-synchronized state exists in the synchronous detection circuit in addition to the normal synchronized state.
For example, the document “Theory of False Lock in Costas loop
s: IEEE TRANSACTIONS ON COMMUNICATIONS, VOL.COM-26,
According to NO.1, JANUARY 1978 ", when the center frequency in a normal synchronization state is fo and the transmission symbol rate of the signal is fs, a pseudo synchronization state occurs at a frequency of fo ± n (fs / 2) ( Hereinafter, this frequency is referred to as a pseudo sync frequency),
It becomes difficult to obtain normal demodulated data. Therefore, in the conventional digital signal demodulator using the coherent detection method, it is general to adopt a method of avoiding the pseudo-synchronized state by making the signal pull-in frequency width of the coherent detection circuit sufficiently smaller than the pseudo-synchronous frequency. It was

[0003]

At present, digital music broadcasting by a 12 GHz band MSK modulation system using a communication satellite is currently performed in Japan, and in the future, a QPSK modulation system by a 12 GHz or 21 GHz band broadcasting satellite will be used. Digital TV broadcasting is also planned. A satellite receiver for consumer use is ± 2 for a 12 GHz band receiver.
Since carrier frequency fluctuations of about MHz occur, the tuner unit needs a digital signal demodulator capable of following the fluctuations. However, in the past, as described above, the signal pull-in frequency width in the digital demodulator is limited in order to avoid the pseudo synchronization state.
There is a problem that the carrier frequency fluctuation cannot be sufficiently tracked.

Therefore, an object of the present invention is to provide a digital signal demodulating device capable of sufficiently following a carrier frequency fluctuation and avoiding a pseudo synchronization state.

[0005]

In order to achieve the above object, the present invention corrects an error in the data obtained by reproducing an error correction circuit, and also based on an error rate of the data. The synchronous detection unit is configured to detect whether the synchronous detection unit is in the pseudo synchronous state and output the detection result as a pseudo synchronous detection signal, and the synchronous detection unit is set to the synchronous state from the signal output from the synchronous detection unit. A synchronization detection circuit that detects whether or not there is, and outputs the detection result as a synchronization detection signal, a sweep signal generation circuit that generates a sweep signal, and an AFC signal that is fed back to the frequency conversion unit. A superimposing means for superimposing a signal, a pseudo synchronization detection signal output from the error correction circuit and a synchronization detection signal output from the synchronization detection circuit are input, and the synchronization detection signal is in a synchronization state of the synchronization detection unit. Before a certain period of time after indicating that there is, a signal indicating that the synchronous detection unit is not in the pseudo-synchronization state is used instead of the pseudo-synchronization detection signal output from the error correction circuit. And a signal control means for directly outputting the pseudo synchronization detection signal output from the error correction circuit after the lapse of the time, and a pseudo synchronization detection signal output from the signal control means and the synchronization detection circuit. The output sync detection signal is input, the pseudo sync detection signal indicates that the sync detector is not in the pseudo sync state, and the sync detection signal indicates that the sync detector is in the sync state. In that case, the superimposing means is controlled so as not to superimpose the sweep signal on the AFC signal in the superimposing means. A superposition control means for controlling said superimposing means so as to perform superimposition of the sweep signal to the serial AFC signal and to provide a.

[0006]

As described above, by providing the superimposing means for superimposing the sweep signal on the AFC signal for controlling the oscillation frequency of the oscillation signal in the frequency conversion section, the frequency of the oscillation frequency of the oscillation signal in the frequency conversion section is provided. By widening the range, it is possible to expand the frequency range in which the synchronization state can be established, and by controlling this superposition means by the synchronization detection signal to detect the synchronization state, at the same time stopping the superposition of the sweep signal, Even if the frequency fluctuation of the received signal is large, the synchronization state can be quickly established.

Further, since it is impossible to detect the pseudo sync state by the sync detection circuit, the error correction circuit in the data reproduction circuit obtains the data error rate and compares the data error rate with a predetermined value. , The result is output as a pseudo-synchronization detection signal, and when the pseudo-synchronization state is detected by controlling the superimposing means, the AF of the sweep signal is detected.
It is configured so that the superimposition on the C signal is restarted and the synchronization state is removed.
Prevents pseudo sync condition.

The above operation is shown in the flow chart of FIG.

At step 601, when a signal is received,
In step 602, the frequency of the intermediate frequency signal is swept using the sweep signal, and the process proceeds to step 603.

In step 603, synchronous detection is performed on the intermediate frequency signal, the result is output, and step 604
Move on to.

In step 604, it is determined whether or not the synchronous detection circuit is in the synchronous state by measuring from the output signal of the synchronous detection circuit in the synchronous detection circuit. Only when in the synchronous state, the process proceeds to step 605 and the synchronous state The loop of step 603 and step 604 is continued until the state is established.

In step 605, the superimposition of the sweep signal on the AFG signal is stopped, and the process proceeds to step 606.

In step 606, it is determined whether the output signal of the synchronous detection circuit is in the pseudo synchronization state by measuring the error rate in the error correction circuit. Only when it is determined that the pseudo synchronization state is not established, the step is performed. If it is determined to be in the pseudo-synchronous state, the process returns to step 602, and the operation from step 602 is repeated.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below as an application to a heterodyne receiver with reference to the drawings.

FIG. 1 is a block diagram showing a digital signal demodulating apparatus as a first embodiment of the present invention. In FIG. 1, 1 is a received signal input terminal, 2 is a first mixer circuit,
3 is a first local oscillation circuit, 4 is a tuning circuit, 5 is a microcomputer (hereinafter referred to as a microcomputer), 6 is a tuning signal input terminal, 7 is a second mixer circuit, 8 is a second local oscillation circuit,
9 is an IF (intermediate frequency) filter, 10 is a synchronous detection circuit,
11 is an oscillation circuit for synchronous detection, 12 and 13 are low-pass filters (hereinafter referred to as LPF), 14 is a data recovery circuit,
15 is an error correction circuit, 16 is a reproduction data output terminal, 17
Is a synchronous reproducing circuit, 18 is an error detecting circuit, 19 is a clock reproducing circuit, 20 is a synchronous detecting circuit, 21 is an adder, 22 is an LPF, 23 is a sweep signal generating circuit, 24 and 25 are switch circuits, and 26 is a delay circuit. Is.

In FIG. 1, the received radio frequency signal S _RF input from the input terminal 1 is mixed with the output signal of the first local oscillation circuit 3 for channel selection in the first mixer circuit 2,
It is converted to the first IF signal S _IF1 .

The output of the first local oscillation circuit 3 is controlled by the signal output from the channel selection circuit 4, and the channel selection circuit 4 uses the microcomputer 5
It is controlled by the signal output by. The microcomputer 5 receives the tuning signal input from the input terminal 6 and outputs a control signal corresponding to the tuning signal to the tuning circuit 4.

The first IF signal S _IF1 is mixed by the second mixer circuit 7 with the output signal of the second local oscillation circuit 8 and converted into the second IF signal S _IF2 .

By supplying the second IF signal S _IF2 to the IF filter 9 which is a band pass filter, a received signal other than the channel designated by the channel selection signal input from the input terminal 6 and an unnecessary band are supplied. External noise, interference, etc. are removed, and the IF signal of the channel designated by this channel selection signal is selected.

The second IF signal S _IF2 output from the IF filter 9 is supplied to the synchronous detection circuit 10. In the synchronous detection circuit 10, the carrier signal S _CA output from the synchronous detection oscillation circuit 11 which is a voltage controlled oscillator (VCO) is input, and the second IF signal S _IF2 is synchronously detected thereby. Here, the synchronous detection means the carrier signal S _CA and the second IF.
This is detection performed in a state where the frequency and phase of the signal S _IF2 match. The output signal S _I of the synchronous detection circuit 10,
S _Q is supplied to the LPFs 12 and 13 to remove high frequency components.

The output signals S _I and S _Q of the LPFs 12 and 13 are supplied to a data reproducing circuit 14, where the data signal used for modulating the received signal S _RF is reproduced, and the error correcting circuit 15 corrects the error. And output from the output terminal 16.

Also, the output signals S _{I of the} LPFs 12 and 13,
S _Q is also supplied to the synchronous reproduction circuit 17. The sync reproducing circuit 17 is composed of an error detecting circuit 18, a clock reproducing circuit 19 and a sync detecting circuit 20. Of these, the error detection circuit 18 receives the second IF signal S _IF2 input to the synchronous detection circuit 10 from the output signals S _I and S _Q of the LPFs 12 and 13.
And carrier wave signal S output from the oscillation circuit 11 for synchronous detection
An error in frequency or phase with _CA is detected, and two error signals S _AFC and S _PLL are generated. Therefore, when the frequency or phase of the second IF signal S _IF2 changes, the error detection circuit 18 generates these error signals S _AFC and S _PLL . Since the error detecting operation in the error detecting circuit 18 is not directly related to the present invention, its detailed description will be omitted here.
If further detailed explanation is desired, for example, JP-A-55
See, for example, Japanese Patent Publication No.-73164.

The clock reproducing circuit 19 which constitutes the synchronous reproducing circuit 17 has an output signal S from the LPFs 12 and 13.
_The data reproducing clock is reproduced from _I and S _Q and supplied to the data reproducing circuit 14. Similarly, the sync detection circuit 20 that constitutes the sync reproduction circuit 17 includes the LPF 12,
It is detected from the output signals S _I and S _{Q of} 13 whether the synchronous detection circuit 10 is in a synchronous state capable of synchronous detection, and a synchronous detection signal S _LD indicating the detection result is output.

The synchronization detection circuit 20 will be described in more detail with reference to FIG. 2 is a block diagram showing a specific example of the synchronization detection circuit in FIG. 1. In FIG. 2, 201, 202 and 205 are multipliers and 203 is an LP.
F and 204 are adders, and the parts corresponding to those in FIG.

In FIG. 2, the output signals of the LPFs 12 and 13 are squared by the multipliers 201 and 202, respectively, and then combined by the adder 204, and the output signal is multiplied by the multiplier 205 from the clock recovery circuit 19 of the synchronous recovery circuit 17. The output signal of the multiplier 205 is multiplied by L
The synchronization detection signal S _LD is obtained by passing it through the PF 203. This synchronization detection signal S _LD is the second intermediate frequency signal S
_If the frequency and the phase of the carrier wave S _CA output from the _IF2 and the oscillation circuit 11 for synchronous detection match, it is determined that they are in a synchronized state, and a high level signal (hereinafter referred to as H signal) is generated.
If they do not match, a low level signal (hereinafter referred to as the L signal) is determined as not being in the synchronized state.

As described above, according to this example,
The synchronization state can be detected with a simple configuration.

On the other hand, one of the two error signals S _AFC and S _PLL generated from the error detection circuit 18 is the error signal S
_{The AFC} is fed back to the second local oscillation circuit 8 via the adder 21 as an AFC signal for absorbing the frequency error, and causes the oscillation frequency of the second local oscillation circuit 8 to follow the frequency fluctuation of the reception signal S _RF. Then, the second intermediate frequency signal S _IF2 output from the second mixer circuit 7 is made to match the center frequency of the IF filter 9. The other error signal S _PLL is fed back to the synchronous detection oscillation circuit 11 as a PLL signal for absorbing a phase error, and PLL-controls the carrier signal S _CA output from the synchronous detection oscillation circuit 11, The phase of the second IF signal S _IF2 output from the IF filter 9 is made to follow.

However, with the above method alone, the received signal S
_{When the RF} frequency fluctuates significantly, the second mixer circuit 7
It is assumed that it takes time to match the second IF signal S _IF2 output from the center frequency of the IF filter 9. Therefore, in the present embodiment, a sweep circuit 23 that generates a sweep signal is prepared, and the generated sweep signal S _SW is superimposed on the AFC signal S _AFC by the adder 21 via the switch circuit 24 to generate the second local oscillation. The oscillation frequency of the circuit 8 is forcibly swept, the oscillation frequency range of the second local oscillation circuit 8 is widened, the synchronization frequency range of the reception signal S _RF is widened, and the synchronization state is quickly established. There is. At the same time, the synchronization detection signal S _LD output from the synchronization detection circuit 20 is used to control the switch circuit 24 so that the sweep is quickly stopped when the synchronization state is established.
_{When LD} becomes an H signal, the switch circuit 24 is turned off to stop superimposing the sweep signal S _{SW on} the AFC signal S _AFC .

However, when the center frequency of the second intermediate frequency signal S _IF2 in the normal synchronization state is fo and the received symbol rate of the signal is fs, fo ± n (fs /
At the frequency of 2), the synchronous detection circuit 10 may be in a pseudo synchronous state. Here, the pseudo sync state means that the sync detection circuit 20 outputs the H signal indicating the sync state as the sync detection signal S _LD although the sync detection circuit 10 is not in the sync state. State. In such a pseudo-synchronized state, data is not normally reproduced in the data reproducing circuit 14, and it is necessary to prevent this.

Therefore, in the present embodiment, the error correction circuit 15 corrects the data error and simultaneously measures the data error rate. When the error rate exceeds a predetermined value, the synchronous detection is performed. It is determined that the circuit 10 is in the pseudo sync state, and the H signal is output as the pseudo sync detection signal S _{FL D} ,
If the error rate is equal to or lower than a predetermined value, it is determined that the normal synchronization state is established, and the L signal is output as the pseudo synchronization detection signal S _FLD . The switch circuit 24 is also controlled by the pseudo sync detection signal S _FLD .

Here, for example, this pseudo synchronization detection signal S
A method of controlling the superimposition of the sweep signal S _{SW on} the AFC signal S _AFC only by _FLD is also conceivable. In this case, however, the error correction circuit 15 detects a pseudo synchronization state after the synchronization state is established. Due to the delay, the state of the synchronous detection circuit 10 has already changed by the time the pseudo synchronous detection signal S _FLD is output. To prevent this, the sweep speed of the sweep circuit 23 may be slowed sufficiently, but in this case, it takes time to establish the synchronization state. Therefore, in order to reliably detect the pseudo sync state without slowing down the sweep speed, the sync state is once detected before the data reproduction circuit 14, and if the sync state is determined, the sweep signal S _SW is detected there. It is necessary to stop the superimposing on the AFC signal S _AFC and keep the state of the synchronous detection circuit 10 constant until the pseudo-synchronous state is determined.

Therefore, the switch circuit 24 is controlled by the two signals of the synchronization detection signal S _LD from the synchronization detection circuit 20 and the pseudo synchronization detection signal S _FLD from the error correction circuit 15.
The sync detection signal S _LD is an H signal, and the pseudo sync detection signal S
Only when _FLD is L signal, sweep signal S _{SW is changed} to AFC signal S
It is configured not to overlap with _AFC .

That is, even if the synchronization detection circuit 20 determines that it is in the synchronization state and the superimposition of the sweep signal S _{SW on} the AFC signal S _AFC is stopped, the error correction circuit 15 determines that it is in the pseudo synchronization state. , The AFC signal S _AFC is again superposed with the sweep signal S _CA to forcibly remove from the synchronization state, and the above-described operation is repeated, whereby the normal synchronization state in which the pseudo synchronization detection signal is not output can be obtained. .

However, if the above configuration is used as it is, it takes some time to reproduce the data and measure the error rate. Therefore, the sync detection signal S _LD and the pseudo sync detection signal S
There is a time lag in the _FLD output, and the synchronization state is temporarily established.
Even if it is in the normal synchronization state, since the pseudo synchronization detection signal S _FLD is output as the H signal in the initial stage, the synchronization detection signal S _LD causes the AFC signal S _AFC of the sweep signal S _SW.
Even if the superimposition on the AFC signal is stopped, the superimposition on the AFC signal S _AFC of the sweep signal S _SW is restarted by the pseudo synchronization detection signal S _{FLD at} the next moment, and the synchronization is lost.

In order to avoid this, the pseudo sync detection signal S
_{The FLD} is controlled by the synchronization detection signal S _LD in the switch circuit 25. When the synchronization state is not established, the supply of the pseudo synchronization detection signal S _{FLD to} the switch circuit 24 is stopped and the normal synchronization state is set instead. The L signal shown is supplied. Further, it is necessary to supply the pseudo sync detection signal S _{FLD to} the switch circuit 24 after a sufficient time for the error correction circuit 15 to detect the pseudo sync state, and to control the switch circuit 25. Is the synchronization detection signal S
_LD is performed with a signal delayed by the delay circuit 26.

This will be described with reference to FIG. FIG. 3 shows FIG.
Detection signal S input to the switch circuit 25 in
₇ is a timing chart showing the respective states of the _LD and the pseudo sync detection signal S _FLD and the presence / absence of superimposition of the sweep signal _{S SW on} the AFC signal S _AFC . In FIG. 3, (A) is a case where the error correction circuit 15 detects a normal synchronization state, and (B) is a case where the error correction circuit 15 detects a pseudo synchronization state. Further, regarding the synchronization detection signal S _LD , H
Indicates a synchronous state, L indicates an asynchronous state, H indicates a pseudo synchronous state, L indicates a normal synchronous state regarding the pseudo synchronization detection signal S _FLD , and ON indicates sweep signal S _SW regarding the sweep signal S _SW , AFC signal S _AFC , And OFF indicates that the sweep signal S _SW is not superimposed on the AFC signal S _AFC .

In the initial state, the switch circuit 24 is connected to
The L signal indicating the asynchronous state is input as the synchronization detection signal S _LD from the synchronization detection circuit 20, the L signal is input as the pseudo synchronization detection signal S _FLD from the switch circuit 25, the switch circuit 24 is in the ON state, and the sweep is performed. Signal S _SW is AF
It is superimposed on the C signal S _AFC .

It is assumed that, at a certain time t, the synchronization detection circuit 20 detects that the synchronization detection circuit 10 is in the synchronization state and outputs the H signal as the synchronization detection signal S _LD . The synchronization detection signal S _LD is input to the switch circuit 24 and also to the switch circuit 25 via the delay circuit 26, and the switch circuit 24 stops superimposing the sweep signal S _{SW on} the AFC signal S _AFC . After a certain period of time, the switch circuit 25
Switch circuit 24 for the pseudo sync detection signal S _FLD
Input to.

In the case of FIG. 3A, even if the pseudo synchronization detection signal S _FLD starts to be input to the switch circuit 24 under the control of the delayed synchronization detection signal S _LD , the pseudo synchronization detection signal S
_{Since FLD} remains the L signal, A of sweep signal S _SW
The normal synchronization state continues stably while the superimposition on the FC signal S _AFC is stopped.

In the case of FIG. 3B, the synchronization detection signal S _LD
After the superimposition of the sweep signal S _{SW on} the AFC signal S _AFC is stopped, the pseudo sync detection signal S _FLD is input to the switch circuit 24 under the control of the delayed sync detection signal S _LD. Since the synchronization detection signal S _FLD is the H signal, superposition of the sweep signal S _{SW on} the AFC signal S _AFC is restarted. In this way, the synchronization state is released and the pseudo synchronization state is prevented.

According to the present embodiment, the sweep circuit 23, the synchronization detecting means, and the pseudo synchronization detecting means are used in an overlapping manner to speed up the establishment of synchronization, increase the width of the synchronization pull-in, and prevent the pseudo synchronization state. .

FIG. 4 is a block diagram showing a digital signal demodulating device according to a second embodiment of the present invention. In FIG. 4, parts corresponding to those in FIG. To do.

In the embodiment shown in FIG. 1, the sweep signal S _SW is superimposed on the AFC signal S _AFC fed back to the second local oscillation circuit 8 via the switch circuit 24, but in this embodiment, It is superimposed on the PLL signal S _PLL fed back to the synchronous detection oscillation circuit 11 via the switch circuit 24.

The operation of this embodiment will be described below.
Similar to the embodiment shown in FIG. 1, the error detection circuit 18 outputs two signals, a PLL signal S _PLL for controlling the synchronous detection oscillation circuit 11 and an AFC signal S _AFC for controlling the second local oscillation circuit 8. Unlike the embodiment shown in FIG. 1, the sweep signal S
PLL signal S that returns _SW to the oscillation circuit 11 for synchronous detection
_It is superimposed on the _PLL . Other operations are similar to those of the embodiment shown in FIG.

According to this embodiment, since the sweep signal S _SW is superimposed on the PLL signal S _PLL which controls the synchronous detection oscillation circuit 11, the same effect as that of the embodiment shown in FIG. 1 can be obtained.

FIG. 5 is a block diagram showing a digital signal demodulating apparatus as a third embodiment of the present invention. In FIG. 5, 51 is an AFC signal receiving section, 52 is a channel selection data output section, and 53 is a sweep. The data generator 54 is a switch circuit. The other parts corresponding to those in FIG. 1 are designated by the same reference numerals and duplicate description will be omitted.

In the embodiment shown in FIG. 1, the sweep signal S _SW is superposed on the AFC signal S _AFC fed back to the second local oscillation circuit 8 via the switch circuit 24, but in the present embodiment, The AFC signal S _AFC is fed back to the AFC signal receiving section 51 of the microcomputer 5.

The operation of this embodiment will be described below.
In FIG. 5, the received signal S _RF input from the input terminal 1
Is a local oscillation circuit 3 for channel selection in the mixer circuit 2.
Is mixed with the output signal of and converted into an IF signal S _IF .

The output of the local oscillation circuit 3 is controlled by the signal output by the channel selection circuit 4, and the channel selection circuit 4 is controlled by the signal output by the microcomputer 5.

The microcomputer 5 receives the channel tuning signal input from the input terminal 6, outputs a control signal corresponding to this signal from the tuning data section 52, and supplies it to the tuning circuit 4.

The IF signal S _IF is supplied to the IF filter 9 which is a bandpass filter, so that a received signal other than the channel designated by the channel selection signal input from the input terminal 6 and unnecessary out-of-band noise are generated. , Interference, etc. are removed, and the IF signal S _{IF of the} channel designated by this channel selection signal is selected.

IF signal S output from IF filter 9
_{The IF} is supplied to the synchronous detection circuit 10. Synchronous detection circuit 10
Then, the carrier signal S _CA output from the synchronous detection oscillation circuit 11 which is a voltage controlled oscillator (VCO) is input,
As a result, the IF signal S _IF is synchronously detected. here,
Synchronous detection is detection performed in a state where the frequency and phase of the carrier signal S _CA and the IF signal S _IF match.
The output signals S _I and S _Q of the synchronous detection circuit 10 are LPFs 12 and 1
3 and the high frequency components are removed.

The output signals S _I and S _Q of the LPFs 12 and 13 are
The data signal is supplied to the data reproducing circuit 14, where the data signal used for modulating the received signal is reproduced, and then the error is further corrected in the error correction circuit 15 and output from the output terminal 16.

Further, the output signals S _{I of the} LPFs 12 and 13 are
S _Q is also supplied to the synchronous reproduction circuit 17. The operation of the synchronous reproducing circuit 17 is the same as that of the embodiment shown in FIG. 1, and therefore its explanation is omitted here.

Of the two error signals S _AFC and S _PLL generated from the error detection circuit 18, one signal S _PLL is fed back to the synchronous detection oscillation circuit 11 as a PLL signal for absorbing the phase error. , The oscillation frequency of the synchronous detection oscillation circuit 11 is PLL controlled to follow the phase of the IF signal S _IF . The other error signal S _AFC is used as an AFC signal for absorbing a frequency error, and is used as an AF signal inside the microcomputer 5.
It is fed back to the C signal receiving unit 51 via the LPF 32. A
The FC signal receiving unit 51 superimposes the input AFC signal on the tuning circuit control signal output from the tuning data unit 52 to cause the oscillation frequency of the local oscillation circuit 3 to follow the frequency fluctuation of the reception signal S _RF. , The frequency error of the intermediate frequency signal S _IF is corrected.

However, the received signal S _RF can be obtained only by the above method.
If the frequency f is significantly changed, it is assumed that it takes time for the frequency of the intermediate frequency signal S _IF input to the synchronous detection circuit 10 and the frequency of the carrier wave S _CA output from the synchronous detection oscillation circuit 11 to match. Therefore, the sweep data 53 is prepared inside the microcomputer, the sweep data is superimposed on the tuning circuit control signal via the switch circuit 54, the oscillation frequency of the local oscillation circuit 3 is forcedly swept, and the input signal S _RF is synchronized. The frequency range is widened and the synchronization state is quickly established. For other operations, the same operations as in the embodiment shown in FIG. 1 are performed.

According to this embodiment, the sweep circuit 23 is unnecessary, and in addition to the effect of the embodiment shown in FIG. 1, the circuit structure can be further simplified.

FIG. 6 is a block diagram showing a digital signal demodulating device according to a fourth embodiment of the present invention. In FIG. 6, 27 is a second microcomputer. The other parts corresponding to those in FIG. 1 are designated by the same reference numerals and duplicate description will be omitted.

The operation of this embodiment will be described below.
In the embodiment shown in FIG. 1, using a synchronization detection signal S _LD and the pseudo sync detecting signal S _FLD as a means of controlling the switch circuit 24, further pseudo sync detecting signal S _FLD sync detection signal S
_The switch circuit 25 is controlled by the _LD . In the present embodiment, the sync detection signal S _LD and the pseudo sync detection signal S _FLD are temporarily taken in by the second microcomputer 27, and a control signal having the same function as that of the embodiment shown in FIG. 1 is supplied to the switch circuit 24. The operation similar to that of the embodiment shown in FIG. 1 can be performed with a simpler circuit configuration. Further, the second microcomputer 27 may be operated by the microcomputer 5. For other operations, the same operations as in the embodiment shown in FIG. 1 are performed.

According to the present embodiment, since the operation of the switch circuit 25 and the delay circuit 26 is performed by the second microcomputer 27, adjustment of circuit constants etc. becomes unnecessary, and in addition to the effect of the embodiment shown in FIG. Moreover, the circuit configuration can be further simplified.

FIG. 7 is a block diagram showing a digital signal demodulating device as a fifth embodiment of the present invention. In FIG. 7, parts corresponding to those in FIG. To do.

In the embodiment shown in FIG. 1, the switch circuit 25
In the present embodiment, the switch circuit 2 is controlled by a signal obtained by delaying the synchronization detection signal S _LD.
4 outputs a signal indicating the ON / OFF state of the switch circuit 24, which is controlled by a delayed signal. That is, the switch circuit 24 is turned on,
When the sweep signal S _SW is superimposed on the AFC signal S _AFC , the switch circuit 25 is turned off with a delay.
When the L signal is supplied to the switch circuit 24, the switch circuit 24 is turned off, and the superimposition of the sweep signal S _{SW on} the AFC signal S _AFC is stopped, the switch circuit 25 is turned on after a delay. And the pseudo sync detection signal S
_FLD is supplied to the switch circuit 24.

According to this embodiment, the same effect as that of the embodiment shown in FIG. 1 can be obtained.

[0064]

As described above, according to the present invention,
A synchronization detection signal output from a synchronization detection circuit having a simple structure such as multiplication of a reception signal and a clock generated from the reception signal, and an error correction circuit of a data reproduction circuit, which is obtained by using an error rate By controlling the sweep circuit for expanding the capture range by combining with the pseudo sync detection signal, the sync state can be established at high speed without falling into the pseudo sync state, and the frequency range in which synchronous detection can be performed can be expanded. Therefore, the carrier frequency fluctuation can be sufficiently tracked.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital signal demodulating device as a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific example of a synchronization detection circuit in FIG.

FIG. 3 is a timing chart showing respective states of a sync detection signal S _LD and a pseudo sync detection signal S _FLD input to a switch circuit 25 in FIG. 1 and whether or not a sweep signal S _SW is superposed on an AFC signal S _AFC . is there.

FIG. 4 is a block diagram showing a digital signal demodulation device as a second embodiment of the present invention.

FIG. 5 is a block diagram showing a digital signal demodulating device as a third embodiment of the present invention.

FIG. 6 is a block diagram showing a digital signal demodulating device as a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a digital signal demodulating device as a fifth embodiment of the present invention.

FIG. 8 is a flowchart showing a flow of operations of the digital signal demodulation device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Received signal input terminal, 2 ... 1st mixer circuit, 3 ... 1st local oscillation circuit, 4 ... Tuning circuit, 5 ... Microcomputer, 6 ... Tuning signal input terminal, 7 ... 2nd mixer circuit, 8 ... Two local oscillation circuits, 9 ... IF filter, 10 ... Synchronous detection circuit, 11 ...
Oscillation circuit for synchronous detection, 12, 13 ... LPF, 14 ... Data recovery circuit, 15 ... Error correction circuit, 16 ... Reproduction data output terminal, 17 ... Synchronous reproduction circuit, 18 ... Error detection circuit, 1
9 ... Clock reproduction circuit, 20 ... Synchronization detection circuit, 21 ... Adder, 22 ... LPF, 23 ... Sweep signal generation circuit, 24,
25 ... Switch circuit, 26 ... Delay circuit, 27 ... Second microcomputer, 51 ... AFC signal receiving section, 52 ... Channel selection data output section, 53 ... Sweep data generating section, 54 ... Switch circuit,
201, 202, 205 ... Multiplier, 203 ... LPF, 2
04 ... Adder.

Claims (5)

[Claims] 1. At least one frequency converter for mixing a digitally modulated reception signal with an oscillation signal to convert it into an intermediate frequency signal, and synchronously detecting the intermediate frequency signal obtained by the conversion with a carrier signal. It has a synchronous detection section for outputting and an error correction circuit inside thereof, reproduces data from the signal output from the synchronous detection section, and corrects the error of the data obtained by reproduction by the error correction circuit. A data reproducing circuit for detecting a frequency fluctuation and a phase fluctuation of the intermediate frequency signal from the signal output from the synchronous detection unit, and an error signal (hereinafter referred to as an AFC signal) corresponding to the frequency fluctuation and the phase. An error detection circuit that generates an error signal (hereinafter, referred to as a PLL signal) according to a variation, and the generated AFC signal is fed back to the frequency conversion unit to generate the AFC signal. Frequency control means for controlling the oscillation frequency of the oscillation signal in the frequency conversion section, and the generated PLL signal is fed back to the synchronous detection section, and the phase of the carrier signal in the synchronous detection section is returned by the PLL signal. In the digital signal demodulating device including a phase control unit for controlling, the error correction circuit corrects an error of the data obtained by reproduction, and further, based on an error rate of the data, the synchronization is performed. Detects whether the detection unit is in the pseudo synchronization state, outputs the detection result as a pseudo synchronization detection signal, and determines whether the synchronization detection unit is in the synchronization state from the signal output from the synchronization detection unit. Detection circuit, which outputs the detection result as a synchronization detection signal, a sweep signal generation circuit which generates a sweep signal, and feedback to the frequency conversion section. Superimposing means for superimposing the generated sweep signal on the AFC signal, a pseudo sync detection signal output from the error correction circuit and a sync detection signal output from the sync detection circuit, Before a certain time elapses after the detection signal indicates that the synchronous detection unit is in the synchronous state, the synchronous detection unit is not in the pseudo synchronous state in place of the pseudo synchronous detection signal output from the error correction circuit. A signal indicating that the pseudo-synchronization detection signal is output, and after the elapse of the time, the pseudo-synchronization detection signal output from the error correction circuit is output as it is, and the signal control means outputs the signal. The pseudo sync detection signal and the sync detection signal output from the sync detection circuit are input, and the pseudo sync detection signal indicates that the sync detection unit is not in the pseudo sync state. When the synchronous detection signal indicates that the synchronous detection unit is in a synchronous state, the superimposing means is controlled so as not to superimpose the sweep signal on the AFC signal in the superimposing means, In other cases, the superimposing means is provided to control the superimposing means so that the superimposing means superimposes the sweep signal on the AFC signal. 2. A at least one frequency converter for mixing a digitally modulated reception signal with an oscillation signal to convert it into an intermediate frequency signal, and synchronously detecting the intermediate frequency signal obtained by the conversion with a carrier signal. It has a synchronous detection section for outputting and an error correction circuit inside thereof, reproduces data from the signal output from the synchronous detection section, and corrects the error of the data obtained by reproduction by the error correction circuit. A data reproducing circuit for detecting a frequency fluctuation and a phase fluctuation of the intermediate frequency signal from the signal output from the synchronous detection unit, and an error signal (hereinafter referred to as an AFC signal) corresponding to the frequency fluctuation and the phase. An error detection circuit that generates an error signal (hereinafter, referred to as a PLL signal) according to a variation, and the generated AFC signal is fed back to the frequency conversion unit to generate the AFC signal. Frequency control means for controlling the oscillation frequency of the oscillation signal in the frequency conversion section, and the generated PLL signal is fed back to the synchronous detection section, and the phase of the carrier signal in the synchronous detection section is returned by the PLL signal. In the digital signal demodulating device including a phase control unit for controlling, the error correction circuit corrects an error of the data obtained by reproduction, and further, based on an error rate of the data, the synchronization is performed. Detects whether the detection unit is in the pseudo synchronization state, outputs the detection result as a pseudo synchronization detection signal, and determines whether the synchronization detection unit is in the synchronization state from the signal output from the synchronization detection unit. Is detected and the detection result is output as a synchronization detection signal, a sweep signal generation circuit that generates a sweep signal, and a feedback signal to the synchronous detection unit. Superimposing means for superimposing the generated sweep signal on the PLL signal, a pseudo sync detection signal output from the error correction circuit and a sync detection signal output from the sync detection circuit, Before a certain time has elapsed after the detection signal indicates that the synchronous detection unit is in the synchronous state,
Instead of the pseudo sync detection signal output from the error correction circuit, a signal indicating that the sync detection unit is not in the pseudo sync state is output as the pseudo sync detection signal, and after the elapse of the time, the error The signal control means for directly outputting the pseudo sync detection signal output from the correction circuit, the pseudo sync detection signal output from the signal control means, and the sync detection signal output from the sync detection circuit are input, and the pseudo sync signal is input. When the synchronous detection signal indicates that the synchronous detection unit is not in the pseudo synchronous state, and the synchronous detection signal indicates that the synchronous detection unit is in the synchronous state, the superimposing means outputs a signal to the PLL signal. The superimposing means is controlled so as not to superimpose the sweep signal, and in other cases, the superimposing means superimposes the sweep signal on the PLL signal. A digital signal demodulating apparatus characterized by a provided a superposition control means for controlling said superimposing means so. 3. A local oscillation circuit for generating and outputting an oscillation signal, a microcomputer (hereinafter, referred to as a microcomputer) for generating and outputting a control signal according to an input tuning signal, and an output from the microcomputer. A channel selection circuit that controls the oscillation frequency of the oscillation signal in the local oscillation circuit according to the control signal, and mixes the input digitally modulated reception signal with the oscillation signal output from the local oscillation circuit, A mixer circuit for converting the frequency of the received signal to an intermediate frequency and outputting it as an intermediate frequency signal, a synchronous detection unit for synchronously detecting and outputting the intermediate frequency signal output from the mixer circuit by a carrier signal, and inside thereof. An error correction circuit is provided, data is reproduced from the signal output from the synchronous detection unit, and the error of the data obtained by the reproduction is corrected by the error correction circuit. A data reproduction circuit that corrects
An error signal (hereinafter referred to as an AFC signal) corresponding to the frequency variation and an error corresponding to the phase variation are detected by detecting the frequency variation and the phase variation of the intermediate frequency signal from the signal output from the synchronous detection unit. Error detection circuit for generating a signal (hereinafter referred to as a PLL signal), and the generated AFC
Frequency control means for returning a signal to the microcomputer, superimposing the AFC signal on the control signal generated in the microcomputer, and controlling the oscillation frequency of the oscillation signal in the local oscillation circuit; and the generated PLL. A digital signal demodulating apparatus comprising: a phase control means for feeding back a signal to the synchronous detection section and controlling the phase of the carrier signal in the synchronous detection section by the PLL signal. In addition to correcting the error of the data obtained by the above, based on the error rate of the data, it is detected whether or not the synchronous detection unit is in the pseudo synchronous state, and the detection result is output as a pseudo synchronous detection signal. In addition, it detects whether or not the synchronous detection unit is in a synchronous state from the signal output from the synchronous detection unit, and the detection result is a synchronous detection signal. And a sync detection circuit output from the error correction circuit and a sync detection signal output from the sync detection circuit are input, and the sync detection signal is synchronized with the sync detection unit. Before a lapse of a certain time after indicating that the pseudo-sync detection signal is output, the pseudo-sync detection signal output from the error correction circuit is replaced by a signal indicating that the sync detection unit is not in the pseudo-sync state. And a signal control means for outputting the signal as a signal and, after the lapse of the time, directly outputting the pseudo synchronization detection signal output from the error correction circuit, the microcomputer prepares sweep data, and the signal control is performed. The pseudo sync detection signal output from the means and the sync detection signal output from the sync detection circuit are input, and the pseudo sync detection signal causes the sync detection unit to enter the pseudo sync state. And the synchronization detection signal indicates that the synchronization detection unit is in a synchronization state, the sweep data prepared for the generated control signal is not superimposed, and in other cases Is a digital signal demodulating device, wherein the prepared sweep data is superimposed on the generated control signal. 4. An at least one frequency converter for mixing a digitally modulated reception signal with an oscillation signal to convert it into an intermediate frequency signal, and synchronously detecting the intermediate frequency signal obtained by the conversion with a carrier signal. It has a synchronous detection section for outputting and an error correction circuit inside thereof, reproduces data from the signal output from the synchronous detection section, and corrects the error of the data obtained by reproduction by the error correction circuit. A data reproducing circuit for detecting a frequency fluctuation and a phase fluctuation of the intermediate frequency signal from the signal output from the synchronous detection unit, and an error signal (hereinafter referred to as an AFC signal) corresponding to the frequency fluctuation and the phase. An error detection circuit that generates an error signal (hereinafter, referred to as a PLL signal) according to a variation, and the generated AFC signal is fed back to the frequency conversion unit to generate the AFC signal. Frequency control means for controlling the oscillation frequency of the oscillation signal in the frequency conversion section, and the generated PLL signal is fed back to the synchronous detection section, and the phase of the carrier signal in the synchronous detection section is returned by the PLL signal. In the digital signal demodulating device including a phase control unit for controlling, the error correction circuit corrects an error of the data obtained by reproduction, and further, based on an error rate of the data, the synchronization is performed. Detects whether the detection unit is in the pseudo synchronization state, outputs the detection result as a pseudo synchronization detection signal, and determines whether the synchronization detection unit is in the synchronization state from the signal output from the synchronization detection unit. Detection circuit, which outputs the detection result as a synchronization detection signal, a sweep signal generation circuit which generates a sweep signal, and feedback to the frequency conversion section. Superimposing means for superimposing the generated sweep signal on the AFC signal, a pseudo sync detection signal output from the error correction circuit and a sync detection signal output from the sync detection circuit, The superimposing means is controlled so that the superimposing means does not superimpose the sweep signal on the AFC signal until a certain time elapses after the detection signal indicates that the synchronous detecting section is in the synchronous state. At the same time, the pseudo sync detection signal indicates that the sync detection section is not in the pseudo sync state, and the sync detection signal also indicates that the sync detection section is in the sync state. Controlling the superimposing means so as not to superimpose the sweep signal on the AFC signal,
In other cases, the AFC is performed by the superimposing means.
A digital signal demodulating device, comprising: a microcomputer that controls the superimposing means to superimpose the sweep signal on a signal. 5. An at least one frequency converter for mixing a digitally modulated reception signal with an oscillation signal to convert it into an intermediate frequency signal, and synchronously detecting the intermediate frequency signal obtained by the conversion with a carrier signal. It has a synchronous detection section for outputting and an error correction circuit inside thereof, reproduces data from the signal output from the synchronous detection section, and corrects the error of the data obtained by reproduction by the error correction circuit. A data reproducing circuit for detecting a frequency fluctuation and a phase fluctuation of the intermediate frequency signal from the signal output from the synchronous detection unit, and an error signal (hereinafter referred to as an AFC signal) corresponding to the frequency fluctuation and the phase. An error detection circuit that generates an error signal (hereinafter, referred to as a PLL signal) according to a variation, and the generated AFC signal is fed back to the frequency conversion unit to generate the AFC signal. Frequency control means for controlling the oscillation frequency of the oscillation signal in the frequency conversion section, and the generated PLL signal is fed back to the synchronous detection section, and the phase of the carrier signal in the synchronous detection section is returned by the PLL signal. In the digital signal demodulating device including a phase control unit for controlling, the error correction circuit corrects an error of the data obtained by reproduction, and further, based on an error rate of the data, the synchronization is performed. Detects whether the detection unit is in the pseudo synchronization state, outputs the detection result as a pseudo synchronization detection signal, and determines whether the synchronization detection unit is in the synchronization state from the signal output from the synchronization detection unit. Detection circuit, which outputs the detection result as a synchronization detection signal, a sweep signal generation circuit which generates a sweep signal, and feedback to the frequency conversion section. Superimposing means for superimposing the generated sweep signal on the AFC signal, the pseudo sync detection signal output from the error correction circuit and the superimposing means for superimposing the sweep signal on the AFC signal. And a state signal indicating that the state signal
Before the lapse of a certain time after indicating that the sweep signal is not superimposed on the C signal, the synchronous detection unit is not in the pseudo synchronous state in place of the pseudo synchronous detection signal output from the error correction circuit. Is output as the pseudo-synchronization detection signal, and after the elapse of the time, the pseudo-synchronization detection signal output from the error correction circuit is output as it is, and the signal control means outputs the signal. A pseudo sync detection signal and a sync detection signal output from the sync detection circuit are input, the pseudo sync detection signal indicates that the sync detection unit is not in the pseudo sync state, and the sync detection signal is the sync When the detection unit indicates that it is in the synchronous state, the superimposing unit is controlled so as not to superimpose the sweep signal on the AFC signal in the superimposing unit, and otherwise. Case, digital signal demodulating apparatus characterized in that a, a superposition control means for controlling said superimposing means so as to perform superimposition of the sweep signal to the AFC signal in the superposing unit.