JP2890992B2 - Satellite receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a satellite broadcast receiver for receiving broadcast satellites and communication satellites, and more particularly, to a television signal which has been subjected to analog angle modulation and a compressed, multiplexed and digitally modulated television signal. The present invention relates to a satellite broadcasting receiver for receiving.

[0002]

2. Description of the Related Art Broadcasting services using geostationary satellites include multi-channel P in addition to conventional analog television broadcasting.
Commercial music broadcasting and multi-channel digital television broadcasting are being planned. In contrast to the conventional analog angle modulation method, a direct modulation method of directly modulating a carrier with a multi-channel signal is used to increase the use efficiency of radio waves. Therefore, to receive both modulation schemes, respective demodulators are required. As demodulation of the conventional analog angle modulation, demodulation generally using a phase locked droop (PLL) is well known. JP-A-63-30049 discloses an example of demodulation of a digital modulation signal such as an MSK modulation wave or a QPSK modulation wave of a direct modulation system for directly modulating a carrier.

In a demodulation method using a synchronous detection method for demodulating a received MSK signal, a method of reproducing a carrier wave as a reference signal is important, and a capture range of a carrier reproduction circuit is designed to be narrow to about several hundred KHz. After receiving the signal from the satellite, a converter is installed immediately after the antenna to reduce the cable loss, and the converter converts the signal to the first intermediate frequency.
Since a frequency of about MHz is expected, a pull-in circuit is required to tune the carrier reproduction circuit. JP-A-63-
FIG. 6 shows an example of Japanese Patent Publication No. 30049. In FIG. 6 , 1
00 is an input terminal, 2 is a first voltage controlled oscillator (local oscillator), 3 is a first mixer, 4 is a second voltage controlled oscillator (local oscillator), 5 is a second mixer, and 6 is a band. 7 is a first multiplier, 8 is a second multiplier, 9 is a reference oscillator, 10 is a π / 2 phase shifter, and 11 is a first multiplier.
A low-pass filter (LPF), 12 is a second LPF,
13 is a first determination circuit, 14 is a second determination circuit, 15 is an inversion circuit, 16 is a digital signal processing circuit, 101 is a reproduction (demodulation) signal output terminal, 18 is a third multiplier, and 19 is a fourth multiplier. , 20 is a loop filter, 21 is a clock recovery circuit, 22 is an MSK demodulation circuit, and 23 is carrier wave phase error information. The first intermediate frequency output from the converter (not shown) is frequency-converted to a second intermediate frequency by a first frequency conversion circuit including a first local oscillator 2 and a first mixer 3, and 2 local oscillators 4 and 2
The third frequency conversion circuit comprising the mixer 5
, And the carrier frequency is lowered by the double heterodyne method, and is input to the MSK demodulation circuit 22 to demodulate the MSK signal. Although detailed operations are omitted here, the in-phase carrier and the quadrature carrier generated by the reference oscillator 9 and the π / 2 phase shifter 10 modulating the modulation signal input to the MSK demodulation circuit 22, the first multiplier 7 and the second Synchronous detection is performed by multiplying by the multipliers 8 respectively, the in-phase component output and the quadrature component output are multiplied by the third multiplier 18, and furthermore, the clock signal reproduced by the clock reproduction circuit 21 is multiplied by the fourth multiplier 19. The multiplication is performed to detect a carrier phase error between the second intermediate frequency and the output of the reference oscillator 9 and to control the second local oscillator 4 so that the phase difference between the third intermediate frequency and the output of the reference oscillator 9 is constant. This constitutes a negative feedback loop for setting a value. According to this example, since the crystal oscillator having high frequency stability is used as the reference oscillator 9, even if the frequency of the first local oscillator 2 drifts due to ambient temperature fluctuation or temperature fluctuation due to energization, the above-described negative feedback is performed. The third intermediate frequency is stabilized by the loop.

[0004] An example of a PLL demodulation circuit for demodulating a conventional analog angle modulation in FIG. 7 , the same functional blocks as those in FIG. 5 are denoted by the same reference numerals. A detailed description of the operation of the PLL is omitted here. 24 is a high pass filter (HPF), 25 is an RF amplifier, 26 is a variable band pass filter (BPF), 27 is an RF auto gain control (AGC) amplifier, 28 is an IF amplifier, 29 is an IFAGC amplifier, 30 is a phase comparator, 31
Is a loop filter, 32 is a loop amplifier, 33 is a voltage controlled oscillator, 35 is an integrator, 36 is a comparator, 37 is a reference voltage, 38 is a tuning PLL circuit, 39 is a microcomputer, 40 is a PLL demodulation circuit, 41 Is a buffer amplifier,
Reference numeral 42 denotes a descrambling information extraction circuit, 43 denotes a descrambler, 102 denotes a demodulated signal output terminal, and 103 denotes a demodulated signal output terminal from which the descrambler has been released. IFAGC
The amplifier 29, the phase comparator 30, the loop filter 31, the loop amplifier 32, and the voltage controlled oscillator 33 constitute a PLL demodulation circuit 40. To stabilize the second intermediate frequency, an error voltage is output by comparing a low-frequency component obtained by integrating a demodulated signal obtained by branching the output of the loop amplifier 32 with an integrator 35 and a reference voltage 37. The local oscillator 2 is controlled by the error voltage to form a negative feedback loop so that the second intermediate frequency becomes constant. In the figure, for a scrambled signal, descrambling information extraction circuit 42 extracts descrambling information superimposed on, for example, PCM audio data, and descrambles the signal by descrambler 43.

[0005]

In the above conventional example, both the demodulator for the analog angle modulation signal and the demodulator for the digital modulation signal have the second intermediate frequency (or the third intermediate frequency) so that the input frequency is constant. It has means for suppressing fluctuation. However, the demodulator of the digital modulation signal is insufficient for suppressing the drift of the converter and deteriorates the characteristics. Also, since the configuration of the negative feedback loop that stabilizes the input frequency of the demodulator is different between the demodulator of the analog angle modulation signal and the demodulator of the digital modulation signal, the frequency stabilization control is applied to the satellite broadcasting receiver equipped with both demodulation methods. There was a problem that management of the information became complicated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a demodulation of a digital modulation without deteriorating demodulation characteristics even with a large drift like a converter. It is an object of the present invention to provide a satellite broadcast receiver in which the frequency stabilization control of both demodulation methods of a receiver is simplified.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a narrow-band negative feedback loop for controlling the second local oscillator 4 so as to make the phase difference between the third intermediate frequency and the output of the reference oscillator 9 constant. This is achieved separately by forming a wideband negative feedback loop.

That is, a synchronous state judging means for the demodulator of the digital modulation signal, a negative feedback loop for feeding back the low frequency component of the phase difference error signal of the demodulator for the digital modulation signal to the (first) local oscillator, A means for sweeping the oscillation frequency of the oscillator is provided, and when the demodulator of the digital modulation signal is in the asynchronous state, the negative feedback loop is disconnected, the local oscillator is set in the running state, and the demodulator of the digital modulation signal is in the synchronization state. Time is achieved by connecting a negative feedback loop and controlling the local oscillator with the same negative feedback loop.

[0009]

When the carrier frequency of the digital modulation signal deviates from the center due to the drift of the converter, the digital modulation signal cannot follow the narrow-band negative feedback loop of the demodulator, but the local oscillator is generated by the low-frequency component of the phase difference error signal. , It is possible to perform broadband tracking. Also, if the carrier frequency of the digitally modulated signal is off-center in the initial state or channel selection, etc., and the demodulator is in the asynchronous state, the negative feedback loop is cut off, the oscillation frequency of the local oscillator is swept, and the carrier signal is converted to a digital signal. By displacing to the frequency that can be pulled in the narrowband negative feedback loop of the demodulator of the modulation signal and connecting the negative feedback loop when the demodulator reaches the synchronization state,
Broadband tracking is performed as described above.

According to the present invention, as a result, the carrier can be demodulated stably without deteriorating the demodulation characteristics even when the frequency of the carrier greatly shifts due to the drift of the converter. Further, since the negative feedback loop for demodulating the analog angle modulation signal and the demodulation for digital modulation are fed back to the same local oscillator, the switching by the channel selection circuit is simplified.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a satellite broadcast receiver as one embodiment of the present invention. In FIG. 1, FIG.
The same symbols are used for the same functional blocks as in FIG. Also, the HPF 24, the RF amplifier 25, the variable BPF 26, the RFAGC amplifier 27, and the IF amplifier 28 shown in FIG.
Is abbreviated. In addition, 34 is a demodulator of a digital modulation signal, 44 and 48 are switches, 45 is a synchronization state determination circuit,
46 is a comparator, 47 is a reference voltage, and 49 is an integrator.

In this embodiment, a demodulator 3 for digitally modulated signals is used.
4 (for example, the mixer 5 of FIG. 6 of the related art, the local oscillator 4 and the demodulator 22), the low-frequency component of the phase error information obtained by integrating the phase error information obtained by the integrator 48 and the reference voltage. 47 to generate an error voltage,
This constitutes a negative feedback loop to the local oscillator 2 via the microcomputer 39. This negative feedback loop is connected and disconnected by a switch 44 controlled by a synchronization state determination circuit 45. That is, the switch 44 is connected to the synchronization state determination circuit 45.
Accordingly, the demodulator 34 of the digital modulation signal is in a disconnected state in an asynchronous state, and is in a connected state in a synchronous state. As a result, in the synchronized state, since the fluctuation of the low frequency component of the phase error information corresponds to the frequency fluctuation input to the demodulator,
The low-speed but wide-band control is performed on the high-speed and narrow-band negative feedback loop of the digital modulation signal demodulator 34 described in the conventional example, and the input frequency of the demodulator can be stabilized. The selection of the negative feedback loop by the demodulator 34 of the digital modulation signal and the negative feedback loop by the demodulator 40 of the analog angle modulation signal is performed by the switch 48 in accordance with the switching signal of the negative feedback loop from the microcomputer.

FIG. 2 is a block diagram showing another embodiment of the present invention. Although the operation principle is the same as that of FIG. 1, the output of the synchronization state discrimination circuit 45 is branched and inputted to the microcomputer 39 for controlling channel selection. That is, the microcomputer stops the control of the local oscillator by the negative feedback when the demodulator is in the asynchronous state when there is no output from the synchronous state determination circuit 45,
The control voltage of the local oscillator is run to bring the demodulator 34 of the digital modulation signal into a synchronized state.

FIG. 3 is a block diagram showing an embodiment of a descrambler-compatible satellite broadcast receiver using the present invention. The operation principle is the same as in FIGS. 1 and 2 except that the switch 50 and the output terminal 1 to the descrambler (not shown) are used.
04 is provided. The difference from FIG. 6 of the conventional example is that the descrambling information extraction circuit is arranged in a descrambler, and the demodulator outputs the demodulators 34 of the digital modulation signal and the demodulator 40 of the analog angle modulation signal from the microcomputer to the descrambler. The output is selectively output by the switch 50 in conjunction with the switch 48 by the switching signal of the negative feedback loop.

FIG. 4 is a block diagram showing one embodiment of a descrambler-compatible satellite broadcast receiver using the present invention. Although the operation principle is the same as the case of FIGS. 1, 2 and 3, buffer amplifiers 41a and b, descrambling information extraction circuits 42a and 42b, switches 51 and 52,
A baseband output terminal 105 to the descrambler and a descrambling information output terminal 106 to the descrambler are provided. 3 is different from FIG. 3 in that it includes descrambling information extraction circuits 42a and 42b corresponding to the digital modulation signal and the analog modulation signal, respectively. When the digital modulation signal and the analog modulation signal have the same scrambling format in the baseband, descrambling can be performed by one descrambler. Correspondingly, the demodulated outputs of the demodulator 34 of the digital modulation signal and the demodulator 40 of the analog angle modulation signal and the descrambling information are switched by the switch 51 and the switch 52 by the switch signal of the negative feedback loop switching signal from the microcomputer. The output is selectively output in conjunction with 48 and supplied to the descrambler.

FIG. 5 is a block diagram showing an embodiment of a satellite broadcast receiver corresponding to a multiplexed and compressed digital modulation signal using the present invention. Although the operation principle is the same as that of the case of FIG. 4, a multiplexed signal selection circuit 53 and a decompression circuit 54 are provided after the digital modulation signal demodulator 34 in order to perform signal processing of the multiplexed and compressed digital modulation signal. . A desired signal is selected from a multiplexed signal that is a demodulated output of the digital signal demodulator 34 by a multiplexed signal selection circuit 53, and a decompression circuit 54 restores a compressed signal.

[0018]

According to the present invention, even if the carrier frequency of the digital modulation signal is greatly deviated from the center, the demodulation characteristics are not deteriorated, and the negative feedback loop for demodulating the analog angle modulation signal and demodulating the digital modulation is provided. Are fed back to the same local oscillator, so that switching by the tuning circuit is simplified. As a result, for example, it is possible to achieve a stable and high-performance satellite broadcast receiver that receives a television signal modulated by analog angle using a broadcasting satellite or a communication satellite and a television signal modulated by compression and multiplexing. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a block diagram showing a conventional example.

[Explanation of symbols]

2 local oscillator, 3 mixer, 6 BPF, 34 demodulator for digital modulation signal, 40 demodulator for analog angle modulation, 35, 49 integrator, 46, 36 comparator, 47,
37: Reference voltage source, 44, 48: Switch, 45: Synchronization state discriminator.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04B 1/16 H04H 1/00

Claims (5)

(57) [Claims] 1. A mixer for converting a first intermediate frequency into a second intermediate frequency, a local oscillator, a first demodulator for demodulating an analog angle modulation signal, and a second demodulator for demodulating a digital modulation signal. In a satellite broadcast receiver including a demodulator and a descrambler for restoring a scrambled demodulated signal, a second demodulator includes a carrier recovery circuit for generating a carrier recovery phase error signal, and a synchronous detector having a synchronization state determination unit. A first negative feedback loop for detecting the frequency fluctuation of the second intermediate frequency signal from the first demodulator and feeding back to the local oscillator, and the frequency fluctuation of the second intermediate frequency signal from the second demodulator. And a means for selecting a first negative feedback loop and a second negative feedback loop, wherein the second negative feedback loop is used to determine the synchronization state when the second negative feedback loop is selected. Yo A connection and disconnection of the control of the local oscillator by the second negative feedback loop. 2. The method according to claim 1, further comprising means for running the oscillation frequency of the local oscillator, wherein the synchronous state determining means disconnects the second negative feedback loop when the second negative feedback loop is selected. A satellite broadcast receiver comprising: running the oscillation frequency of a local oscillator; stopping the running of the oscillation frequency of the local oscillator in a synchronization detection state; and connecting a second negative feedback loop. 3. A means according to claim 1, wherein said selecting means for selectively outputting the outputs of said one demodulator and said second demodulator to a descrambler selects a first negative feedback loop and a second negative feedback loop. A satellite broadcast receiver that operates in conjunction with a satellite broadcast receiver. 4. A satellite broadcast receiving apparatus according to claim 2, wherein the selectively output signals from the first demodulator and the second demodulator to the descrambler are a baseband signal and scramble information. Machine. 5. The method according to claim 1, wherein the second demodulator is a compression,
A satellite broadcast receiver comprising means for selecting and expanding a multiplexed television signal.