JPH0713527A - Display device and driving device for display device - Google Patents

Abstract

PURPOSE:To decrease the number of driving voltage input terminals and the number of elements of a source driver. CONSTITUTION:A decoder circuit 8 relating to one source line in the source driver 2 converts N-bits of digital image signals supplied via a shift register circuit 5, a bus transistor circuit 6 and a latch circuit 7 to 2N/2<m> pieces of decimal signals and m-bits of digital signals. A voltage level selection circuit 9 and output signal selection circuit 10 relating to the source line selects one driving voltage from total level number 2N of the driving voltages divided to 2<m> times by each level number 2N/2<m> and successively inputted during one horizontal scanning period in accordance with 2N/2<m> pieces of decimal signals and m-bits of digital signals from the decoder circuit 8 and outputs this voltage to the source line. The level number 2N/2<m> of the driving voltages fewer than the required level number 2N are handled in such a manner, by which the number of the driving voltage input terminals and the number of the elements of the source driver 2 are decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device and a method for driving a flat panel display device, and more particularly, to a floor corresponding to a digital value given by a digital image signal and represented by the digital image signal. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device that performs a key display and a driving method thereof.

[0002]

2. Description of the Related Art In the case of driving a liquid crystal display device, the response speed of liquid crystal is very low as compared with the response speed of a fluorescent material used in a CRT (cathode ray tube) display device. A circuit is used.

That is, in the liquid crystal display drive circuit, the image signals sent from time to time are not given to each pixel as they are, but the image signal voltage sampled corresponding to each pixel within one horizontal scanning period is horizontally scanned. It is held during the period, and is output to all pixels all at once at the beginning of the next horizontal scanning period or at an appropriate time in the middle thereof. Then, when the output of the image signal voltage to each pixel is started, the output voltage (image signal voltage) is held for a time sufficiently longer than the response time of the liquid crystal.

In the conventional liquid crystal display drive circuit, a capacitor is used to hold the above-mentioned output image signal voltage. FIG. 8 shows the conventional liquid crystal display drive circuit described above.
FIG. 6 is a circuit diagram of a source driver that supplies a drive voltage to N pixels on one scan line selected by a scan signal. Further, as shown in FIG. 9, the drive voltage output circuit for supplying the drive voltage to the n-th pixel in the source driver has an analog switch SW ₁ and a sampling capacitor C as shown in FIG.
It is composed of _SMP , analog switch SW ₂ , hold capacitor C _H and output buffer amplifier A. Also,
FIG. 10 is an operation term chart in the source driver shown in FIG. Hereinafter, according to FIG. 8 to FIG.
The operation of the source driver in the conventional liquid crystal display drive circuit will be described.

The analog image signal V _S input to each analog switch SW ₁ is a sampling clock signal T _SMP1 corresponding to each of N pixels on one scanning line selected for each horizontal synchronizing signal H _{syn. ..} are sequentially sampled by the analog switch SW ₁ in the “on” state in synchronization with T _SMPN . Then, the instantaneous voltages V _{SMP1 to} V _SMPN at each sampling point of the analog image signal V _S sampled in this _manner are _converted into sampling capacitors C 1.
_Applied to _SMP . As a result, the nth sampling capacitor C _SMP is charged by the instantaneous voltage V _SMPn in the analog image signal V _S and its voltage is held.

During one cycle of the horizontal synchronizing signal H _syn , the voltages V _{SMP1 to} V _SMPN sampled as described above and held in the respective sampling capacitors C _SMP.
Is synchronized with the output pulse OE which is given to all the analog switches SW ₂ simultaneously, and each sampling capacitor C
Is moved to the hold capacitor C _H corresponding from _SMP, is outputted to the source line O ₁ ~ O _N connected to the pixels via a buffer amplifier A.

However, in the liquid crystal display drive circuit for supplying a drive voltage to each pixel based on the analog image signal V _S as described above, the following will be described in order to increase the capacity and definition of the liquid crystal display panel. It turns out that there are some problems like this.

(1) The sampling capacitor C _SMP
When transferring the electric charge charged to the Hall capacitor C _H ,
The following formula is established between the voltage V _H appearing in the Hall capacitor C _H and the sampled voltage V _SMP .

[Equation 1]

Therefore, the hold capacitor C _H
In order for the voltage V _H held by V _SMP to be approximately the same value as the sampled instantaneous voltage V _SMP , the capacitances of the sampling capacitor C _SMP and the holding capacitor C _H must satisfy the condition C _SMP >> C _H. . That is, it is necessary to increase the capacity of the sampling capacitor C _SMP to some extent or more. However, if the capacitance of the sampling capacitor C _SMP is too large, it is necessary to take a long time (one sampling time) for charging the sampling capacitor C _SMP .

However, the number of pixels to which a drive voltage is to be supplied in one horizontal scanning period is increasing with the recent increase in size and definition of liquid crystal display devices, and one sampling time is shortened in inverse proportion to this. There is a need. That is, the analog sampling method as described above has a limit in increasing the size and the definition of the liquid crystal display device.

(2) The analog image signal V _S is supplied to the source driver through the bus line. Therefore, the frequency band of the analog image signal becomes wider and the wiring capacity of the bus line becomes larger as the liquid crystal display device becomes larger and finer. Therefore, a circuit for supplying an analog image signal to the source driver needs a wide band power amplifier, which causes an increase in cost.

(3) In the case of providing a plurality of analog image signal supply bus lines as in the case of color display by RGB video signals, the above-mentioned wide band is provided along with the increase in capacity and definition of the liquid crystal display panel. The power amplifier is required to have extremely high performance and quality such that there is no phase difference between a plurality of output analog image signals and variation in amplitude characteristics and frequency characteristics does not occur.

(4) Unlike the display on the CRT, in the drive circuit for the matrix type liquid crystal display device, an image is displayed on the pixels arranged in a matrix based on the analog image signal sampled in synchronization with the clock. . In that case, it is very difficult to ensure the accuracy of the sampling time for the analog image signal because the delay of the signal in the drive voltage output circuit including the delay in the bus line is unavoidable. In particular, in the case of computer graphics in which the relationship between the sampling time and the address of the display pixel in the analog image signal must be closely matched, the signal delay and the deterioration of the frequency characteristic which occur in the drive voltage output circuit. Displacement of the display position of the image, blurring of the image, and the like caused by the above are important problems.

Many of the problems that occur when supplying a driving voltage to a pixel based on the analog image signal V _S are solved by using a digital image signal. When a driving voltage is supplied to the pixel based on the digital image signal, a source driver as shown in FIG. 11 is used.

The source driver for supplying the drive voltage to the pixel based on the digital image signal will be described below. Here, for simplification, the digital image signal is composed of four values y _{0 to} y ₃ represented by 2 bits (D ₁ , D ₀ ), and each pixel is supplied from an external power source. 4
It is assumed that any one of the drive voltages V _{0 to} V ₃ of one level is supplied.

The source driver shown in FIG. 11 has N driving voltage output circuits and supplies a driving voltage to N pixels. Then, as shown in FIG. 12, the n-th drive voltage output circuit in this source driver has two first-stage D circuits to which the respective bit signals of the digital image signals (D ₁ , D ₀ ) are input. Flip-flops (hereinafter referred to as sampling flip-flops) M _SMP , two second-stage D flip-flops (hereinafter referred to as hold flip-flops) M _H , one decoder DEC and four analog switches It is composed of ASW _{0 to} ASW ₃ .

The drive voltage output circuit operates as follows to output the drive voltage to the source line O _n . The two sampling flip-flops M _SMP have the digital image signal D ₀ , at the rising time of the sampling pulse T _SNPn .
Capture and hold D ₁ . Thus, the digital image signals D ₀ and D ₁ held in the sampling flip-flop M _SMP are taken in by the hold flip-flop M _H in synchronization with the output pulse OE at the time when the sampling in one horizontal scanning period is completed. Output to the decoder DEC.

Then, the decoder DEC supplies each of the four values y _{0 to} y ₃ obtained by decoding the input 2-bit digital image signal to the corresponding analog switch ASW _{0 to} ASW ₃ . . Then, the analog switches ASW _{0 to} AS are selected according to the four values y _{0 to} y _3.
Any one becomes conductive of W _3, it is the driving voltage supplied to the analog switch and the introducing of the driving voltage V ₀ ~V ₃ supplied from the outside is outputted to the source line O _n.

[0019]

According to such a source driver which supplies a driving voltage to a pixel based on a digital image signal, the above problems (1) to (4) are solved. However, it has the following problems.

As the gradation of the image displayed on the pixel increases and the number of bits of the digital image signal increases, a D flip-flop and a decoder D forming a source driver are formed.
The size of EC etc. increases rapidly. As a result, the circuit area and the number of elements increase, and the non-defective rate also decreases. For example, if the circuit of the decoder DEC that converts a 4-bit digital image signal into 16 decimal signals is composed of MOS (metal oxide semiconductor) transistors, 104 elements are required.

Further, as the number of bits of the digital image signal increases, the number of analog switches ASW increases with a power of "2". Since the analog switch ASW is an on-resistance inserted between the voltage source of the drive voltage and the source line O, its size is preferably large, and an increase in the number thereof causes an extreme increase in circuit area. .

Further, when the decoder DEC and the analog switch ASW are formed in the source driver by using a polycrystalline silicon thin film transistor, a driving voltage required for displaying a multi-gradation image on the pixel of the display section. It is necessary to prepare as many input terminals as the total number of levels (that is, 2 ⁴ = 16 in the case of display by a 4-bit digital image signal).

Therefore, an object of the present invention is to provide a display device and a driving method thereof capable of reducing the number of elements of a source driver when performing gradation display based on a digital image signal and significantly reducing the circuit area accordingly. To provide.

[0024]

In order to achieve the above object, the invention according to claim 1 provides a display section having pixels arranged in a matrix and switching elements connected to each of the pixels, and the above switching. A first driving circuit for turning on the switching element by applying a scanning voltage to a control terminal of the element through a scanning line, and a driving voltage of a level corresponding to a digital image signal to the input terminal of the switching element in the on state. In a display device having a second drive circuit which supplies a pixel via a line to display pixels connected to the switching element, the second drive circuit decodes an input digital image signal to perform the first drive. A period for selecting one of the periods obtained by dividing one horizontal scanning period in which the scanning voltage is applied to one scanning line by the circuit into a predetermined number. A decoder unit for generating a selection signal and a level selection signal for selecting any one of a plurality of levels of driving voltage input in each period in a predetermined procedure, and a plurality of grayscale levels for each pixel of the display unit. The drive voltage of a predetermined level required for displaying an image is taken in every one of the predetermined number of levels for each period, and any one of a plurality of levels of drive voltage taken in for each period. A voltage level selection unit that selects one based on the level selection signal from the decoder unit, and the drive voltage selected by the voltage level selection unit for each of the periods described above are sequentially taken in, and one of the periods is selected. One of them is selected based on the period selection signal from the decoder section, and the drive voltage fetched from the voltage level selection section during this selected period is output to the signal line associated with the pixel to be displayed. It is characterized by comprising an output signal selection part.

The invention according to claim 2 is the display device according to claim 1, wherein the switching element of the display section, the first drive circuit, the decoder section, the voltage level selection section, and The second driving circuit including the output signal selection unit is integrally formed on the same substrate by using an amorphous semiconductor.

According to a third aspect of the present invention, the pixels arranged in a matrix and the display section having the switching element connected to each of the pixels, and the control terminal of the switching element are scanned through the scanning line. A first drive circuit for applying a voltage to turn on the switching element, and a drive voltage of a level corresponding to a digital image signal is supplied to the input terminal of the switching element in the on state via a signal line to the switching element. A method of driving a display device having a second drive circuit for displaying connected pixels, wherein the second drive circuit decodes an input digital image signal and one scan is performed by the first drive circuit. A period selection signal for selecting one of the periods obtained by dividing one horizontal scanning period in which a scanning voltage is applied to a line into a predetermined number, and the above periods It is necessary to generate a level selection signal for selecting one of the input driving voltages of a plurality of levels by a predetermined procedure, and further, to display a multi-gradation image on each pixel of the display section. The driving voltage of a predetermined level is taken in every one of the predetermined number of times for each period, and one of the driving voltages of the plurality of levels taken in for each period is selected as the level selection signal. Based on the period selection signal, and further outputs any one of the drive voltages of the levels selected for each period to the signal line associated with the pixel to be displayed. It is characterized by that.

[0027]

In the invention according to claim 1 and claim 2, the first
When the scanning voltage is supplied to one scanning line by the driving circuit, the scanning voltage is applied to the control terminal of the switching element connected to the pixels arranged in a matrix in the display section through the scanning line. Then, the switching element is turned on.

Then, the second drive circuit operates as follows. That is, first, the decoder section decodes the input digital image signal to generate a period selection signal and a level selection signal in a predetermined procedure. Then, the driving voltage of a predetermined level required for displaying an image of a plurality of gradations on each pixel of the display unit by the voltage level selection unit is obtained by dividing one horizontal scanning period into a predetermined number. In the above, each one of the predetermined number of levels is taken in, and one of the driving voltages of a plurality of levels taken in each of the periods is selected based on the level selection signal from the decoder section.

The drive voltage selected in each of the above periods is sequentially taken into the output signal selection section. The output signal selection unit selects any one of the periods based on the period selection signal from the decoder unit,
The drive voltage taken in during the selected period is output to the signal line associated with the pixel to be displayed.

In this manner, the decoder unit, the voltage level selection unit, and the output signal selection unit in the second drive circuit are used to display the predetermined gradation required for displaying an image of a plurality of gradations on each pixel of the display unit. The drive voltage of the level number obtained by dividing the number of levels by the predetermined number is handled, and the drive voltage of the level to be output to the signal line is selected from the drive voltage of the predetermined level number.

[0031]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. In the following description, a matrix type liquid crystal display device will be described as an example, but the present invention can be applied to other display devices. In the following description, a case where a polycrystalline silicon thin film transistor is used as a circuit element will be described as an example, but the present invention can be applied to a display device using a thin film transistor made of another material.

FIG. 1 is a block diagram showing the structure of the source driver in the display device of the present invention. Also, FIG.
FIG. 2 is a schematic configuration diagram of a display device having the source driver shown in FIG. 1. Prior to the description of the present invention with reference to FIG. 1, the display device according to the present invention will be described below with reference to FIG.

As shown in FIG. 7, the display unit 1 has M × N pixels P (j, i) (j = 1, 2, ..., M;) arranged in M rows and N columns.
, N) and switching elements T (j, i) (j = 1,2, ..., M; i = 1, 2) connected to the pixel P (j, i).
2, ..., N). The display unit 1 is driven by the source driver 2 and the gate driver 3.

One end of each of the plurality of signal lines O _i (i = 1, 2, ..., N) arranged in parallel in the area of the display unit 1 has an output terminal S (i) (of the source driver 2). i = 1, 2, ..., N). Further, the input terminals of the switching elements T (j, i) arranged in the same row are connected to the signal line O _i . Similarly, one end of each of the plurality of scanning lines L _j (j = 1, 2, ..., M) arranged in parallel to and orthogonal to the signal line O _i has an output terminal G (j) (of the gate driver 3 j = 1,
2, ..., M), and the control terminals of the switching elements T (j, i) arranged in the same row are connected to each scanning line L _i .

As the switching element T (j, i),
Thin film transistors (TFTs) are used. Hereinafter, the signal line O _i is called a source line and the scanning line L _j is called a gate line.

A voltage of level "H" is sequentially output from the output terminal G (j) of the gate driver 3 to the gate line L _j after a specific period. Here, the specific period is referred to as one horizontal scanning period jH (j = 1, 2, ..., M), and the time obtained by adding the one horizontal scanning period jH to all “j” is one vertical scanning period. Call it a period.

When a voltage of level "H" (hereinafter, this voltage is referred to as a scan voltage) is applied from the output terminal G (j) of the gate driver 3 to the gate line L _j , the scan voltage is applied to the gate line L _j. A thin film transistor T connected to Lj
When applied to the gate terminal of (j, i), the thin film transistor T (j, i) is turned on. In this way “on”
The voltage supplied from the output terminal S (i) of the source driver 2 through the source line O _i to the pixel P (j, i) connected to the drain terminal of the thin film transistor T (j, i) in the state. A voltage corresponding to (hereinafter, this voltage is referred to as a drive voltage) is charged. Thus, the level of the voltage charged in the pixel P (j, i) is maintained during one vertical scanning period,
A constant level voltage is applied to (j, i).

In this case, according to the present invention, the structure of the source driver 2 for supplying a voltage to the electrode of the pixel P (j, i) connected to the thin film transistor T (j, i) in the "on" state and the structure thereof The present invention relates to a voltage supply method.

The source driver 2 in the present invention supplies a drive voltage to the display section 1 as follows. That is,
When the thin film transistor T (j, i) connected to the pixel P (j, i) is turned on by the scanning of the gate driver 3, the thin film transistor T turned on by the source driver 2 The period for supplying the drive voltage based on the digital image signal to (j, i) is divided into a plurality of periods. Then, for each divided period, the pixel P (j, i)
A driving voltage of a predetermined level required for displaying an image of a plurality of gradations is sequentially input to the source driver 2 by the number of levels which is 1 / the number of divided times. Since the source driver 2 selects any one of the plurality of levels of the driving voltage sequentially input based on the digital image signal, and supplies it to the thin film transistor T (j, i) in the “on” state. is there. Hereinafter, the configuration of the source driver 2 will be described in detail.

FIG. 1 is a block diagram showing the structure of the source driver 2 according to the present invention. Source driver 2
Is roughly composed of a shift register circuit 5, a pass transistor circuit 6, a latch circuit 7, a decoder circuit 8, a voltage level selection circuit 9 and an output signal selection circuit 10 which are arranged in parallel.

The N-bit digital image signal input to the source driver 2 is sequentially transferred to the latch circuit 7 by sequentially turning on the individual pass transistors forming the pass transistor circuit 6 by the shift register circuit 5. It is sent out and held. In this way, when the latch circuit 7 holds the digital image signal for one horizontal scanning line, the transfer gate becomes conductive in synchronization with the transfer pulse R1, and the digital image for one horizontal scanning line held in the latch circuit 7 is obtained. The signal is transferred to the decoder circuit 8.

In the decoder circuit 8, the digital image signal is converted into 2 ^N / 2 ^m decimal signals and m-bit digital signal as described later. The decimal signal is sent to the voltage level selection circuit 9, while the digital signal is sent to the output signal selection circuit 10.

In the present embodiment, each pixel P (j,
i) is 2 ^N based on the N-bit digital image signal.
Images with gradations shall be displayed. Therefore, originally,
The voltage level selection circuit 9 has 2 ^N levels from an external power supply.
Drive voltage must be input.

However, in the present embodiment, in order to reduce the number of elements of the source driver 2 and make it possible to greatly reduce the circuit area, the number of driving voltage input terminals provided in the source driver 2 is 2 ^N / 2. ^The number is ^m . Then, in the voltage level selection circuit 9 and the output signal selection circuit 10, the total number of levels as described below in detail according to the decimal signal and the digital image signal based on the driving voltage having a small number of levels of 2 ^N / 2 ^m. Any one of the 2 ^N drive voltages is selected and supplied to the display unit 1. Thus, by reducing the number of levels of the drive voltage signal handled by the source driver 2, the number of elements forming the decoder circuit 8, the voltage level selection circuit 9 and the output signal selection circuit 10 is reduced.

The operation of the voltage level selection circuit 9 and the output signal selection circuit 10 will be described below. here,
From the period when the thin film transistor T (j, i) connected to the pixel P (j, i) to be driven is in the “on” state, the latch circuit 7 holds the digital image signal for one horizontal scanning line. A period obtained by subtracting the required period and the period required to generate 2 ^N / 2 ^m decimal signals and m-bit digital signal by the decoder circuit 8 is defined as "T", and this period "T" is 2 ^m. For the time being. Then, the voltage level selection circuit 9 divides the total number of levels 2 ^N by the number of levels 2 ^N / 2 ^m and supplies the drive voltage to the above 2 ^N / 2 ^{m for} each period "T / 2 ^m ".
Sequentially take in from 2 ^m driving voltage input terminals (not shown). Then, from the drive voltage of the number of levels 2 ^N / 2 ^m taken in every "T / 2 ^m " in each of the above periods, one drive voltage is set to 2 ^N / 2 above.
It selects based on the 2 ^m decimal signals and sends it to the output signal selection circuit 10.

In this case, the supply of the driving voltage from the outside is carried out as follows, for example. That is,
A reference voltage with a level number of 2 ^N / 2 ^m is obtained from an external power supply. Then, the reference voltage is sequentially boosted every "T / 2 ^m " in each period to supply the driving voltage of the total number 2 ^N of levels.

The output signal selection circuit 10 is based on the m-bit digital signal from the decoder circuit 8,
A period in which the drive voltage is supplied to the pixel P (j, i) is selected from the above periods "T / 2 ^m ". Then, during this selected period, the drive voltage of the level selected by the voltage level selection circuit 9 is output to the source line O _i . Thus, when the period "T" has elapsed, the drive voltage of one level selected from the drive voltages of the total level number 2 ^N is supplied to the pixel P (j, i) to be driven.

That is, in this embodiment, the above 2 ^N / 2
^{The m number} of decimal signals constitutes the level selection signal, and the m-bit digital signal constitutes the period selection signal.

By configuring the source driver 2 as described above, the decoder circuit 8 for supplying the driving voltage of the level number 2 ⁴ to the pixel P (j, i) based on, for example, a 4-bit digital image signal. Can be realized with 20 transistors.

A specific circuit example of the source driver 2 having the above configuration will be described below. FIG. 2 is a specific circuit diagram of the shift register circuit 5. The shift register circuit 5 is composed of a clocked CMOS (complementary metal oxide semiconductor) inverter and a NOR gate, and has a driving power source V
_{Based on DD} (not shown), the start pulse SP, and the clock pulses P1 and P2, the drive pulse is sequentially output to the individual pass transistors forming the pass transistor circuit 6 by operating according to the timing chart shown in FIG.

The shift register circuit 5 having the above-mentioned configuration sets the voltage of the driving power source V _DD to 18 V and sets the clock pulse P1,
When the pulse voltage of P2 is set to 18V, the clock frequency operates normally at 2 MHz. It should be noted that all the following explanations are based on the above voltage value and frequency value. In the present embodiment, the number of gate lines L _{j and} the number of source lines O _i of the display unit 1 are both 100, and the frame frequency is 60 Hz. Furthermore, the number of bits of the input digital image signal is 4 bits, and the voltage value is 18
V.

As described above, the drive pulses sequentially output from the shift register circuit 5 sequentially turn on the individual pass transistors of the pass transistor circuit 6, and the latched circuit 7 receives the captured N = 4 bit digital image signal. Transfer to. In this way, when the digital image signal for one horizontal scanning line is held in the latch circuit 7,
As described above, the latch circuit 7 transfers the held digital image signal in synchronization with the transfer pulse R1 to the decoder circuit 8. The period from the start of the scanning of the j-th gate line L _{j to} the end of the series of operations up to this point is “T0”.

FIG. 4 is a concrete circuit diagram of the decoder circuit 8, the voltage level selection circuit 9 and the output signal selection circuit 10. The decoder circuit 8 comprises two knot gates 11 and 12 and four NOR gates 13 to 16 as one unit.

In FIG. 4, for example, the above source line O
2 high-order bits of 4-bit digital image signal (G0, G1, G2, G3) input to the decoder circuit 8 for _i
(G0, G1) is the coincidence circuit 2 which constitutes the output signal selection circuit 10 as it is as the digital signal of m = 2 bits.
Input to 1. On the other hand, the lower 2 bits (G2, G3) are used for the NOT gates 11 and 12 and NOR gates 13 to 16.
By ^{2 N / 2 m = 2 4} /2 2 = 4 pieces of decimal signals D0~
Converted to D3. Then, each of the obtained four decimal signals D0 to D3 is input to the gate terminal of any one of the four transistors 17 to 20 constituting the voltage level selection circuit 9.

As a result, any one of the transistors 17 to 20 is turned "on" according to the information of the lower 2 bits (G2, G3) of the digital image signals G0 to G3, and the total number of levels 2 ^N = 2. ⁴ = 16 one of the driving voltages V0, V1, V2, V3 level number ^{2 N / 2 m = 2 4} /2 2 = 4 that is currently input of the driving voltage is selected, the output signal selecting circuit The signal is sent to the pass transistor 22 which constitutes 10.

The output signal selection circuit 10 is composed of the coincidence circuit 21 and the pass transistor 22 as described above. The matching circuit 21 receives m = input from the decoder circuit 8.
When the 2-bit digital signal (B0, B1) and the externally input m = 2-bit digital signal (S1, S2) match, the pass transistor 22 is turned "on" and the voltage is set as described above. The drive voltage selected by the level selection circuit 9 is output to the source line O _i . Here, the matching circuit 21 has a circuit configuration as shown in FIG. 5, and is exclusive when the levels of the digital signals (B0, B1) and the levels of the digital signals (S1, S2) match. The same level "L" signal is output from the OR gates 24 and 25. Therefore, the level "H" is output from the NOR gate 23.
The signal is output and the pass transistor 22 is turned on.

The above-mentioned digital signal of m = 2 bits
(B0, B1) is a signal for setting the above period in which the pass transistor 22 is turned "on". That is, as described above, from the period in which the thin film transistor T (j, i) connected to the pixel P (j, i) to be driven is in the “on” state (that is, one horizontal scanning period) to the period “T0”. The period "T" after subtracting "2 ^m = 2 ² = 4 is divided into periods" T1, T
2, T3, T4 ", and digital signals (B0, B1)
The relationship between and the period during which the pass transistor 22 is in the "on" state is set as shown in Table 1.

[Table 1]

FIG. 6 is a timing chart of each signal during one horizontal scanning period when the j-th gate line L _j is scanned and the switching element T (j, i) is in the “ON” state. Table 2 shows the level of each signal or the driving voltage value at that time.

[Table 2] Hereinafter, according to FIG. 6 and Table 2, the decoder circuit 8,
The operations of the voltage level selection circuit 9 and the output signal selection circuit 10 will be specifically described.

Here, the total number of levels of the drive voltage supplied to the voltage level selection circuit 9 is 2 ^N = 2 ⁴ = 16,
6 and as shown in Table 2, the level number obtained from an external power source ^{2 N / 2 m = 2 4} /2 2 = 4 reference voltages V0 = 0.0 V, V1
= 0.5V, V2 = 1.0V, V3 = 1.5V in each period T1, T
It is supplied as it is for every 2, T3, T4, or it is stepped up by 2V and supplied sequentially.

Now, for example, if the digital image signal (G0, G1, G2, G3) = (0,0,0,0) is input from the latch circuit 7 to the circuit related to the source line O _i in the decoder circuit 8. To do. Then, in the decoder circuit 8, the upper 2 bits of the digital image signal (G0, G1, G2, G3)
(G0, G1) = (0, 0) is sent to the matching circuit 21 of the input signal selection circuit 10 as a digital signal (B1, B2). As a result, the period during which the pass transistor 22 is "on" by the digital signal (B1, B2) = (0, 0) is set to "T1".

Next, the digital image signals (G0, G1,
The lower 2 bits (G2, G3) = (0, 0) of G2, G3) are
By the decoding circuit 8, the decimal signals D0 = 0, D1 = 0,
It is converted into D2 = 0 and D3 = 1. As a result, the transistor 20 among the four transistors 17 to 20 constituting the voltage level selection circuit 9 is turned on, and the drive voltage “V0” supplied to the transistor 20 is applied to the pass transistor 22 of the output signal selection circuit 10. Is entered.

Therefore, the driving voltage V0 (T1) = 0.0V sequentially input from the outside in the above periods T1, T2, T3, T4.
V0 (T2) = 0.5V, V0 (T3) = 1.0V, V0 (T4) =
1.5 is selected and sequentially input to the pass transistor 22.

Meanwhile, from the outside, the matching circuit 21 of the output signal selection circuit 10 is supplied with a period "T" as shown in FIG.
The digital signal (S1, S2) that becomes (0, 0) is input to 1 ". The matching circuit 21 inputs the digital signal (B1, B2) and the digital signal (B1, B2) input from the decoder circuit 8 as described above. This is a circuit that outputs a signal of level "H" when S1 and S2) match.
During the period "T1" in which (1, S2) becomes (0,0) and coincides with the digital signals (B1, B2), the matching circuit 21 outputs a signal of level "H" and the pass transistor 22 is "on". Becomes

As a result, the drive voltage V0 (T1) = 0.0V selected by the transistor 20 of the voltage level selection circuit 9 is output to the source line O _i during the period "T1". Thus, the number of levels sequentially input during the above-mentioned period "T = T1 to T4" in one horizontal scanning period 2 ⁴ = 1
6 driving voltage period T1 0.0V, 0.5V, 1.0V, 1.5V period T2 2.0V, 2.5V, 3.0V, 3.5V period T3 4.0V, 4.5V, 5.5 Only one driving voltage 0.0V is selected from the 0V, 5.5V period T4 6.0V, 6.5V, 7.0V, 7.5V, and the pixel of the display unit 1 is selected through the source line O _i. It is supplied to P (j, i).

It is assumed that, for example, a digital image signal (G0, G1, G2, G3) = (0, 1, 1, 1) is input in the next one horizontal scanning period. Then, the upper 2 bits (G0, G1) = (0, 1) are sent from the decoder circuit 8 to the matching circuit 21 as a digital signal (B1, B2), and the pass transistor 22
The period during which "ON" is set to "T3".

Further, the digital image signal (G0, G
The lower 2 bits (G2, G3) = (1, 1) of (1, G2, G3) are converted by the decoding circuit 8 into the decimal signals D0 = 1, D1 = 0, D2.
= 0, D3 = 0. As a result, the transistor 17 among the four transistors 17 to 20 forming the voltage level selection circuit 9 is turned on, and the transistor 17 is turned on.
Drive voltage “V3” supplied to the output signal selection circuit 1
It is input to the 0 pass transistor 22.

On the other hand, the coincidence circuit 21 of the output signal selection circuit 10 is supplied with the digital signals (S1, S2) which are (0, 1) during the period "T3". Therefore, the digital signals (S1, S2) become (0, 1) and the digital signals (B1, B2
During the period "T3" which coincides with 2), the coincidence circuit 21 outputs a signal of level "H", and the pass transistor 22 is turned "on".

As a result, the drive voltage V3 (T3) = 5.5V selected by the transistor 17 of the voltage level selection circuit 9 is output to the source line O _i during the period "T3". Thus, the digital image signal (G0) is selected from among the driving voltages (0.0V to 7.5V) of the total number of levels 2 ⁴ = 16 which are sequentially input during the period "T = T1 to T4" in the one horizontal scanning period. , G1, G2, G3) = (only one drive voltage 5.5V based on 0,1,1,1) is selected, the pixel P (j of the display unit 1 via the source lines O _i, i ).

Thereafter, in the same manner, in accordance with the input digital image signals (G0, G1, G2, G3), the period "T1 to T4".
Any one of the drive voltages “V0, V1, V2, V3” is selected in any one of the periods and is supplied to the pixel P (j, i) of the display unit 1.

At this time, the decoder circuit 8, the voltage level selection circuit 9, and the output signal selection circuit 10 have the number of levels 2 ⁴ which are sequentially taken in four times in each period "T1, T2, T3, T4". Since it is sufficient to handle the drive voltage of / 2 ² = 4, the number of elements forming each circuit can be reduced and the circuit area can be greatly reduced.

As described above, in this embodiment, when displaying an image of 2 ^N gradations based on a digital image signal having the number of bits N, the number of total levels is 2 for each period obtained by dividing one horizontal scanning period by 2 ^m. taking sequential voltage level selection circuit 9 divides the driving voltage of the ^N level by several 2 ^N / 2 ^m. On the other hand, the decoder circuit 8 converts an N-bit digital image signal into 2 ^N / 2 ^m decimal signals and an m-bit digital image signal. Then, the voltage level selection circuit 9 selects and outputs one driving voltage from the driving voltages of the number of levels 2 ^N / 2 ^m fetched in each period based on the decimal signal from the decoder circuit 8. It is sent to the signal selection circuit 10.

The output signal selection circuit 10 outputs the digital signals (S1, S2) from the outside and the digital signal (B1 from the decoder circuit 8 among the drive voltages sent from the voltage level selection circuit 9 in each period. , B2), the drive voltage sent from the voltage level selection circuit 9 in a specific period is selected and supplied to the pixel P (j, i) via the source line O _i .

[0073] Thus, 1 dividing the horizontal scanning period 2 ^m period, since taking the driving voltage of the total level number 2 ^N in each divided period are level by several 2 ^N / 2 ^m, the decoder circuit 8,
The voltage level selection circuit 9 and the output signal selection circuit 10 do not need to have drive voltage input terminals and elements for handling the driving voltage of the total number of levels 2 ^N , and are sufficient for handling the driving voltage of the number of levels 2 ^N / 2 ^m . Drive voltage input terminals and devices are sufficient. That is, according to the present embodiment, the decoder circuit 8, the voltage level selection circuit 9, and the output signal selection circuit 10 can be composed of 49 transistors per source line O _i . On the other hand, in the case of the source driver of the conventional display device, 120 transistors are required, and the number of circuit elements can be significantly reduced.

Here, the circuit elements constituting the source driver 2, including the thin film transistor T (j, i) connected to the pixel P (j, i), are formed by using a large number of polycrystalline silicon thin film transistors. . This polycrystalline silicon thin film transistor is formed as follows.

First, an amorphous silicon thin film is formed at a substrate temperature of 450 ° C. by a low pressure CVD (chemical vapor deposition) method using disilane as a raw material on a glass substrate having a high strain point as a substrate of the display unit 1. The amorphous silicon thin film thus obtained is annealed in a nitrogen atmosphere at 600 ° C. for 10 hours to be polycrystallized to form the channel, source and drain portions of the transistor. A silicon dioxide thin film is formed on this polycrystalline silicon thin film by the atmospheric pressure CVD method to form a gate insulating film. Next, a polycrystalline silicon thin film is formed by a low pressure CVD method and patterned to form a gate electrode. After that, ions are implanted into the source and drain portions, and activation annealing is performed at 600 ° C. for 20 hours to form an N-type or P-type polycrystalline silicon thin film transistor.

The shift register circuit, the decoder circuit 8,
Specific circuits of the voltage level selection circuit 9 and the output signal selection circuit 10 are not limited to the circuit diagrams shown in FIGS. 2, 4 and 5. Further, the relationship between the upper 2 bits of the digital image signal and the period in which the pass transistor 22 is "on" and the driving voltage value supplied in each period (T1, T2, T3, T4) are shown in Tables 1 and 2. 2 and FIG. 6 are not limited.

[0077]

As is apparent from the above, the display device of the invention according to claim 1 has a decoder section for decoding an input digital image signal to generate a period selection signal and a level selection signal, and one horizontal scanning. A voltage level for sequentially taking in a predetermined number of driving voltages for each period divided by a predetermined number and for selecting one of them based on the level selection signal. The drive voltage selected by the selection unit and the voltage level selection unit is sequentially captured, and the drive voltage captured during the period selected based on the period selection signal is output to the signal line associated with the pixel to be displayed. Since the output signal selection section for performing the above is provided in the second drive circuit, the drive voltage of the above-mentioned predetermined number of levels necessary for displaying an image of a plurality of gradations on the pixels of the display section is output to the signal line. In selecting the can level the drive voltage, the number of the predetermined levels may be handled only the driving voltage of the number of levels divided by the predetermined number.

Therefore, the number of drive voltage input terminals and the number of elements of the second drive circuit can be significantly reduced as compared with the case where the drive voltage of the predetermined level is handled, and the circuit area can be greatly reduced accordingly.

The display device of the invention according to claim 2 is
The second drive circuit including the switching element of the display section, the first drive circuit, the decoder section, the voltage level selection section and the output signal selection section is integrally formed on the same substrate by an amorphous semiconductor. The display device of the invention according to the first aspect can be formed compactly with higher density.

According to a third aspect of the present invention, there is provided a display device driving method, wherein a display unit, a first drive circuit for turning on a switching element of the display unit, and a drive voltage of a level corresponding to a digital image signal are turned on. In a display device having a second drive circuit for supplying the switching element in the state, the second drive circuit decodes an input digital image signal to generate a period selection signal and a level selection signal, and
For each period formed by dividing the horizontal scanning period into a predetermined number, a predetermined number of driving voltages are sequentially taken in by the number of levels of the predetermined number and one of them is selected based on the level selection signal. , Any one of the drive voltages selected for each period is output based on the period selection signal and is output to the signal line associated with the pixel to be displayed. When selecting a drive voltage of a level to be output to the signal line from the drive voltage of the predetermined level necessary for displaying an image of gradation, the second drive circuit divides the predetermined level number by the predetermined number. It is only necessary to handle the drive voltages of the specified levels.

Therefore, according to the present invention, the number of drive voltage input terminals and the number of elements of the second drive circuit in the display device can be significantly reduced as compared with the case where the drive voltage of the predetermined number of levels is handled. Accordingly, the circuit area can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a source driver in a display device of the present invention.

FIG. 2 is a specific circuit diagram of the shift register circuit in FIG.

3 is an operation timing chart of the shift register circuit shown in FIG.

FIG. 4 is a specific circuit diagram of a decoder circuit, a voltage level selection circuit, and an output signal selection circuit in FIG.

5 is a specific circuit diagram of the matching circuit in FIG.

FIG. 6 is a timing chart of each signal during one horizontal scanning period.

FIG. 7 is a schematic configuration diagram of a display device having the source driver shown in FIG.

FIG. 8 is a circuit diagram of a source driver in a conventional liquid crystal display drive circuit.

9 is a circuit diagram of an n-th drive voltage output circuit in the source driver shown in FIG.

10 is an operation timing chart in the source driver shown in FIG.

FIG. 11 is a circuit diagram of a conventional source driver that supplies a drive voltage to a pixel based on a digital image signal.

12 is a circuit diagram of the nth drive voltage output circuit in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Display part, 2 ... Source driver, 3 ... Gate driver, 5 ... Shift register circuit, 6 ... Pass transistor circuit,
7 ... Latch circuit, 8 ... Decoder circuit,
9 ... Voltage level selection circuit, 10 ... Output signal selection circuit, 11, 12 ... Not gate, 13-1
6, 23 ... NOR gate, 17-20 ... Transistor, 21 ... Matching circuit, 22 ... Pass transistor, 24, 25 ... Exclusive OR gate.

Claims (3)

[Claims] 1. A display unit having pixels arranged in a matrix and switching elements connected to each of the pixels, and a scanning voltage applied to a control terminal of the switching element via a scanning line to the switching element. A first drive circuit for turning on the switch, and a drive voltage having a level corresponding to the digital image signal supplied to the input terminal of the switching element in the on state via a signal line to display the pixel connected to the switching element. In a display device having two driving circuits, the second driving circuit decodes an input digital image signal, and one horizontal scanning period in which a scanning voltage is applied to one scanning line by the first driving circuit. A period selection signal for selecting any one of the periods divided by a predetermined number, and a plurality of levels of drive voltage input in each period. A decoder unit that generates a level selection signal for selecting one of them in a predetermined procedure, and a predetermined number of levels of the drive voltage required when displaying an image of a plurality of gradations on each pixel of the display unit. For each of the above periods by a predetermined number of levels, and any one of a plurality of levels of drive voltages fetched for each of the periods is selected based on a level selection signal from the decoder section. A voltage level selection unit and the drive voltage selected for each period by the voltage level selection unit are sequentially taken in, and any one of the periods is selected based on a period selection signal from the decoder unit, A display device, comprising: an output signal selection unit that outputs the drive voltage fetched from the voltage level selection unit to a signal line associated with a pixel to be displayed during the selected period. 2. The display device according to claim 1, wherein the switching element of the display section, the first drive circuit, the second drive including the decoder section, the voltage level selection section, and the output signal selection section. A display device in which a circuit is integrally formed on the same substrate by using an amorphous semiconductor. 3. A display unit having pixels arranged in a matrix and switching elements connected to each of the pixels, and a scanning voltage applied to a control terminal of the switching element via a scanning line to the switching element. A first drive circuit for turning on the switch and a drive voltage of a level corresponding to the digital image signal to the input terminal of the switching element in the on state via a signal line to display the pixel connected to the switching element. A driving method of a display device having two driving circuits, wherein the second driving circuit decodes an input digital image signal, and a scanning voltage is applied to one scanning line by the first driving circuit. Period selection signal for selecting any one of the periods obtained by dividing one horizontal scanning period into a predetermined number, and a plurality of levels input in each period. A level selection signal for selecting any one of the drive voltages is generated in a predetermined procedure, and further, a predetermined number of levels required for displaying an image of a plurality of gradations on each pixel of the display section. The driving voltage is taken in every one of the predetermined number of levels for each period,
Any one of the plurality of levels of driving voltage taken in for each period is selected based on the level selection signal, and further, any one of the levels of driving voltage selected for each period is A method for driving a display device, comprising selecting based on a period selection signal and outputting to a signal line associated with a pixel to be displayed.