JPH07131494A - Branchmetric arithmetic circuit - Google Patents

Abstract

PURPOSE:To provide the branchmetric arithmetic circuit which can be reduced in circuit scale by decreasing the number of branchmetric bits. CONSTITUTION:This circuit is the branchmetric arithmetic circuit of a trellis decoding circuit which decodes nonencoded bits by using encoded bits after the Viterbi decoding of a Viterbi decoding part on the basis of a reception symbol obtained by demodulating data, trellis-encoded and modulated on a transmission side, decoded on a reception side and then making a soft decision, and is equipped with an amplitude limiting means 11 which limits the amplitude of the received symbol obtained by making the soft decision and a Euclidean distance arithmetic means 13 which calculates the square of a Euclidean distance as to the data after the amplitude limitation by the amplitude limiting means 11 as the branchmetric of Viterbi decoding.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a branch metric operation circuit of a trellis decoding circuit which decodes a trellis coded and modulated information symbol.

[0002]

2. Description of the Related Art In recent years, in the field of broadcasting, a trellis coded modulation system is used as a coding method for obtaining a coding gain in a limited frequency band. For the coding method and effects, see, for example, "Trellis-" by G. Ungerboeck.
Coded Modulation with Redundant Signal Sets Part
I: Introduction "and his work" Trellis-Coded Modulatio "
nwith Redundant Signal Sets Part II: State of the A
rt ”, IEEE Communications Magazine, 1987-Vol.25.N
It is mentioned in o.2.

A brief overview will be given below. The general form of the trellis encoder is shown in FIG. Referring to FIG. 9, information symbol (k + m) bits are uncoded bits (k bits),
The coded bits (n bits) obtained by expanding the m bits by the convolutional encoder 101 are used as modulation symbol (k + n) bits, which are modulated and transmitted. The trellis coded modulation system is characterized by the arrangement of the modulation symbols.

FIG. 10 shows an example in which k = 2, m = 1, n = 2 and the modulation method is 16QAM. In the example shown in FIG. 10, the upper 2 bits correspond to non-coded bits and the lower 2 bits correspond to coded bits. From the configuration of the trellis encoder shown in FIG. 9, the code bit which is the lower 2 bits obviously has a larger inter-code distance. So the top 2bi
For t, the intersymbol distance is taken depending on the modulation symbol arrangement.

In FIG. 10, for example, a symbol ◯ is a symbol whose lower 2 bits are “00”. Δ is a symbol of “11”, □ is a symbol of “01”, and ⊚ is a symbol of “10”. The basic principle of the trellis coded modulation method is to maximize the distance on the modulation symbol arrangement and to obtain a total inter-code distance for symbols that differ only in the upper 2 bits by arranging in this way.

By the way, the receiving side decodes this by the Viterbi algorithm. The basic state transition diagram of the decoding includes parallel state transitions as shown in FIG. That is, in the case of this example, among the state transitions from time (j-1) to time j, focusing on the transition from state {0,0} to state {0,0}, the possible encoder output is There are four ways. This corresponds to the symbol ◯ in FIG. 10 in which the number of possible cases of 2 bits of non-coding is 4. Also, for the coded bit “11”, four branches corresponding to the symbols of Δ have time j
Enter the state {0,0} in. Therefore, the path selection at this node is to select the path having the closest distance to the received symbol sequence from the eight paths.

When the received symbol is softly determined, it is assumed that the position e of the received symbol is detected by the soft determination at a position as shown in FIG. 12 due to the influence of transmission line noise.
In this case, first, the branch metric is obtained to obtain the path metric. At this time, it is clear that the distance to the symbol of 08 is the shortest in the distance to the symbols of four.

[0008] In the text, ○ 8 means that 8 is entered in ○ (for example, refer to FIG. 8), and similarly ΔF is △.
It means the one in which F is entered. That is, by writing a character immediately after the figure, it means that the character is written in the figure.

In this way, when the path is selected by using the branch metric, the time (j-
Since the path (Rj-1) left in 1) is common to the four paths passing through the path of the symbol ◯, the path (Rj-1) is
The path metric for -1) is also common. Therefore,
The difference in path metric for these four paths is equal to the difference in branch metric for each of the O symbols. Therefore, the calculation of the path metric for selecting the path can be represented by the calculation for the path passing through 08. Therefore, this 08 is called a representative symbol.

Further, referring to FIG. 12, for the symbol Δ, ΔF is the closest to the received symbol, and ΔF is the representative symbol. Therefore, it is sufficient to consider only the path passing through ΔF among the paths of the dotted line in FIG. 13, and comparing the path metric of the path passing through 08 and the path metric of the path passing through ΔF, the likelihood With a larger path metric, that is, a path with a smaller path metric is selected. Thus, in trellis decoding, it is not necessary to calculate the branch metric for all symbols, and it is sufficient to calculate the branch metric only for the representative symbol determined by the position of the received symbol.

In this way, the coded bit at time j is decoded by the Viterbi algorithm, and the coded bit is "0".
If it is 1 ”, the possible modulation symbols of the representative symbol set 008, ΔF, ◎ 2, and □ 5 at time j are □ 5 where the lower 2 bits are“ 01 ”.
The non-coded bit is “01” which is the upper 2 bits. That is, the non-coded bits can be decoded using the Viterbi-decoded coded bits. To summarize the above, the basic configuration of trellis decoding is roughly divided into an uncoded bit decoding unit 105 and a Viterbi decoding unit 103 as shown in FIG. Note that the Viterbi-decoded coded bits are used for decoding the non-coded bits.

As described above, it is necessary to calculate the branch metric in Viterbi decoding. FIG. 15 shows a configuration example of a conventional branch metric unit (hereinafter sometimes abbreviated as BMU) for calculating a branch metric. In trellis decoding, the square of the Euclidean distance between the received symbol and the representative symbol of each subset is used. 2 of this Euclidean distance
If the square is used as a branch metric as it is, each branch metric (◯, Δ, ⊚, □) is represented by 8 bits.

[0013]

On the other hand, in many cases, the bits are cut off due to the scale reduction of the path metric calculation circuit that follows. That is, in the conventional configuration, for example, when the branch metric unit is composed of ROM, the soft-decision received symbol is expressed by 10 bits,
If the bit censoring is the upper 4 bits, 2 ¹⁰ × 4 × 4 =
Requires 8192 bit ROM. RO of this scale
There is a cost disadvantage in incorporating M as a trellis decoding LSI into one chip.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a branch metric operation circuit capable of reducing the number of bits of branch metric and reducing the circuit scale.

[0015]

In order to achieve the above object, the first invention of the present application is to convolutionally encode a part of a predetermined number of bits for an information symbol composed of a plurality of bits on the transmission side. Coded bits, and the rest of the bits are non-coded bits and are paired with the coded bits and subjected to trellis coded modulation, demodulated on the receiving side, and based on the received symbols obtained by soft decision. , A branch metric operation circuit of a trellis decoding circuit that decodes non-coded bits using coded bits that have been Viterbi-decoded by a Viterbi decoding unit, and applies amplitude limitation to a received symbol obtained by the soft decision. The square metric of the Euclidean distance for the amplitude limiting means and the data whose amplitude is limited by the amplitude limiting means is calculated as the branch metric in the Viterbi decoding. And summarized in that and a Euclidean distance calculation means.

More specifically, on the transmission side, an information symbol composed of a plurality of bits is convolutionally coded, which is a part of m bits, to expand it to n (> m) bits, and the remaining k bits. A bit is a non-coded bit and a (k + m) bit trellis-coded and modulated in combination with the coded bit is transmitted, and on the receiving side, a demodulator demodulates and a soft-decision received symbol is input to a Viterbi decoding circuit. A branch metric for calculating a branch metric for a representative symbol of each subset used in the Viterbi decoding in a trellis decoding circuit configured to decode the k uncoded bits by using the n coded bits decoded by In the arithmetic circuit, for the received symbol that has been soft-decided, the amplitude-limited data is applied to the amplitude-limited data. Is obtained by a configuration in which a branch metric by calculating the square of the Euclidean distance by the Euclidean distance calculation means.

Further, the second invention of the present application has a non-linear processing means for performing a non-linear processing for limiting the output value of the Euclidean distance calculating means according to claim 1 to the predetermined value when the output value exceeds the predetermined value. Is the gist.

The third invention of the present application is summarized as having a bit truncation means for truncating the output of the Euclidean distance calculation means according to the first aspect.

The fourth invention of the present application is summarized in that it has bit truncation means for truncating the output of the non-linear processing means according to the second aspect.

Further, the fifth invention of the present application has a non-linear processing means for performing non-linear processing for limiting the output value of the bit truncation means to a predetermined value when the output value exceeds the predetermined value. Use as a summary.

[0021]

With the above configuration, the branch metric arithmetic circuit of the first invention of the present application demodulates the trellis coded modulation on the transmission side to the reception side to obtain a reception symbol obtained by soft decision. On the other hand, in order to easily calculate the Euclidean distance, the amplitude limiting means limits the amplitude. Further, the square of the Euclidean distance with respect to the data on which the amplitude is limited is calculated by the Euclidean distance calculating means and used as a branch metric in Viterbi decoding.

In the branch metric arithmetic circuit of the second invention of the present application, when the output value of the Euclidean distance arithmetic means according to claim 1 exceeds a predetermined value, the nonlinear processing means performs the nonlinear processing to such an extent that decoding deterioration does not occur, and the output concerned. By limiting the value to the predetermined value, the number of bits required to express each branch metric can be reduced.

In the branch metric operation circuit according to the third aspect of the present invention, the bit truncation means performs the bit truncation on the output of the Euclidean distance computation means.

The branch metric operation circuit according to the fourth aspect of the present invention performs bit truncation on the output of the non-linear processing means according to the second aspect.

The branch metric operation circuit according to the fifth aspect of the present invention performs non-linear processing to such an extent that decoding deterioration does not occur when the output value of the bit truncation means according to claim 3 exceeds a predetermined value, and the output value is set to the predetermined value. It is possible to reduce the number of bits required to express each branch metric by limiting to.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a branch metric arithmetic circuit according to the present invention. As shown in FIG. 1, in the branch metric operation circuit of this embodiment, a limiter unit 11, a Euclidean distance operation unit 13, a non-linear processing unit 15, and a bit truncation unit 17 are connected in series.

First, an example of amplitude limitation of a received symbol will be described with reference to FIG. Even if the branch metric is obtained after performing the amplitude limitation as shown in FIG. 2, the correction capability is not deteriorated. This is because the order of the Euclidean distance for each representative symbol does not change even if the amplitude is limited. For example, the received symbol a shown in FIG.
The representative symbol closest to is □ 9, and also ○ C, ◎
The distance is small in the order of 6 and Δ3. Then, even in the symbol b after the amplitude is limited, the order does not change.

By thus limiting the amplitude, the Euclidean distance calculation can be performed by calculating the square of the Euclidean distance only in the area surrounded by the set of four representative symbols as shown in FIG. FIG. 3 shows an example of what value the square of the Euclidean distance with respect to the lower left representative symbol in the nine-value soft decision takes, depending on the position of the received symbol. For example, if the received symbol is c
At the position of, the square of the Euclidean distance from the representative symbol at the lower left starting point is 5 ² +5 ² = 50.
Further, the Euclidean distance from the representative symbol at the position of d is 7 ² +0 ² = 49, and similarly, at the position of e, 8 ² +8 ² = 128.

Next, the second embodiment will be described with reference to FIG. Referring to FIG. 3, the value that the square of the Euclidean distance can take is, as is clear from the above, 0 to
It is 128, and its representation requires 8 bits. By the way, in FIG. 3, the bit of the MSB becomes 1 only when there is a received symbol at the position of (c), and only for this case is the MSB (Most Significant).
It is uneconomical to use 1 bit of ant Bit).
Therefore, the 128 values at this time are set to the non-linear processing means 103.
To 127. As a result, the whole can be represented by 7 bits.

As a representative example of the error rate characteristic, a simulation experiment by a computer is shown in FIG. 4 (in the figure, TCM is an abbreviation for Trellis Coded Modulation). The graph [g] in FIG.
BER (Bit Error Ra) when non-linear processing is not performed
te) characteristic. Further, the graph [f] is the BER characteristic when the amplitude limitation and the non-linear processing are performed, and the number of bits BS of each branch metric is 7. Graph [g]
It can be seen that there is almost no difference in the BER characteristics when comparing the graph of [f] with that of [f]. For reference, the BER characteristics and the graph [b] when the QPSK modulation of the graph [a] is used.
16QAM BER characteristics (when encoding is not performed) are also shown.

Next, a third embodiment will be described with reference to FIGS. After the amplitude is limited, the bits are cut off by the bit cutoff means, and the path metric calculation in the subsequent stage can be made more efficient. According to the graph [e] of the simulation experiment result of FIG. 4, it is understood that the decoding deterioration hardly occurs even when the high-order 3 bits are discontinued. FIG. 5 shows each branch metric corresponding to FIG. 3 at that time in decimal notation. If bit truncation is performed without performing the non-linear processing, in order to prevent decoding deterioration,
It can be easily imagined that 4 bits are required as shown in FIG.

Next, a fourth embodiment will be described with reference to FIGS. As is apparent from the above, the order of the non-linear processing means 103 and the bit truncation means 104 in FIG. 1 can be exchanged. For example, by forcing "8" in the upper right of the branch metrics in Fig. 6 to "7",
It matches the branch metric in FIG. 5, and can be expressed in 3 bits.

Next, a fifth embodiment according to the present invention will be described with reference to FIGS. 7 and 8. FIG. 7 shows a better signal arrangement when the number of uncoded bits is 2 bits or more, and an example thereof is shown (uncoded 2bi
t).

In this, first, a symbol group set in a predetermined bit arrangement, that is, an uncoded 2 bit (higher 2 bits) arrangement in each subset symbol of a subset is mapped by a Gray code. Specifically, for example, when paying attention to the symbol of ◯ (the lower 2 bits are “00”), the adjacent symbols ◯ 0 and ◯ 4 differ by only 1 bit.

Next, among the representative symbols of each subset,
Adjacent ones are arranged so that the lower 2 bits of the coded bits differ by only 1 bit. In particular,
For example, □ 5 and ◯ C, and □ 5 and Δ3 which are adjacent to each other are made to differ by only 1 bit for the lower 2 bits.

By doing so, the magnitude relationship between the Euclidean distance and the Hamming distance for the non-coded bits matches. In addition, since the magnitude relationship between the Euclidean distance and the Hamming distance is the same for the coded bits that are subject to Viterbi decoding, the BER characteristic is 0.1 to 0.3 dB in C / N conversion as compared with the example shown in FIG. The degree is improved.

FIG. 8 shows the BER characteristics when the amplitude limitation, the non-linear processing, and the bit truncation (Bs = 3) are applied by using the signal arrangement shown in FIG. [I], graph [j]). In addition,
In this example, the number of representation bits (quantization bit number) of the received symbol is 12 bits (10 bits in FIG. 4). Also in this case, the effects of the above-mentioned three processes, that is, the amplitude limitation, the non-linear process, and the bit truncation can be ignored.
It turns out to be effective.

The graph [h] is an asymptotic lower limit value (theoretical value) of the BER characteristic of the 16TCM of the present embodiment calculated based on the above-mentioned document.

As described above, according to the above embodiments,
In order to facilitate the calculation of the Euclidean distance, a limiter (amplitude limitation of received symbols) is first applied. This is 16QA
This is useful for rectangular type and cross type modulation schemes such as M and 32QAM. Further, the number of bits of each branch metric can be reduced by applying a non-linear process (limiter) to the output of the Euclidean distance calculation means to the extent that decoding deterioration does not occur, thereby reducing the load of the path metric calculation in the subsequent stage. You can In addition, the scale of the branch metric calculation circuit itself can be reduced.

[0040]

As described above, the present invention has effects such as reducing the number of bits of the branch metric and reducing the circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a branch metric unit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a range of amplitude limitation of received symbols.

FIG. 3 is a diagram showing an example of calculating a branch metric.

FIG. 4 is a diagram showing BER simulation experimental values.

FIG. 5 is a diagram showing a case where there is nonlinear processing.

FIG. 6 is a diagram showing a case without nonlinear processing.

FIG. 7 is a diagram showing an example of a better signal arrangement.

FIG. 8 is a diagram showing BER characteristics by a computer simulation experiment.

FIG. 9 is a diagram showing an example of trellis-coded modulation symbol arrangement.

FIG. 10 is a block diagram showing a configuration of a trellis encoder.

FIG. 11 is a diagram showing an example of parallel state transitions.

FIG. 12 is a diagram showing received symbols and branch metrics.

FIG. 13 is a diagram showing representative symbols and state transitions.

FIG. 14 is a block diagram showing a basic configuration of trellis decoding.

FIG. 15 is a block diagram showing a configuration example of a conventional branch metric unit.

[Explanation of symbols]

 11 limiter unit 13 Euclidean distance calculation means 15 non-linear processing means 17 bit truncation means

Claims (5)

[Claims] 1. An information symbol composed of a plurality of bits on the transmission side is convolutionally coded by convolutionally coding a predetermined number of bits of a part of the information symbols, and the remaining bits are coded as uncoded bits. The coded bits, which have been trellis coded and modulated, are demodulated on the receiving side and are not coded using the coded bits that are Viterbi-decoded by the Viterbi decoding unit based on the received symbols obtained by soft decision. A branch metric operation circuit of a trellis decoding circuit for decoding bits, comprising amplitude limiting means for performing amplitude limitation on the received symbol obtained by the soft decision, and data subjected to amplitude limitation by the amplitude limiting means. And a Euclidean distance calculating means for calculating the square of the Euclidean distance for the branch metric in the Viterbi decoding. Inch metric arithmetic circuit. 2. The branch metric according to claim 1, further comprising a non-linear processing means for performing a non-linear processing for limiting the output value to the predetermined value when the output value of the Euclidean distance calculation means exceeds the predetermined value. Arithmetic circuit. 3. The branch metric calculation circuit according to claim 1, further comprising a bit truncation unit that truncates the output of the Euclidean distance calculation unit. 4. The branch metric arithmetic circuit according to claim 2, further comprising bit truncation means for truncating the output of the non-linear processing means. 5. The branch metric calculation according to claim 3, further comprising a non-linear processing means for performing a non-linear processing for limiting the output value to the predetermined value when the output value of the bit truncation means exceeds the predetermined value. circuit.