JPH07131129A - Double-side-mounted multichip module - Google Patents

Double-side-mounted multichip module

Info

Publication number
JPH07131129A
JPH07131129A JP5276360A JP27636093A JPH07131129A JP H07131129 A JPH07131129 A JP H07131129A JP 5276360 A JP5276360 A JP 5276360A JP 27636093 A JP27636093 A JP 27636093A JP H07131129 A JPH07131129 A JP H07131129A
Authority
JP
Japan
Prior art keywords
chip module
chip
board
heat
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5276360A
Other languages
Japanese (ja)
Inventor
Toru Kishimoto
亨 岸本
Shinichi Sasaki
伸一 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP5276360A priority Critical patent/JPH07131129A/en
Publication of JPH07131129A publication Critical patent/JPH07131129A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15322Connection portion the connection portion being formed on the die mounting surface of the substrate being a pin array, e.g. PGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits

Landscapes

  • Combinations Of Printed Boards (AREA)

Abstract

PURPOSE:To achieve mounting of a chip generating much heat and high density connection between chips by mounting connectors on the periphery of a multichip module board, that serve as external signal connection and feed electric power to LSIs. CONSTITUTION:The figure shows an example where a plurality of processor modules 26 are mounted on a printed wiring board to form a multichip processor. Cooling air flows upward and downward in the figure. Since the heat radiating pathes are distributed on both sides of the multichip module, heat is radiated by efficiently making use of a space where cooling air flows, and the allowable power consumption can be increased. In addition a large number of mutichip modules are connected to the printed wiring board through connectors 16. That is, a mutichip module can be mounted in hook shelf shape; therefore, a problem of increase in mounting area can be solved, and the length of signal lines between multichip modules can be reduced, which leads to improved operation speed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子装置システムの高
速化、高密度実装化によって高密度化接続が必要とな
り、かつ、高い放熱能力を必要とするマルチチップモジ
ュールに係り、特に、高発熱チップ搭載及び高密度なチ
ップ間接続を容易に実現することのできるマルチチップ
モジュールに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module which requires high-density connection due to high-speed and high-density mounting of an electronic device system and requires high heat dissipation capability, and particularly, high heat generation. The present invention relates to a multi-chip module that can easily implement chip mounting and high-density chip-to-chip connection.

【0002】[0002]

【従来の技術】図8に、従来のマルチチップモジュール
の断面及びマルチチップモジュールを搭載したプリント
配線板をシェルフに搭載した状態を示す。ここで、1は
LSIチップ、2は LSI チップ1をマルチチップ基板に
接続するための TAB (TapeAutomated Bonding)、3はア
ルミナなどを絶縁層材料としたマルチチップモジュール
(MCM)基板、4は MCM 基板3とプリント配線板8との信
号接続及び給電を行うための I/O ピン、5は MCM 基板
3に搭載した LSI チップ1を機械的に保護するための
キャップ、6は LSI チップ1から発生する熱を周辺空
気に放熱するためのヒートシンク、7は一般部品、8は
MCM 基板3や一般部品7を搭載するプリント配線板、
9はプリント配線板8間をバックボード11を介して信号
接続するためのコネクタ、10はコネクタピン、11はプリ
ント配線板8間を信号接続し、かつ各プリント配線板8
に給電を行うためのバックボードを示す。なお、冷却用
空気は紙面の上下方向に流れている。
2. Description of the Related Art FIG. 8 shows a cross section of a conventional multi-chip module and a state in which a printed wiring board on which the multi-chip module is mounted is mounted on a shelf. Where 1 is
LSI chip, 2 is a TAB (Tape Automated Bonding) for connecting the LSI chip 1 to a multi-chip substrate, and 3 is a multi-chip module using alumina or the like as an insulating layer material.
(MCM) board, 4 are I / O pins for signal connection and power supply between the MCM board 3 and the printed wiring board 8, and 5 are caps for mechanically protecting the LSI chip 1 mounted on the MCM board 3. , 6 is a heat sink for radiating heat generated from the LSI chip 1 to the surrounding air, 7 is a general component, and 8 is
A printed wiring board on which the MCM board 3 and general parts 7 are mounted,
9 is a connector for connecting signals between the printed wiring boards 8 via the backboard 11, 10 is a connector pin, 11 is a signal connection between the printed wiring boards 8, and each printed wiring board 8
Shows a backboard for power supply to. Note that the cooling air flows in the vertical direction on the paper surface.

【0003】従来構造のマルチチップモジュール(マル
チチップモジュール基板3、LSI チップ1及び I/O ピ
ン4で構成したものを総称)では、マルチチップモジュ
ール基板3の片面のみに部品搭載を行っているため、LS
I チップで発生した熱はマルチチップモジュール基板3
を介してヒートシンク6に導かれ、空気に放熱される。
しかし、全ての放熱方向が同一のため、例えば消費電力
が小さい LSI チップ1も高発熱 LSI チップの影響を受
けて高温となる問題があった。
In a multi-chip module having a conventional structure (generally a multi-chip module substrate 3, an LSI chip 1 and I / O pins 4), components are mounted only on one side of the multi-chip module substrate 3. , LS
The heat generated by the I-chip is the multi-chip module board 3
It is guided to the heat sink 6 via and is radiated to the air.
However, since all the heat radiation directions are the same, there is a problem that, for example, the LSI chip 1 with low power consumption is also affected by the high heat generation LSI chip and becomes high temperature.

【0004】また、全ての熱を一方向に逃がす構成のた
め、発熱を分散することができず、本来ヒートシンクが
不要な低消費電力の LSI を搭載していても、ヒートシ
ンク6が必要となり、かつ、必然的に大型のヒートシン
クを必要とする問題もある。このため、図8に示すよう
に、プリント配線板8間の間隔を増すことが必要とな
り、その結果、信号伝送距離が増し、システムの動作速
度を低減させてしまうという問題もあった。
Further, since all the heat is dissipated in one direction, the heat cannot be dispersed, and the heat sink 6 is required even if the low power consumption LSI that originally requires no heat sink is mounted, and Inevitably, there is also the problem of requiring a large heat sink. Therefore, as shown in FIG. 8, it is necessary to increase the distance between the printed wiring boards 8, resulting in an increase in signal transmission distance and a decrease in system operating speed.

【0005】さらに、図8に示すようなマルチチップモ
ジュールとして、例えばプロセッサモジュールのように
マイクロプロセッサと多数のキャッシュメモリーで構成
されるモジュールを想定すると、従来技術では二次元的
にチップを配置する必要があるため、マイクロプロセッ
サから各キャッシュメモリーまでの距離に差を生じ、最
も遠方に配置されたキャッシュメモリーまでの配線距離
でシステムの性能が決定づけられてしまう。これは、マ
ルチチップモジュールへの部品搭載が二次元的にしか行
えないためである。このため、従来のマルチチップモジ
ュールでは、薄膜技術等高価な技術を駆使して部品を高
密度に搭載し、配線距離を短縮することが行われてき
た。しかし、マルチチップモジュールのコストが上昇す
るとともに、アッセンブルも飛躍的に高度な技術を必要
とするため、製造歩留りが悪化するなど、量産には向か
ないなどの問題をはらんでいた。
Further, assuming that the multi-chip module as shown in FIG. 8 is a module composed of a microprocessor and a large number of cache memories such as a processor module, it is necessary to arrange the chips two-dimensionally in the prior art. Therefore, there is a difference in the distance from the microprocessor to each cache memory, and the performance of the system is determined by the wiring distance to the cache memory arranged farthest away. This is because the components can be mounted on the multi-chip module only in two dimensions. Therefore, in the conventional multi-chip module, components have been mounted at high density by making use of expensive technology such as thin film technology, and the wiring distance has been shortened. However, as the cost of the multi-chip module rises and the assembly requires dramatically advanced technology, the production yield is deteriorated, which is not suitable for mass production.

【0006】さらに、従来のマルチチップモジュール
は、これを搭載するマザーボードに対向して搭載するこ
と、すなわちマザーボードへの二次元的搭載がしばしば
行われていた。しかし、多数のマルチチップモジュール
をマザーボード搭載しようとすると、エリアネックとな
ってしまい、その結果、複数のマザーボードに分割搭載
する等の対策が必要となり、新たなコネクタ接続が必要
となるなど、実装エリア上、信号伝搬上多くの問題があ
った。
Further, the conventional multi-chip module has often been mounted opposite to a mother board on which it is mounted, that is, two-dimensionally mounted on the mother board. However, if you try to mount a large number of multi-chip modules on the motherboard, it will become an area neck, and as a result, you will need to take measures such as mounting separately on multiple motherboards, and you will need a new connector connection. In addition, there were many problems in signal propagation.

【0007】[0007]

【発明が解決しようとする課題】以上説明したように、
従来のマルチチップモジュール実装方式は、生産上、実
装上多くの課題を有していた。
As described above,
The conventional multi-chip module mounting method has many problems in production and mounting.

【0008】本発明の目的は、上記従来技術の有してい
た課題を解決して、高速化が必要な電子装置システムに
対応して、高発熱チップ搭載及び高密度なチップ間接続
を容易に実現することのできる新規なマルチチップモジ
ュール実装構造を提供することにある。
An object of the present invention is to solve the problems of the above-mentioned prior art and to easily mount a high heat generating chip and facilitate high-density chip-to-chip connection in response to an electronic device system that requires high speed. It is to provide a novel multi-chip module mounting structure that can be realized.

【0009】[0009]

【課題を解決するための手段】上記目的は、少なくとも
1個以上の LSI を搭載し、該 LSI 間の信号ネットを接
続する配線と、外部との信号接続及び給電を行うための
コネクタとを具備したマルチチップモジュール基板にお
いて、高発熱 LSI を該マルチチップモジュール基板の
両サイドに、かつ、搭載エリアが上下間で一致しないよ
うに配置し、また、上記マルチチップモジュール基板に
搭載した高発熱 LSI の対向する面上にヒートシンクを
配備し、さらに、上記マルチチップモジュール基板周辺
部に、外部との信号接続及び上記マルチチップモジュー
ル基板に搭載した LSI への給電を司るコネクタを搭載
したことを特徴とする両面実装形マルチチップモジュー
ルとすることによって達成することができる。
Means for Solving the Problems The above object is provided with at least one or more LSIs, wiring for connecting a signal net between the LSIs, and a connector for performing signal connection and power supply with the outside. In the multi-chip module board, the high-heat-generating LSIs are arranged on both sides of the multi-chip module board, and the mounting areas are not vertically aligned. A heat sink is provided on the opposite surface, and a connector for controlling signal connection to the outside and power supply to the LSI mounted on the multi-chip module board is mounted on the periphery of the multi-chip module board. This can be achieved by using a double-sided mounting type multi-chip module.

【0010】本発明は、また、上記マルチチップモジュ
ール周辺部に、少なくとも1個のマルチチップモジュー
ルを搭載するマザーボードにマルチチップモジュールを
垂直方向に搭載接続できるコネクタを設けたことを第二
の特徴とする。
A second feature of the present invention is that the peripheral portion of the multi-chip module is provided with a connector capable of vertically mounting and connecting the multi-chip module to a mother board on which at least one multi-chip module is mounted. To do.

【0011】[0011]

【作用】上記のような構成とすることによって、放熱を
マルチチップモジュールの両サイドに分散することがで
きるため、発熱の集中を避けることができ、マルチチッ
プモジュール周辺の冷却空気を有効に利用して放熱する
ことが可能となる点が従来技術と大きく異なる。
With the above structure, the heat radiation can be distributed to both sides of the multi-chip module, so that the concentration of heat generation can be avoided and the cooling air around the multi-chip module can be effectively used. The fact that heat can be dissipated by heat is significantly different from the prior art.

【0012】また、高発熱チップに個別にヒートシンク
を設けることができるので、ヒートシンクサイズを小型
化することができ、ひいてはマルチチップモジュールの
部品高さを低くでき、その結果、マルチチップモジュー
ル間の信号伝搬を短縮できる点が従来技術と大きく異な
る。
Further, since heat sinks can be individually provided to the high heat generating chips, the heat sink size can be reduced, and the component height of the multi-chip module can be reduced, and as a result, signals between the multi-chip modules can be reduced. The point that the propagation can be shortened is greatly different from the conventional technology.

【0013】また、低消費電力のチップには、不要なヒ
ートシンクを設ける必要がないため、コストを低減でき
る点が従来技術と大きく異なる。
Further, since it is not necessary to provide an unnecessary heat sink on the chip of low power consumption, the point that the cost can be reduced is greatly different from the prior art.

【0014】さらに、部品を両面搭載するため、部品間
の信号配線距離を短縮することができる。このため、薄
膜技術などの高価な配線技術を使用しなくても、配線距
離を短縮でき、例えば従来から使用されているプリント
配線板等を採用することができるため、コストを大幅に
削減できる点が従来技術と大きく異なる。
Furthermore, since the components are mounted on both sides, the signal wiring distance between the components can be shortened. For this reason, the wiring distance can be shortened without using expensive wiring technology such as thin film technology, and for example, a conventionally used printed wiring board or the like can be adopted, so that the cost can be significantly reduced. Is significantly different from the conventional technology.

【0015】本発明は、また、上記したように、マルチ
チップモジュール基板周辺部に、少なくとも1個のマル
チチップモジュールを搭載するマザーボードに、上記マ
ルチチップモジュールをを垂直方向に搭載接続できるコ
ネクタを設けることを第二の特徴とする。
As described above, the present invention also provides, on the peripheral portion of the multi-chip module board, a connector for mounting and connecting the multi-chip module in a vertical direction to a motherboard on which at least one multi-chip module is mounted. This is the second feature.

【0016】これによって、本発明のマルチチップモジ
ュールで単一プロセッサを構成し、これを複数使用した
マルチプロセッサを構成する場合、上記コネクタを介し
てマザーボードに多数個のマルチチップモジュールを接
続することができる。すなわち、マルチチップモジュー
ルをブックシェルフ状に実装することができるため、実
装エリアの問題を克服でき、かつ、マルチチップモジュ
ール間の信号配線距離を短縮できるため、動作速度も向
上できるなどが従来技術と大きく異なる。
Therefore, when a single processor is constructed by the multi-chip module of the present invention and a multi-processor using a plurality of the single processors is constructed, a large number of multi-chip modules can be connected to the motherboard through the connector. it can. That is, since the multichip module can be mounted in a bookshelf shape, the problem of the mounting area can be overcome, and the signal wiring distance between the multichip modules can be shortened, so that the operation speed can be improved. to differ greatly.

【0017】[0017]

【実施例】以下、本発明のマルチチップモジュールにつ
いて、実施例によって具体的に説明する。
EXAMPLES The multi-chip module of the present invention will be specifically described below with reference to examples.

【0018】[0018]

【実施例1】図1は本発明マルチチップモジュールの一
実施例の構成を示す断面図である。
[Embodiment 1] FIG. 1 is a sectional view showing the structure of an embodiment of the multichip module of the present invention.

【0019】ここで、1は LSI チップ、2は TAB(Tape
Automated Bonding 部)、13は高発熱チップに個別に設
けた小形ヒートシンク、14は LSI チップ1を保護する
ためのポッティング樹脂、15はメモリーなど比較的低消
費電力の表面実装部品、16はマルチチップモジュールの
1辺に設けたコネクタハウジング、17はコネクション用
の I/O ピン、18はマルチチップモジュール基板である
プリント配線板、19はプリント配線板18に設けたサーマ
ルビアである。また、図2は図1のマルチチップモジュ
ールを表面側及び裏面側から見た図である。
Here, 1 is an LSI chip, 2 is a TAB (Tape
(Automated Bonding part), 13 is a small heat sink provided individually on the high heat generation chip, 14 is potting resin for protecting the LSI chip 1, 15 is a relatively low power consumption surface mounting component such as memory, and 16 is a multi-chip module. 1 is a connector housing provided on one side, 17 is an I / O pin for connection, 18 is a printed wiring board which is a multi-chip module board, and 19 is a thermal via provided in the printed wiring board 18. 2 is a view of the multi-chip module of FIG. 1 viewed from the front surface side and the back surface side.

【0020】本実施例では、高発熱チップ1をプリント
配線板18の両面に搭載して発熱を分散した形態を示した
ものである。プリント配線板18は一般的には熱伝導率が
低いため、この例ではサーマルビア19を設け、高発熱チ
ップ1から小形ヒートシンク13までの熱抵抗を低減して
いる。例えば、高発熱チップ1としてマイクロプロセッ
サや浮動小数点演算プロセッサを想定し、表面実装部品
15としてキャッシュメモリを想定すると、部品を両面搭
載していることから、基板両面を貫通するスルーホール
を有効に使用することによって配線距離を短縮すること
ができ、その結果、安価に製造することの可能なプリン
ト配線板18を用いても接続距離を短縮でき、従来薄膜配
線技術を使用して配線距離を短縮していた場合と同等の
効果を得ることができる。
In this embodiment, the high heat generating chips 1 are mounted on both surfaces of the printed wiring board 18 to disperse the heat generation. Since the printed wiring board 18 generally has low thermal conductivity, thermal vias 19 are provided in this example to reduce the thermal resistance from the high heat generating chip 1 to the small heat sink 13. For example, assuming that the high heat generation chip 1 is a microprocessor or a floating point arithmetic processor, surface mounting parts
Assuming a cache memory as 15, since the components are mounted on both sides, the wiring distance can be shortened by effectively using the through holes penetrating both sides of the board, and as a result, it is possible to manufacture at low cost. Even if the possible printed wiring board 18 is used, the connection distance can be shortened, and the same effect as in the case where the wiring distance is shortened by using the conventional thin film wiring technology can be obtained.

【0021】[0021]

【実施例2】図3は本発明の第二の実施例を示した図
で、12は無機系材料の典型であるアルミナ基板、20はア
ルミナ基板12内に設けたワイヤボンディングを2段構成
で実現するためのキャビティ部、21はワイヤボンディン
グ部、22はアルミナ基板12側に設けたボンディングパッ
ドを示す。本実施例の場合には、配線収容性をより向上
させるために基板材料としてガラスセラミックス(無機
系材料の一種)のような誘電率の低い材料を使用する
と、熱伝導率も低下するため、このようなアップリケー
ションでは有効である。
[Embodiment 2] FIG. 3 is a view showing a second embodiment of the present invention, in which 12 is an alumina substrate, which is a typical inorganic material, and 20 is a two-stage structure of wire bonding provided in the alumina substrate 12. Reference numeral 21 denotes a wire bonding portion, and 22 denotes a bonding pad provided on the alumina substrate 12 side for realizing the cavity portion. In the case of the present embodiment, when a material having a low dielectric constant such as glass ceramics (a kind of inorganic material) is used as the substrate material in order to further improve the wiring accommodating property, the thermal conductivity is also reduced. It is effective in such applications.

【0022】[0022]

【実施例3】図4は本発明の第三の実施例を示した断面
図で、23はメタルで構成したヒートスプレッダーを示
す。本実施例は、放熱をさらに効果的にするために、高
発熱チップ1の搭載部にキャビティ20を設け、そこに熱
伝導性の高いメタルヒートスプレッダーを挿入した構成
としたもので、これによって高発熱チップ1からヒート
シンク13までの熱抵抗を大幅に低減することができる。
[Embodiment 3] FIG. 4 is a sectional view showing a third embodiment of the present invention, and 23 shows a heat spreader made of metal. In this embodiment, in order to make heat dissipation more effective, a cavity 20 is provided in the mounting portion of the high heat generation chip 1, and a metal heat spreader having high thermal conductivity is inserted therein, and by this, The thermal resistance from the heat generating chip 1 to the heat sink 13 can be greatly reduced.

【0023】[0023]

【実施例4】図5は本発明の第四の実施例を示した断面
図で、ここで、24はチップをフリップチップ接続する一
例である半田ボール、25はフリップチップ接続に対応し
て表面パッドに変更が施されている LSI チップを示
す。
[Embodiment 4] FIG. 5 is a sectional view showing a fourth embodiment of the present invention, in which 24 is a solder ball which is an example of flip-chip connecting chips, and 25 is a surface corresponding to flip-chip connecting. An LSI chip with modified pads is shown.

【0024】本実施例は多端子化が進む LSI に対応し
た例を示したもので、この場合には、放熱用バンプを設
け、その直下にサーマルビア19を設けることによって容
易に実装することができる。すなわち、本発明はデバイ
スの多端子化に対しても有効である。
This embodiment shows an example corresponding to an LSI having an increasing number of terminals. In this case, a heat radiation bump is provided and a thermal via 19 is provided immediately below the bump so that it can be easily mounted. it can. That is, the present invention is effective for increasing the number of terminals of the device.

【0025】[0025]

【実施例5】図6は本発明の第五の実施例を示す断面図
で、この場合は基板として比較的熱伝導率の高いアルミ
ナ基板を採用したもので、サーマルビア等が不要となっ
ている。
[Embodiment 5] FIG. 6 is a sectional view showing a fifth embodiment of the present invention. In this case, an alumina substrate having a relatively high thermal conductivity is adopted as a substrate, and a thermal via or the like is unnecessary. There is.

【0026】[0026]

【実施例6】図7は本発明の第六の実施例を示す断面図
で、ここで26は単一のプロセッサモジュールを示したも
のである。本実施例では、プリント配線板8上にプロセ
ッサモジュール26を複数個搭載してマルチプロセッサを
構築した例を示したものである。本実施例では、冷却空
気は紙面の上下に流れている。放熱経路をマルチチップ
モジュールの両サイドに分散させたことから、冷却空気
が流れる空間を有効に利用して放熱ができ、その結果、
許容できる消費電力を向上させることができる。
Sixth Embodiment FIG. 7 is a cross-sectional view showing a sixth embodiment of the present invention, in which 26 is a single processor module. This embodiment shows an example in which a plurality of processor modules 26 are mounted on the printed wiring board 8 to construct a multiprocessor. In the present embodiment, the cooling air flows above and below the paper surface. Since the heat dissipation paths are distributed on both sides of the multi-chip module, the space where the cooling air flows can be effectively used for heat dissipation, and as a result,
The allowable power consumption can be improved.

【0027】また、コネクタ16を介してマザーボードで
あるプリント配線板8に多数個のマルチチップモジュー
ルを接続することができる。すなわち、マルチチップモ
ジュールをブックシェルフ状に実装できるため、実装エ
リア増加の問題を解決でき、かつ、マルチチップモジュ
ール間の信号配線距離を短縮できるため、動作速度も向
上させることができる。
Further, a number of multi-chip modules can be connected to the printed wiring board 8 which is a mother board via the connector 16. That is, since the multichip module can be mounted in a bookshelf shape, the problem of increasing the mounting area can be solved, and the signal wiring distance between the multichip modules can be shortened, so that the operation speed can be improved.

【0028】[0028]

【発明の効果】以上述べてきたように、マルチチップモ
ジュールを本発明構成のマルチチップモジュールとする
ことによって、従来技術の有していた課題を解決して、
高速化が必要な電子装置システムに対応して、高発熱チ
ップ搭載及び高密度なチップ間接続を容易に実現するこ
とのできる新規なマルチチップモジュール実装構造を提
供することができた。
As described above, the multi-chip module of the present invention is used as the multi-chip module to solve the problems of the prior art.
It has been possible to provide a novel multi-chip module mounting structure capable of easily realizing high heat generation chip mounting and high-density chip-to-chip connection corresponding to an electronic device system that requires high speed.

【0029】すなわち、放熱をマルチチップモジュール
の両サイドに分散できるため、発熱の集中を避けること
ができ、マルチチップ周辺の冷却空気を有効に利用して
放熱することができる利点がある。また、高発熱チップ
に個別にヒートシンクを設けることができるので、ヒー
トシンクサイズを小型化でき、ひいてはマルチチップモ
ジュールの部品高さを低くでき、その結果、マルチチッ
プモジュール間の信号伝搬を短縮できる利点がある。ま
た、低消費電力のチップには、不要なヒートシンクを設
ける必要がないため、コストを低減できる利点がある。
さらに、部品を両面搭載できるため、部品間の信号配線
距離を短縮できる。このため、薄膜技術など高価な配線
技術を用いなくても配線距離を短縮でき、例えば従来か
ら使用されているプリント配線板等を採用できるため、
コストを大幅に削減できる利点がある。
That is, since the heat radiation can be distributed to both sides of the multi-chip module, the concentration of heat generation can be avoided, and the cooling air around the multi-chip can be effectively utilized to radiate heat. In addition, since a heat sink can be provided individually for each high heat generation chip, the heat sink size can be reduced, and the component height of the multi-chip module can be reduced. As a result, the signal propagation between the multi-chip modules can be shortened. is there. In addition, since it is not necessary to provide an unnecessary heat sink on the chip with low power consumption, there is an advantage that the cost can be reduced.
Furthermore, since the components can be mounted on both sides, the signal wiring distance between the components can be shortened. Therefore, the wiring distance can be shortened without using expensive wiring technology such as thin film technology, and for example, a conventionally used printed wiring board or the like can be adopted,
There is an advantage that the cost can be significantly reduced.

【0030】なお、本発明の第二の特徴によって、マル
チチップモジュールで単一プロセッサを構成し、これを
複数使用したマルチプロセッサを構成する場合、上記コ
ネクタを介してマザーボードに多数個のマルチチップモ
ジュールを接続することができる。すなわち、マルチチ
ップモジュールをブックシェルフ状に実装できるため、
実装エリアの問題を克服することができ、かつ、マルチ
チップモジュール間の信号配線距離を短縮できるため、
動作速度も向上できる等の利点がある。
According to the second feature of the present invention, when a single processor is constructed by a multi-chip module and a multi-processor using a plurality of the multi-chip modules is constructed, a large number of multi-chip modules are provided on the motherboard through the above connector. Can be connected. That is, since the multi-chip module can be mounted in a bookshelf shape,
Since the problem of mounting area can be overcome and the signal wiring distance between multi-chip modules can be shortened,
There is an advantage that the operation speed can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一の実施例の構成を示す断面図。FIG. 1 is a sectional view showing the configuration of a first embodiment of the present invention.

【図2】図1に示した両面搭載形マルチチップの上面図
及び裏面図。
2A and 2B are a top view and a back view of the double-sided mounting type multi-chip shown in FIG.

【図3】本発明の第二の実施例の構成を示す断面図。FIG. 3 is a sectional view showing a configuration of a second embodiment of the present invention.

【図4】本発明の第三の実施例の構成を示す断面図。FIG. 4 is a sectional view showing the configuration of a third embodiment of the present invention.

【図5】本発明の第四の実施例の構成を示す断面図。FIG. 5 is a sectional view showing a configuration of a fourth embodiment of the present invention.

【図6】本発明の第五の実施例の構成を示す断面図。FIG. 6 is a sectional view showing the configuration of a fifth embodiment of the present invention.

【図7】本発明の第六の実施例の構成を示す断面図。FIG. 7 is a sectional view showing the structure of a sixth embodiment of the present invention.

【図8】従来のマルチチップモジュールをシェルフ搭載
した場合の断面図。
FIG. 8 is a sectional view of a conventional multi-chip module mounted on a shelf.

【符号の説明】[Explanation of symbols]

1… LSI チップ、2… TAB (Tape Automated Bondin
g)、3… MCM 基板、4…I/O ピン、5…保護キャッ
プ、6…ヒートシンク、7…一般部品、8…プリント配
線板、9…コネクタ、10…コネクタピン、11…バックボ
ード、12…アルミナ基板、13…ヒートシンク、14…ポッ
ティング樹脂、15…表面実装部品、16…コネクタハウジ
ング、17… I/O ピン、18…プリント配線板、19…サー
マルビア、20…キャビティ、21…ワイヤボンディング
部、22…ボンディングパッド、23…メタルヒートスプレ
ッダー、24…半田ボール、25…フリップチップ形 LSI
チップ、26…プロセッサエレメント。
1 ... LSI chip, 2 ... TAB (Tape Automated Bondin
g) 3 ... MCM board, 4 ... I / O pins, 5 ... Protective cap, 6 ... Heat sink, 7 ... General parts, 8 ... Printed wiring board, 9 ... Connector, 10 ... Connector pin, 11 ... Backboard, 12 … Alumina substrate, 13… Heat sink, 14… Potting resin, 15… Surface mount component, 16… Connector housing, 17… I / O pin, 18… Printed wiring board, 19… Thermal via, 20… Cavity, 21… Wire bonding Part, 22 ... Bonding pad, 23 ... Metal heat spreader, 24 ... Solder ball, 25 ... Flip chip type LSI
Chip, 26 ... Processor element.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】少なくとも1個以上の LSI を搭載し、該
LSI 間の信号ネットを接続する配線と、外部との信号接
続及び給電を行うためのコネクタとを具備したマルチチ
ップモジュール基板において、高発熱 LSI を該マルチ
チップモジュール基板の両サイドに、かつ、搭載エリア
が上下間で一致しないように配置し、また、上記マルチ
チップモジュール基板に搭載した高発熱 LSI の対向す
る面上にヒートシンクを配備し、さらに、上記マルチチ
ップモジュール基板周辺部に、外部との信号接続及び上
記マルチチップモジュール基板に搭載した LSI への給
電を司るコネクタを搭載したことを特徴とする両面実装
形マルチチップモジュール。
1. At least one LSI is mounted,
In a multi-chip module board equipped with wiring for connecting signal nets between LSIs and a connector for signal connection and power supply to the outside, high heat-generating LSIs are mounted on both sides of the multi-chip module board. The areas are arranged so that they do not match vertically, and a heat sink is placed on the facing surface of the high heat generation LSI mounted on the multi-chip module board. A double-sided mounting type multi-chip module, which is equipped with a connector for signal connection and power supply to the LSI mounted on the multi-chip module substrate.
【請求項2】上記マルチチップモジュール周辺部に、少
なくとも1個のマルチチップモジュールを搭載するマザ
ーボードにマルチチップモジュールを垂直方向に搭載接
続できるコネクタを設けたことを特徴とする請求項1記
載の両面実装形マルチチップモジュール。
2. The double-sided structure according to claim 1, wherein a connector for mounting and connecting the multi-chip module in a vertical direction to a mother board on which at least one multi-chip module is mounted is provided in the peripheral portion of the multi-chip module. Mounted multi-chip module.
JP5276360A 1993-11-05 1993-11-05 Double-side-mounted multichip module Pending JPH07131129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5276360A JPH07131129A (en) 1993-11-05 1993-11-05 Double-side-mounted multichip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5276360A JPH07131129A (en) 1993-11-05 1993-11-05 Double-side-mounted multichip module

Publications (1)

Publication Number Publication Date
JPH07131129A true JPH07131129A (en) 1995-05-19

Family

ID=17568349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5276360A Pending JPH07131129A (en) 1993-11-05 1993-11-05 Double-side-mounted multichip module

Country Status (1)

Country Link
JP (1) JPH07131129A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6285559B1 (en) 1998-05-26 2001-09-04 Nec Corporation Multichip module
US6818983B2 (en) 2001-08-03 2004-11-16 Renesas Technology Corp. Semiconductor memory chip and semiconductor memory device using the same
JP2007012856A (en) * 2005-06-30 2007-01-18 Toyoda Gosei Co Ltd Led apparatus and housing therefor
JP2014045816A (en) * 2012-08-29 2014-03-17 Toshiba Corp X-ray ct apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6285559B1 (en) 1998-05-26 2001-09-04 Nec Corporation Multichip module
US6818983B2 (en) 2001-08-03 2004-11-16 Renesas Technology Corp. Semiconductor memory chip and semiconductor memory device using the same
JP2007012856A (en) * 2005-06-30 2007-01-18 Toyoda Gosei Co Ltd Led apparatus and housing therefor
JP2014045816A (en) * 2012-08-29 2014-03-17 Toshiba Corp X-ray ct apparatus

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