JPH07130995A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To restrain a punchthrough, to lower a parasitic capacity and to reduce a leakage current by a method wherein a heavily doped layer is formed in a channel part and on both sides of a gate and the heavily doped layer does not exist in a sourcedrain part. CONSTITUTION:A silicon-oxide-film spacer 400 is formed on both sides of a gate pattern, a source-drain diffused layer 220 is formed, and a tungsten layer 500 is formed on a source-drain substrate. A silicon oxide film 910 and a polycrystal silicon layer 310 are formed in the gate pattern part, the silicon oxide film 400 is formed on both sides of a gate, a field oxide film 15 is formed in an element isolation region, a mask shape which is covered with the tungsten layer 500 is formed in a source-drain part, boron ions are implanted, and a heavily doped layer 200 is obtained. In addition, a tungsten layer is deposited selectively on the polycrystal silicon layer 310 and the tungsten layer 500 on the source-drain part, and a gate electrode 300 having a double structure by the polycrystal silicon layer and the tungsten layer is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device structure of an insulated gate field effect transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art Insulated gate field effect transistors are
Since the manufacturing process is simple, miniaturization is easy,
Therefore, it is widely used as an excellent element adapted to high integration and high performance. An MO formed on a silicon substrate, which is a typical insulated gate field effect transistor
In an S (Metal Oxide Silicon) transistor, an oxide film is formed on a substrate by an oxidation process, and polycrystalline silicon which is made conductive by doping impurities with a high concentration is deposited.
A transistor can be formed by patterning a polycrystalline silicon layer using a photoresist method, forming a gate electrode, and ion-implanting the gate electrode into a mask to form source and drain electrodes.

In this manufacturing process, since the gate electrode and the source and drain electrodes which form the three terminals of the transistor are formed in a self-aligned manner, miniaturization can be achieved.

However, as miniaturization progresses and the distance between the source and drain (gate length) becomes shorter, a phenomenon called punch through occurs in which a leakage current flows between the source and drain even when the channel is in an off state. As a result, there is a problem that the performance deteriorates. Therefore, in the related art, it has been considered to suppress the leakage current by increasing the impurity concentration inside the substrate. For example, SMSze, Physics of Semiconductor Device (Physics of Semiconductor Device
s) Second Edition, Published by Wiley, New York, 488
As can be seen on the page, it is practiced to form a high concentration layer inside the substrate.

[0005]

In the above prior art, in order to further shorten the channel length, it is necessary to increase the concentration of the high concentration impurity layer inside the substrate. At this time, since the high-concentration impurity layer is also formed under the source and drain diffusion layers, there arises a problem that the parasitic capacitance between the source and drain and the substrate increases and the leak current increases.

An object of the present invention is to provide a high-concentration impurity layer inside a substrate for suppressing punch-through under the gate (channel portion) and under the insulating layer on the side surface of the gate (side portions on both sides of the gate).
It is an object of the present invention to provide a semiconductor device in which the high-concentration impurity layer does not exist near the source and the drain in order to reduce the parasitic capacitance and the leakage current, which are formed in the above-described method, and a manufacturing method thereof.

[0007]

In order to achieve the above object, the present invention provides an insulated gate field effect transistor in which an insulator layer is formed on the side surface of a gate electrode in a self-aligned manner.
A material having a lower ion transmittance than the gate electrode and the insulating layer or a material thicker than the gate electrode and the insulating layer is selectively deposited or grown on the source and drain substrates, Using the mask as a mask, impurities having the same conductivity type as the substrate are doped by ion implantation. As a result, the high-concentration impurity layer is selectively formed on both sides of the channel portion and the gate, and the source and drain portions do not have the high-concentration impurity layer.

[0008]

A high-concentration impurity layer that suppresses punch-through is formed inside the substrate at both sides of the channel portion and the gate, and a high-concentration impurity layer is not provided at the source and drain portions, resulting in low parasitic capacitance and low leakage current. Is realized.

[0009]

EXAMPLE 1 FIG. 1 shows an element cross section of an insulated gate field effect transistor formed on a silicon substrate having the structure of the present invention.

100 is a silicon substrate, 150 is a field oxide film layer forming an element isolation region, 300 is a gate electrode having a two-layer structure of a polycrystalline silicon layer and a tungsten layer, and 220 and 210 are impurity diffusion layer electrodes (source and source). Drain), 900 is a gate insulating film, 200 is a high-concentration impurity layer formed in the substrate, 400 is a spacer layer formed on the side surface of the gate, 500 is a tungsten layer formed in the source and drain portions, and 960 is an interlayer insulating film. Layers 600 are wiring layers to the gate, source and drain, respectively. The basic transistor structure and its operation are the same as conventional ones.

The high-concentration impurity layer 200 characterizing the structure of the present invention includes (1) a channel portion (immediately below the gate), (2) both side portions of the gate, (3) source and drain portions, and (4) element isolation region. The presence or absence of formation changes in each,
A structure that meets the challenges has been realized.

A method of manufacturing the structure of the present invention will be described with reference to FIGS. Here, as a typical structure, NMOS
Although description will be made using a FET, the same formation can be performed by changing the impurity conductivity type.

In FIG. 2, p-type impurities are added at 10 ¹⁵ cm ^-3.
A silicon substrate containing boron is doped with 10 ¹³ cm ^-2 by an ion implantation method and annealed at 1050 ° C. to form a layer (well) near the surface with a concentration higher than that of the substrate by about one digit. At this time, the well forming step may be omitted. FIG. 2 shows the vicinity of the surface of the substrate, and the substrate 100 shows a well. After forming the well, the substrate surface is thermally oxidized to form a 10 nm silicon oxide film on the entire surface of the substrate. CVD (chemical vapor depo
The silicon nitride film is deposited to a thickness of 120 nm by the sition method, patterned using the photoresist method, and anisotropically etched to process the silicon nitride film. The silicon nitride film is used as a mask to thermally oxidize the substrate, and a portion (element isolation region) not covered with the silicon nitride film has a thickness of 3
An oxide film 150 (field oxide film) of 00 nm is formed. After removing the silicon nitride film by wet etching and further removing the silicon oxide film formed under the silicon nitride film, a gate oxide film 900 having a thickness of 5 nm is formed by thermal oxidation.

In FIG. 3, the polycrystalline silicon layer 310 made conductive by doping phosphorus at a high concentration is subjected to CVD.
Method, a silicon oxide film (910) having a thickness of 100 nm is deposited by a CVD method, and a C film is further deposited.
A silicon nitride film (920) of 100 nm is deposited by the VD method. The silicon nitride film 920, the silicon oxide film 910, and the polycrystalline silicon 310 are anisotropically etched using the resist material patterned by the photoresist method as a mask to form a gate pattern.

In FIG. 4, arsenic 30 k is used as a mask with the 920, 910 and 310 layers processed into the gate pattern.
Ion implantation is performed with an acceleration voltage of eV and a dose amount of 2 × 10 ¹³ cm ⁻² to form a low concentration diffusion layer electrode 210.

In FIG. 5, a silicon oxide film is deposited to a thickness of 100 nm by the CVD method and anisotropically etched,
Silicon oxide film spacers 400 are formed on both sides of the gate pattern.

In FIG. 6, arsenic is used at an acceleration voltage of 30 ke.
Ion implantation is performed with V and a dose amount of 10 ¹⁵ cm ^-2 to form a source / drain diffusion layer 220.

In FIG. 7, tungsten is selectively deposited on the source and drain substrates by a selective CVD method to form a tungsten layer 500.

In FIG. 8, the silicon nitride film 920 is removed by anisotropic etching. As a result, in the gate pattern portion, the thickness of the silicon oxide film 910 is about 10 n.
m, the thickness of the polycrystalline silicon 310 is about 100 nm, and the thickness of the silicon oxide film 400 is about 200 n on both sides of the gate.
m, the element isolation region has a thickness of the field oxide film 150 of about 300 nm, and the source and drain portions have a mask shape covered with the tungsten layer 500. Accelerating voltage of 1 for boron at a dose of 5 × 10 ¹³ cm ^-2
The high-concentration impurity layer 200 can be obtained by implanting ions at 00 keV. This ion implantation is
The implantation depth may be set so that it reaches the substrate through the spacers formed on both sides of the gate or the substrate surface of the channel portion has a concentration capable of realizing an arbitrary threshold value.

In FIG. 9, the silicon oxide film 910 is removed by anisotropic etching to remove the polycrystalline silicon layer 31.
After exposing 0, tungsten is selectively deposited again on the polycrystalline silicon layer 310 and the tungsten layer 500 on the source and drain by the selective CVD method,
A gate electrode 300 having a double structure of a polycrystalline silicon layer and a tungsten layer is formed.

In FIG. 10, an interlayer insulating film 960 whose surface is flattened is formed.

In FIG. 11, contact holes to each electrode are formed in the interlayer insulating film 960.

Further, in FIG. 12, aluminum is deposited by the sputtering method and processed on the pattern by using the photoresist method to form the wiring 600.

Here, the element isolation is performed also in the high-concentration impurity layer 20.
However, a conventional method known as a field implantation method, in which an impurity having the same conductivity type as the substrate is doped by ion implantation at the time of patterning before forming the field oxide film thickness 150, can be used.

(Embodiment 2) A gate oxide film 900 is formed by the same process as in Embodiment 1.

In FIG. 13, the polycrystalline silicon layer 310 which is made conductive by doping phosphorus at a high concentration is CV.
After the thickness of 100 nm is deposited by the D method, the silicon oxide film 910 of 100 nm is deposited by the CVD method. After the gate pattern is formed by anisotropically etching the silicon oxide film 910 and the polycrystalline silicon layer 310 using the resist material patterned using the photoresist method as a mask,
The low concentration diffusion layer electrode 210 is formed as in the first embodiment.
Next, a silicon nitride film is deposited to a thickness of 100 nm by the CVD method,
By anisotropically etching, the silicon nitride film spacers 410 are formed on both sides of the gate pattern, and the source / drain diffusion layer electrodes 220 are formed as in the first embodiment.
Tungsten is selectively deposited on the source and drain substrates by a selective CVD method to form a tungsten layer 500. As a result, the high-concentration impurity layer 2 similar to that of the first embodiment is formed.
00 can be formed.

Example 3 A high concentration impurity layer 200 is formed as in Example 1. At this time, the source / drain diffusion layer electrode 220 is not formed. The gate electrode is non-doped polycrystalline silicon.

In FIG. 14, the tungsten layer 500 is shown.
Using a mask (not shown) as a mask, phosphorus is ion-implanted at an accelerating voltage of 25 keV and a dose amount of 10 ¹⁶ cm ^-2 to make the polycrystalline silicon layer conductive, thereby forming a gate electrode 300. After removing the tungsten layer 500 by the wet etching method, a silicon oxide film (930) 8 nm is deposited by the CVD method, and arsenic is accelerated at an acceleration voltage of 30 keV and a dose amount of 10 ¹⁵ cm.
^-2 ion-implanted source / drain diffusion layer electrode 22
0 can be formed.

As shown in FIG. 15, after forming the high-concentration impurity layer 200, the tungsten layer 500 (not shown) and the silicon oxide film 910 (not shown) are etched and the spacer 400 (not shown) is removed. The gate 300 can be ion-implanted into a mask to form a diffusion layer 220 serving as a source and a drain. In addition, the spacer 4
Source / drain diffusion layer electrode 220 before forming 00
Can be formed.

[0030]

EFFECT OF THE INVENTION Punch-through is suppressed by the high-concentration impurity layers formed on the gate in a self-aligned manner at the channel portion and both sides of the gate, and the high-concentration impurity layers are not provided in the source and drain portions. Excellent device characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view of an element according to an embodiment of the present invention.

FIG. 2 is a sectional view of the element in the first step showing the manufacturing method of the present invention.

FIG. 3 is a sectional view of the element in the second step showing the manufacturing method of the present invention.

FIG. 4 is a sectional view of the element in the third step showing the manufacturing method of the present invention.

FIG. 5 is a sectional view of the element in the fourth step showing the manufacturing method of the present invention.

FIG. 6 is a sectional view of the element in the fifth step showing the manufacturing method of the present invention.

FIG. 7 is a sectional view of an element in a sixth step showing the manufacturing method of the present invention.

FIG. 8 is a sectional view of the element in the seventh step showing the manufacturing method of the present invention.

FIG. 9 is a sectional view of an element in an eighth step showing the manufacturing method of the present invention.

FIG. 10 is a sectional view of an element in a ninth step showing the manufacturing method of the present invention.

FIG. 11 is a sectional view of an element in a tenth step showing the manufacturing method of the present invention.

FIG. 12 is a sectional view of the element in the 11th step showing the manufacturing method of the present invention.

FIG. 13 is a sectional view of an element showing Example 2 of the present invention.

FIG. 14 is a sectional view of an element showing Example 3 of the present invention.

FIG. 15 is a sectional view of an element showing Example 4 of the present invention.

[Explanation of symbols]

100 ... Silicon substrate, 150 ... Field oxide film, 2
00 ... High concentration impurity layer, 210, 220 ... Diffusion layer electrode,
300 ... Gate electrode, 400 ... Oxide film spacer layer, 50
0 ... Tungsten layer, 600 ... Wiring layer, 900 ... Gate insulating film, 960 ... Interlayer insulating film.

Claims (5)

[Claims] 1. An insulated gate field effect transistor comprising a gate electrode provided on a semiconductor substrate with an insulating film interposed therebetween, and an impurity diffusion layer having a conductivity type different from that of the substrate as source and drain electrodes. A semiconductor device having a layer of the same type as the impurities of the substrate and having a high concentration under the gate electrode in the substrate, and the high concentration impurity layer is not formed in the vicinity of the source and the drain. 2. A material having a lower ion transmissivity than the gate electrode and the gate side surface portion, or a material having a larger film thickness than the gate electrode and the gate side surface portion, on the semiconductor substrate outside the gate electrode and the gate side surface portion. Immediately below the gate electrode and directly below the gate side surface by depositing or growing, and using the material as a mask, doping an impurity having the same conductivity type as the impurity of the substrate by an ion implantation method and appropriately selecting the ion implantation energy. In the method for manufacturing a semiconductor device, a layer having the same type as the impurities of the substrate and having a high concentration is selectively formed in the substrate. 3. A method for manufacturing a semiconductor device, wherein the gate electrode is formed into a conductive type by doping the gate electrode with an impurity using the material of claim 2 as a mask. 4. A semiconductor device, wherein the material of claim 2 is a material selectively deposited or grown on silicon. 5. The semiconductor device according to claim 4, wherein the material is tungsten.