JP3073685B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a structure of a power FET requiring a high withstand voltage and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, demand for field effect transistors, particularly gallium arsenide (GaAs) MESFETs, has been greatly increased with the development of communication equipment mainly for mobile phones due to their excellent performance. Among them, a power FET used for a transmission amplifier and the like is a low-voltage operation and low power consumption Ga.
Utilizing the features of the As substrate, it has been dramatically increased. In particular, recently, with the progress of communication systems from analog to digital, devices with lower distortion have been demanded. A GaAs MESFET using an epitaxial film or an FET in which an undoped layer containing no impurity is formed immediately below a gate electrode to improve the breakdown voltage (especially, MISFET: M
etal Insulator Semiconductor
tor FET) and the like are suitable for these low-distortion power devices, and further improved performance is achieved.

[0003] Important measures for reducing distortion are improvement of drain withstand voltage, flat drain conductance and flat transconductance.

The drain breakdown voltage is determined by the impurity concentration just below the gate and the distance between the gate and the drain. Naturally, as seen in the example of the MISFET, the lower the impurity concentration immediately below the gate, the better the breakdown voltage, and the longer the distance between the gate and the drain, the better the breakdown voltage.

In order to realize a flat drain conductance, it is necessary to increase the effective gate length to some extent and to increase the aspect ratio between the effective gate length and the channel thickness (effective gate length / channel thickness). The configuration of a conventional MISFET having such a structure will be described with reference to the drawings.

FIG. 35 is a sectional view showing a conventional GaAs MISFET. In FIG. 35, 51 is a semi-insulating substrate made of GaAs, 52 is a conductive layer made of n-type GaAs doped with Si as an impurity, 53 is an undoped layer made of GaAs or AlGaAs not doped with an impurity. , Conductive layer 52 and undoped layer 5
3 is generally formed using a crystal growth method. Also, 5
Reference numeral 4 denotes n doped with Si at a high concentration by an ion implantation method.
^A contact region made of ⁺ type GaAs; 55, a drain electrode; 56, a source electrode;
The source electrode 56 is formed by an evaporation method such as AuGe. Reference numeral 57 denotes a gate electrode, and 58 denotes an element isolation region. The element isolation region 58 is formed by insulating the semi-insulating substrate 51 by an ion implantation method of oxygen, hydrogen, boron, or the like.

Furthermore, in order to realize a flat transconductance, the peak of the impurity concentration in the active region may be set at a deep position in the semi-insulating substrate 51.

[0008]

However, in the conventional GaAs MISFET structure, the withstand voltage is improved by adopting the MIS structure as compared with the MESFET. However, since the electric field is concentrated at the end of the gate electrode, the drain withstand voltage is reduced. It depends only on the distance between the gate and the drain. Therefore, in order to achieve a higher breakdown voltage in order to realize a lower distortion, the distance between the gate and the drain must be increased. However, increasing the distance between the gate and drain increases the resistance between the gate and drain,
There is a problem that the on-resistance of the FET increases and various characteristics during low-voltage operation deteriorate.

Further, if the aspect ratio is increased by increasing the gate length in order to realize a low distortion, there is a problem that the gate length is increased and the gain is reduced.

As described above, low distortion, low voltage, and high gain are contradictory. In a conventional field-effect transistor, low distortion, low voltage, and high gain are required. It was difficult to be compatible.

In view of the above, according to the present invention, the on-resistance can be suppressed even if the withstand voltage between the gate and the drain is increased, and a flat drain conductance can be obtained even if the gate length is shortened for high gain. Accordingly, an object of the present invention is to provide a field-effect transistor capable of realizing both low distortion and low voltage and high gain, and a method for manufacturing such a field-effect transistor.

[0012]

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

In order to achieve the above object,
According to a first aspect of the present invention, there is provided a method of manufacturing a field-effect transistor, comprising the steps of: forming a conductive layer doped with an impurity and an undoped impurity not doped on a semi-insulating substrate by a crystal growth method; Forming layers sequentially;
Forming a step in the undoped layer such that the drain side is thicker than the source side by selectively etching the surface of the undoped layer; and straddling the step on the undoped layer. Forming a gate electrode made of a refractory metal in a region, forming a side wall made of an insulator on a side surface of the gate electrode, and forming an impurity on the semi-insulating substrate using the gate electrode and the side wall as a mask. Forming a contact region for the drain and the source by performing a heat treatment after the ion implantation to the concentration.

According to a second aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising the steps of:
A step of sequentially forming a conductive layer doped with impurities and an undoped layer not doped with impurities by a crystal growth method, and selectively etching a surface portion of the undoped layer so that the drain side of the undoped layer has a source side. A step of forming a step portion that is thicker than the side,
Forming a protrusion made of an insulator at a distance from the step on the undoped layer below the step, and forming the protrusion on the protrusion and on the undoped layer. Forming a gate electrode with a refractory metal in a straddling region; and ion-implanting impurities at a high concentration into the semi-insulating substrate using the gate electrode and the protrusions as a mask; And a step of forming a region.

According to a third aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising the steps of:
A step of sequentially forming a conductive layer doped with impurities, an undoped layer not doped with impurities, and a contact layer doped with impurities at a high concentration by a crystal growth method,
A step of partially exposing the undoped layer by selectively etching the contact layer; and a step of selectively etching a surface portion of an exposed region in the undoped layer to selectively expose the undoped layer. And a step of forming a gate electrode in a region over the undoped layer over a step on the drain side of the recess.

According to the constitutions of claims 1 to 3 , after selectively etching the surface of the undoped layer, a step is formed in the undoped layer such that the drain side is thicker than the source side. Since the gate electrode is formed in a region straddling the step portion, the gate electrode can be formed in a region straddling the step portion on the undoped layer having the step portion such that the drain side is thicker than the source side.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising the steps of:
A step of sequentially forming a conductive layer doped with impurities and an undoped layer not doped with impurities by a crystal growth method, and selectively etching the undoped layer to expose a source-side region in the conductive layer. Forming a contact region of a drain and a source by performing a heat treatment after high-concentration ion implantation of impurities into the semi-insulating substrate; and performing a process on the exposed region of the conductive layer and the undoped region. Forming a gate electrode over the layer.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising the steps of:
A step of sequentially forming a conductive layer doped with impurities and an undoped layer not doped with impurities by a crystal growth method, and selectively etching the undoped layer to expose a source-side region in the conductive layer. Forming a gate electrode made of a high melting point metal over an exposed region of the conductive layer and over the undoped layer, and forming a side wall made of an insulator on a side surface of the gate electrode. After the step, the semi-insulating substrate is ion-implanted with a high concentration of impurities using the gate electrode and the side wall as a mask, and then heat-treated.
Forming a drain and source contact region.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising the steps of:
A step of sequentially forming a conductive layer doped with impurities and an undoped layer not doped with impurities by a crystal growth method, and selectively etching the undoped layer to expose a source-side region in the conductive layer. And forming a protrusion made of an insulator at an interval from the undoped layer in an exposed region on the conductive layer, and on the protrusion, on an exposed region in the conductive layer and Forming a gate electrode of a refractory metal over the undoped layer, performing high-concentration ion implantation on the semi-insulating substrate using the gate electrode and the protrusions as a mask, and performing heat treatment. And a step of forming a source contact region.

A solution taken by the invention of claim 7 is that a method for manufacturing a field effect transistor is provided on a semi-insulating substrate.
A step of sequentially forming a conductive layer doped with impurities, an undoped layer not doped with impurities, and a contact layer doped with impurities at a high concentration by a crystal growth method,
Selectively etching the contact layer to partially expose the undoped layer, and selectively etching an exposed region in the undoped layer to expose a source-side region in the conductive layer. And a step of forming a gate electrode over the exposed region of the conductive layer and over the undoped layer.

[0034] According to this arrangement 4-7, by selectively etching the undoped layer, after exposing the area of the source side of the conductive layer, on the exposed region of the conductive layer and on the undoped layer Since the gate electrode is formed so as to straddle, the gate electrode can be formed so as to straddle the conductive layer and the undoped layer formed only on the drain side.

[0035]

A solution taken by the invention of claim 8 is that a method of manufacturing a field effect transistor is provided on a semi-insulating substrate.
Forming a conductive layer doped with impurities by a crystal growth method, and selectively etching a surface portion of the conductive layer to form a step on the conductive layer such that the drain side becomes thicker than the source side. Forming a portion, a step of forming a gate electrode made of a high melting point metal in a region over the step portion on the conductive layer, and a step of forming a side wall made of an insulator on a side surface of the gate electrode, Forming a drain and a source contact region by performing a heat treatment after high-concentration ion implantation of impurities into the semi-insulating substrate using the gate electrode and the side wall as a mask. It is.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising the steps of:
Forming a conductive layer doped with impurities by a crystal growth method, and selectively etching a surface portion of the conductive layer to form a step on the conductive layer such that the drain side becomes thicker than the source side. Forming a protrusion, and forming a protrusion made of an insulator at a distance from the step on a lower portion of the step on the conductive layer; and forming the protrusion on the conductive layer. Forming a gate electrode made of a refractory metal over the region over the protrusions and the protrusions, and heat-treating the semi-insulating substrate with high-concentration ions of impurities using the gate electrodes and the protrusions as a mask. And a step of forming a source contact region.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a field-effect transistor, comprising the steps of: forming a conductive layer doped with impurities and a highly doped impurity on a semi-insulating substrate by a crystal growth method; Forming the contact layer sequentially, the step of partially exposing the conductive layer by selectively etching the contact layer, and the step of selectively etching the surface portion of the exposed region in the conductive layer. A step of forming a concave portion in an exposed region of the conductive layer, and a step of forming a gate electrode in a region over the conductive layer over a step portion on the drain side of the concave portion. Is what you do.

[0039]

According to the constitution of claims 8 to 10 , after selectively etching the surface portion of the conductive layer, a step is formed in the conductive layer so that the drain side is thicker than the source side. Since the gate electrode is formed in the region straddling the step portion, the gate electrode can be formed in the region straddling the step portion on the conductive layer having the step portion such that the drain side is thicker than the source side.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a field effect transistor according to one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a first type of the present invention, a first type.
GaAs as Field Effect Transistor According to Embodiment
1 shows a cross-sectional structure of an sMISFET. In FIG. 1, 1 is a semi-insulating substrate made of GaAs, 2A is Si
Is a conductive layer made of n-type GaAs doped with impurities, 3A is an undoped layer made of GaAs or AlGaAs not doped with an impurity, and the undoped layer 3A has a layer thickness on the drain side more than the source side by etching. It has a step portion formed so as to be formed.
The conductive layer 2A and the undoped layer 3A are generally formed using a crystal growth method. 4A is a contact region made of n ⁺ -type GaAs doped with Si at a high concentration by ion implantation, 5 is a drain electrode, 6 is a source electrode, and the drain electrode 5 and the source electrode 6 are AuGe.
And the like. 7 is a gate electrode, 8
Is an element isolation region, and the element isolation region 8 is formed by insulating the semi-insulating substrate 1 by ion implantation of oxygen, hydrogen, boron, or the like.

The features of the first embodiment are, as described above,
The undoped layer 3A has a step portion in which the drain side is formed thicker than the source side by etching.

FIG. 2 shows a second type of the present invention.
GaAs as Field Effect Transistor According to Embodiment
2 shows a cross-sectional structure of an sMES / MISFET. Second
In the embodiment, the same reference numerals are given to the same elements as those in the first embodiment, and the description will be omitted. still,
In FIG. 2, 3B denotes Ga which is not doped with impurities.
It is an undoped layer made of As or AlGaAs.

The feature of the second embodiment is that the undoped layer 3B
Is formed only on the drain side below the gate electrode 7 on the conductive layer 2A.

Therefore, the conductive layer 2 is formed under the gate electrode 7.
Is exposed, the conductive layer 2 is etched before the gate electrode 7 is formed, and the thickness of the conductive layer 2 is adjusted to adjust the threshold value and current value of the FET. Can be.

FIG. 3 shows a third type of the present invention.
GaAs as Field Effect Transistor According to Embodiment
2 shows a cross-sectional structure of an sMESFET. In the third embodiment, the same elements as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 3, 2B is an n-type G doped with Si as an impurity.
It is a conductive layer made of aAs.

The features of the third embodiment are that the undoped layer 3A in the first embodiment is not formed and that the conductive layer 2B has a step portion such that the drain side is thicker than the source side. And a point that the gate electrode 7 is formed so as to extend over the step portion of the conductive layer 2B.

In the third embodiment, the undoped layer 3
Since A is not formed, the breakdown voltage is lower than that of the first embodiment and the second embodiment. However, the breakdown voltage is lower than that of the conventional MESFET in which the gate electrode 57 is formed on the flat conductive layer 52 as shown in FIG. Also the withstand voltage is improved.

In the first to third embodiments, the semi-insulating substrate 1 made of GaAs is used. However, the semi-insulating substrate 1 can be made of any material other than GaAs. .

Hereinafter, a method of manufacturing the above-described first type field effect transistor will be described.

FIGS. 4 and 5 are cross-sectional views showing steps of a first method of manufacturing a first type of field effect transistor.

First, as shown in FIG. 4A, a conductive layer 2 and an undoped layer 3 are sequentially laminated on a semi-insulating substrate 1 by a crystal growth method. Next, as shown in FIG. 4B, after a resist pattern 31 is formed on the undoped layer 3, a wet etching method using the resist pattern 31 as a mask is performed on the source side of the surface of the undoped layer 3 on the source side. By removing the region, a step structure is formed such that the drain side becomes thicker than the source side, and then the resist pattern 31 is removed. Next, as shown in FIG.
After a resist pattern 32 is formed on the undoped layer 3, Si is doped at a high concentration by ion implantation using the resist pattern 32 as a mask to form source and drain contact regions 4A. Thereafter, after removing the resist pattern 32, a high-temperature heat treatment is performed to activate the contact region 4A.

Next, as shown in FIG. 5A, after a resist pattern 33 is formed on the semi-insulating substrate 1, a metal film is deposited using the resist pattern 33 as a mask. Is lifted off to form a drain electrode 5 and a source electrode 6. next,
As shown in FIG. 5B, after forming a resist pattern 34 on the semi-insulating substrate 1 so that the step of the undoped layer 3 is exposed, a metal film is deposited using the resist pattern 34 as a mask. Thereafter, the gate electrode 7 is formed by lifting off the resist pattern 34. As the configuration of the gate electrode 7, a three-layer structure of Ti / Pt / Au, a two-layer structure of Ti / Al, or a single-layer structure of Al can be used. Next, when element isolation regions 8 are formed by ion implantation of hydrogen ions or the like using a resist pattern (not shown) as a mask, as shown in FIG.
A first-type field-effect transistor in which a flat conductive layer 2A and an undoped layer 3A having a step portion are formed below the gate electrode 7 is obtained.

In the first manufacturing method, the formation method and the formation process of the element isolation region 8 can be changed as appropriate. Instead of the ion implantation method, the peripheral region is removed by simple etching to remove the element isolation region 8. May be formed.

FIGS. 6 and 7 are cross-sectional views showing the steps of a second method of manufacturing the first type of field-effect transistor. The feature of the second manufacturing method is that a refractory metal such as a tungsten-based or molybdenum-based metal is used for the gate electrode 7, so that a heat treatment step can be performed after the gate electrode 7 is formed.

The steps shown in FIGS. 6A and 6B correspond to FIG.
This is the same as the steps shown in (a) and (b). Then, FIG.
As shown in (c), a gate electrode 7 is formed of the above-mentioned refractory metal in a region over the step on the undoped layer 3. As the gate electrode 7, a single-layer structure of WSi, WSiN, or Mo can be used.

Next, as shown in FIG. 7A, after an insulating film 9 made of SiN or SiO ₂ is deposited on the entire surface, the insulating film 9 is subjected to anisotropic dry etching. As shown in FIG. 7B, side walls 9A are formed on both sides of the gate electrode 7. Next, after a resist pattern 35 is formed on the semi-insulating substrate 1, the gate electrode 7, the side wall 9A
Then, Si is doped at a high concentration by ion implantation using the resist pattern 35 as a mask to form source and drain contact regions 4A. Thereafter, a high-temperature heat treatment is performed to activate contact region 4A. next,
When the drain electrode 5, the source electrode 6, and the element isolation region 8 are formed in the same manner as in the first manufacturing method, a flat conductive layer 2A is formed below the gate electrode 7 as shown in FIG.
Thus, a first-type field-effect transistor in which the undoped layer 3A having the step structure is formed is obtained.

According to the second manufacturing method, the contact region 4A is formed in a self-aligned manner using the side wall 9A of the gate electrode 7 as a mask.
, The source and drain resistances are low.

FIGS. 8 and 9 are cross-sectional views showing steps of a third method of manufacturing a first type field effect transistor. A feature of the third manufacturing method is that a sidewall 10 made of an insulating layer is formed on the source side of the gate electrode 7 before the step of forming the gate electrode 7.

The steps shown in FIGS. 8A and 8B correspond to FIG.
This is the same as the steps shown in (a) and (b). Thereafter, an insulating layer made of a SiN film or SiO ₂ is formed on the entire surface of the semi-insulating substrate 1, and the insulating layer is patterned to obtain a structure shown in FIG.
As shown in (c), a side wall 10 is formed on the undoped layer 3 in a region closer to the source than the step.

Next, after forming a metal film made of the above-mentioned refractory metal over the entire surface of the semi-insulating substrate 1 by a vapor deposition method, the metal film is patterned and shown in FIG. As described above, the gate electrode 7 is formed on the region across the step in the undoped layer 3 and on the side wall 10. Next, after forming a resist pattern 36 on the semi-insulating substrate 1,
Si is heavily doped by an ion implantation method using the gate electrode 7, the side wall 10, and the resist pattern 36 as a mask to form source and drain contact regions 4A. Thereafter, a high-temperature heat treatment is performed to form the contact region 4.
Activate A. Next, similarly to the first manufacturing method, when the drain electrode 5, the source electrode 6, and the element isolation region 8 are formed, a flat conductive layer is formed below the gate electrode 7, as shown in FIG. A first-type field-effect transistor in which 2A and an undoped layer 3A having a step structure are formed is obtained.

According to the third manufacturing method, the contact region 4A on the source side is formed in a self-aligned manner, and the contact region 4A on the drain side is formed by the resist pattern 36, so that the degree of freedom in designing the source resistance and the drain withstand voltage is increased. Increases.

FIGS. 10 and 11 are cross-sectional views showing the steps of a fourth method of manufacturing a first type field effect transistor. A feature of the fourth manufacturing method is that an ion implantation method is not used for forming a contact region.

First, as shown in FIG. 10A, a conductive layer 2, an undoped layer 3, and a contact layer 4 are sequentially stacked on a semi-insulating substrate 1 by using a crystal growth method. Next, FIG.
0 (b), after forming a resist pattern 37 on the contact layer 4, a part of the contact layer 4 is removed by a wet etching method using the resist pattern 37 as a mask, and the surface of the undoped layer 3 is removed. To expose. Next, as shown in FIG. 10C, a drain electrode 5 and a source electrode 6 are formed on the contact layer 4.

Next, as shown in FIG. 11A, after forming a resist pattern 38 on the semi-insulating substrate 1,
The surface of the undoped layer 3 is partially removed by wet etching using the resist pattern 38 as a mask to form a recess 3 a in the undoped layer 3. Next, FIG.
As shown in FIG. 1, an undoped layer 3 is formed on a semi-insulating substrate 1.
After forming a resist pattern 39 having an opening straddling the step on the drain side of the concave portion 3a, a metal film is deposited using the resist pattern 39 as a mask. Thereafter, when the resist pattern 39 is lifted off to form the gate electrode 7, as shown in FIG. 11C, a flat conductive layer 2A and an undoped layer 3A having a step structure are formed below the gate electrode 7. The obtained first type field effect transistor is obtained.

According to the fourth manufacturing method, the undoped layer 3
Since the drain electrode 5 and the source electrode 6 are formed before the formation of the undoped layer, the current can be monitored when the undoped layer 3 is removed. Further, since the gate electrode 7 is formed last, there is no need to use a refractory metal for the gate electrode 7.

Hereinafter, a method of manufacturing the above-described second type field effect transistor will be described.

FIGS. 12 and 13 are cross-sectional views showing each step of the first method of manufacturing the second type field-effect transistor.

First, as shown in FIG. 12A, a conductive layer 2 and an undoped layer 3 are sequentially stacked on a semi-insulating substrate 1 by a crystal growth method. Next, as shown in FIG. 12B, after a resist pattern 31 is formed on the undoped layer 3, a source-side region in the undoped layer 3 is removed by a wet etching method using the resist pattern 31 as a mask. Thus, the undoped layer 3 is left only on the drain side. Next, as shown in FIG.
After forming a resist pattern 32 thereon, Si is doped at a high concentration by ion implantation using the resist pattern 32 as a mask to form source and drain contact regions 4A. Then, after removing the resist pattern 32, a high-temperature heat treatment is performed to form the contact region 4A.
Activate.

Next, as shown in FIG. 13A, after a resist pattern 33 is formed on the semi-insulating substrate 1, a metal film is deposited using the resist pattern 33 as a mask.
Then, the drain electrode 5 and the source electrode 6 are formed by lifting off the resist pattern 33. Next, a resist pattern 34 is formed on the semi-insulating substrate 1 such that the region from which the undoped layer 3 is removed and the region where the undoped layer 3 remains are exposed, and a metal film is formed using the resist pattern 34 as a mask. Then, the gate electrode 7 is formed by lifting off the resist pattern 34. Next, when element isolation regions 8 are formed by ion implantation of hydrogen ions or the like using a resist pattern (not shown) as a mask, a flat conductive layer 2A is formed below the gate electrode 7 as shown in FIG. And a second type field effect transistor having the undoped layer 3B only on the drain side.

FIGS. 14 and 15 are cross-sectional views showing the steps of a second method for manufacturing a field-effect transistor of the second type.

The steps shown in FIGS. 14A and 14B correspond to the steps shown in FIG.
This is the same as the steps shown in FIGS. 2 (a) and (b). Thereafter, a gate electrode 7 is formed of a high melting point metal on the region where the undoped layer 3 is removed and the conductive layer 2 is exposed and on the region where the undoped layer 3 remains.

Next, as shown in FIG.
After an insulating film 9 made of SiO ₂ or SiO ₂ is deposited on the entire surface, anisotropic dry etching is performed on the insulating film 9 to form side walls on both sides of the gate electrode 7 as shown in FIG. 9A is formed. Next, after a resist pattern 35 is formed on the semi-insulating substrate 1, the gate electrode 7, the side walls 9 A and the Si and Si are doped at a high concentration by ion implantation using the resist pattern 35 as a mask. The region 4A is formed. Thereafter, a high-temperature heat treatment is performed to activate contact region 4A. Next, similarly to the first manufacturing method, when the drain electrode 5, the source electrode 6, and the element isolation region 8 are formed, FIG.
As shown in (2), a second type field effect transistor having a flat conductive layer 2A below the gate electrode 7 and an undoped layer 3B existing only on the drain side is obtained.

FIGS. 16 and 17 are cross-sectional views showing steps of a third method for manufacturing a field-effect transistor of the second type.

The steps shown in FIGS. 16A and 16B correspond to the steps shown in FIG.
This is the same as the steps shown in FIGS. 2 (a) and (b). Thereafter, an insulating layer made of a SiN film or SiO ₂ is formed on the entire surface of the semi-insulating substrate 1, and the insulating layer is patterned to obtain a structure shown in FIG.
As shown in FIG. 6C, the side wall 10 is formed on the conductive layer 2 exposed by removing the undoped layer 3.

Next, a metal film made of a high melting point metal is formed over the entire surface of the semi-insulating substrate 1 by a vapor deposition method.
The metal film is patterned, and a gate electrode 7 is formed on the conductive layer 2, the undoped layer 3, and the side wall 10 as shown in FIG. Next, after forming a resist pattern 36 on the semi-insulating substrate 1, the gate electrode 7, the side wall 1
The source and drain contact regions 4A are formed by doping Si at a high concentration by an ion implantation method using the 0 and the resist pattern 36 as a mask. Thereafter, a high-temperature heat treatment is performed to activate contact region 4A. Next, similarly to the first manufacturing method, when the drain electrode 5, the source electrode 6, and the element isolation region 8 are formed, FIG.
As shown in (2), a second type field effect transistor having a flat conductive layer 2A below the gate electrode 7 and an undoped layer 3B existing only on the drain side is obtained.

FIGS. 18 and 19 are cross-sectional views showing steps of a fourth method of manufacturing a second type field effect transistor.

First, as shown in FIG. 18A, a conductive layer 2, an undoped layer 3, and a contact layer 4 are sequentially stacked on a semi-insulating substrate 1 by using a crystal growth method. Next, FIG.
As shown in FIG. 8B, after a resist pattern 37 is formed on the contact layer 4, a part of the contact layer 4 is removed by wet etching using the resist pattern 37 as a mask, and the surface of the undoped layer 3 is removed. Expose. Next, as shown in FIG. 18C, a drain electrode 5 and a source electrode 6 are formed on the contact layer 4.

Next, as shown in FIG. 19A, after forming a resist pattern 38 on the semi-insulating substrate 1,
The source-side region in the undoped layer 3 is removed by a wet etching method using the resist pattern 38 as a mask. Next, as shown in FIG. 19B, a resist pattern 39 is formed on the semi-insulating substrate 1 so that the region where the undoped layer 3 is removed and the region where the undoped layer 3 remains are opened. Then, a metal film is deposited using the resist pattern 39 as a mask. After that, when the resist pattern 39 is lifted off to form the gate electrode 7, FIG.
As shown in FIG. 9C, a second type field effect transistor having a flat conductive layer 2A below the gate electrode 7 and an undoped layer 3B existing only on the drain side is obtained.

Hereinafter, a method of manufacturing the above-described third type field effect transistor will be described.

FIGS. 20 and 21 are cross-sectional views showing each step of the first method of manufacturing the third type field effect transistor.

First, as shown in FIG. 20A, a conductive layer 2 is laminated on a semi-insulating substrate 1 by a crystal growth method. Next, as shown in FIG. 20B, after forming a resist pattern 31 on the conductive layer 2, the resist pattern 31 is formed.
The region on the source side in the surface portion of the conductive layer 2 is removed by a wet etching method using as a mask to form a step structure in which the drain side is thicker than the source side.
After that, the resist pattern 31 is removed. Next, FIG.
As shown in FIG. 1C, after a resist pattern 32 is formed on the conductive layer 2, Si is doped at a high concentration by ion implantation using the resist pattern 32 as a mask, and the source and drain contact regions 4A are formed. To form Thereafter, after removing the resist pattern 32, a high-temperature heat treatment is performed to activate the contact region 4A.

Next, as shown in FIG. 21A, after a resist pattern 33 is formed on the semi-insulating substrate 1, a metal film is deposited using the resist pattern 33 as a mask.
Then, the drain electrode 5 and the source electrode 6 are formed by lifting off the resist pattern 33. Next, as shown in FIG. 21B, a resist pattern 34 is formed on the semi-insulating substrate 1 so that a step portion of the conductive layer 2 is exposed, and then the resist pattern 34 is used as a mask to form a metal film. , And then the resist pattern 34
Is lifted off to form a gate electrode 7.
Next, when the element isolation region 8 is formed by ion implantation of hydrogen ions or the like using a resist pattern (not shown) as a mask, the gate electrode 7 is formed as shown in FIG.
Thus, a third type field effect transistor in which the conductive layer 2B having a step structure is formed underneath is obtained.

FIGS. 22 and 23 are cross-sectional views showing each step of the second method of manufacturing the third type field effect transistor.

The steps shown in FIGS. 22A and 22B correspond to the steps shown in FIG.
This is the same as the steps shown in FIGS. Thereafter, as shown in FIG. 22C, a gate electrode 7 is formed of a high melting point metal in a region over the step on the conductive layer 2.

Next, as shown in FIG.
After an insulating film 9 made of SiO ₂ or SiO ₂ is deposited on the entire surface, the insulating film 9 is anisotropically dry-etched to form side walls on both sides of the gate electrode 7 as shown in FIG. 9A is formed. Next, after a resist pattern 35 is formed on the semi-insulating substrate 1, the gate electrode 7, the side walls 9 A and the Si and Si are doped at a high concentration by ion implantation using the resist pattern 35 as a mask. The region 4A is formed. Thereafter, a high-temperature heat treatment is performed to activate contact region 4A. Next, similarly to the first manufacturing method, when the drain electrode 5, the source electrode 6, and the element isolation region 8 are formed, FIG.
As shown in (2), a second type field effect transistor in which a conductive layer 2B having a step structure is formed below the gate electrode 7 is obtained.

FIGS. 24 and 25 are cross-sectional views showing steps of a third method of manufacturing a third type of field effect transistor.

The steps shown in FIGS. 24A and 24B correspond to the steps shown in FIG.
This is the same as the steps shown in FIGS. Then, after forming an insulating layer made of SiN or SiO ₂ on the entire surface of the semi-insulating substrate 1, the insulating layer is patterned and
As shown in (c), the side wall 10 is formed on the conductive layer 2 at a portion closer to the source than the step.

Next, after a metal film made of a high melting point metal is formed on the semi-insulating substrate 1 over the entire surface by a vapor deposition method,
By patterning the metal film, as shown in FIG.
The gate electrode 7 is formed on the gate electrode 0. Next, after a resist pattern 36 is formed on the semi-insulating substrate 1, Si is doped at a high concentration by an ion implantation method using the gate electrode 7, the side wall 10, and the resist pattern 36 as a mask, and the source and the drain are formed. The contact region 4A is formed. Thereafter, a high-temperature heat treatment is performed to activate contact region 4A. Next, similarly to the first manufacturing method, when the drain electrode 5, the source electrode 6, and the element isolation region 8 are formed,
As shown in FIG. 25C, a third type field effect transistor in which the conductive layer 2B having a step structure is formed below the gate electrode 7 is obtained.

FIGS. 26 and 27 are cross-sectional views showing the steps of a fourth method of manufacturing a field-effect transistor of the second type.

First, as shown in FIG. 26A, a conductive layer 2 and a contact layer 4 are sequentially stacked on a semi-insulating substrate 1 by using a crystal growth method. Next, as shown in FIG. 26B, after forming a resist pattern 37 on the contact layer 4, a part of the contact layer 4 is removed by wet etching using the resist pattern 37 as a mask to form a conductive layer. The surface of No. 2 is exposed. Next, as shown in FIG. 26C, a drain electrode 5 and a source electrode 6 are formed on the contact layer 4.

Next, as shown in FIG. 27A, after forming a resist pattern 38 on the semi-insulating substrate 1,
The surface of the conductive layer 2 is partially removed by a wet etching method using the resist pattern 38 as a mask.
A concave portion 2a is formed in the substrate. Next, as shown in FIG. 27 (b), after forming a resist pattern 39 having an opening over the step portion on the drain side of the concave portion 2a of the conductive layer 2 on the semi-insulating substrate 1, A metal film is deposited using the resist pattern 39 as a mask. Thereafter, when the resist pattern 39 is lifted off to form the gate electrode 7, as shown in FIG. 27C, a third type of conductive layer 2B having a step structure is formed below the gate electrode 7. A field effect transistor is obtained.

FIGS. 28 and 29 are cross-sectional views showing the steps of the fifth method of manufacturing the third type field effect transistor. The difference from the first to fourth manufacturing methods is that they are formed using only the ion implantation method.

First, as shown in FIG. 28A, after a resist pattern 40 is formed on the semi-insulating substrate 1, Si is doped using the resist pattern 40 as a mask to form the conductive layer 2. Next, as shown in FIG.
After forming a resist pattern 32 on the semi-insulating substrate 1, a contact region 4A is formed by ion implantation using the resist pattern 32 as a mask. Thereafter, after removing the resist pattern 32, a high-temperature heat treatment is performed to activate the contact region 4A. Next, FIG.
As shown in (c), after forming a resist pattern 31 on the semi-insulating substrate 1, a region on the source side on the surface portion of the conductive layer 2 is removed by wet etching using the resist pattern 31 as a mask. To form a step structure such that the drain side is thicker than the source side,
The resist pattern 31 is removed.

Next, as shown in FIG. 29A, after a resist pattern 33 is formed on the semi-insulating substrate 1, a metal film is deposited using the resist pattern 33 as a mask.
Then, the drain electrode 5 and the source electrode 6 are formed by lifting off the resist pattern 33. Next, as shown in FIG. 29B, a resist pattern 34 is formed on the semi-insulating substrate 1 so that the step of the conductive layer 2 is exposed, and the metal film is formed using the resist pattern 34 as a mask. , And then the resist pattern 34
Is lifted off to form a gate electrode 7, as shown in FIG. 29C, a third type field effect transistor in which a conductive layer 2B having a step structure is formed below the gate electrode 7. Is obtained.

FIG. 30 shows a fourth type of the present invention.
GaAs as Field Effect Transistor According to Embodiment
2 shows a cross-sectional structure of an sMESFET. In FIG. 30, 1 is a semi-insulating substrate made of GaAs, and 11 is Ga
An undoped buffer layer made of As, 12 is a conductive layer made of n-type GaAs doped with Si as an impurity, and the conductive layer 12 is formed by etching so that the drain side becomes thicker than the source side. It has a step. Reference numeral 13 denotes a contact region made of n ⁺ -type GaAs doped with Si at a high concentration. The undoped buffer layer 11, the conductive layer 12, and the contact region 13 are generally formed using a crystal growth method. You. 5 is a drain electrode, 6 is a source electrode, and the drain electrode 5 and the source electrode 6 are formed on the contact region 13 by vapor deposition of AuGe or the like. Reference numeral 7 denotes a gate electrode, and the gate electrode 7 is formed in a region straddling a step of the conductive layer 12.

The feature of the fourth embodiment is that, as described above, the conductive layer 12 has the step portion in which the drain side is formed thicker than the source side by etching.
The height of the step is limited, and the height of the step is not more than the thickness of a depletion layer formed inside the semiconductor region on the drain side by the gate electrode 7.

The thickness of the depletion layer means the thickness of the depletion layer formed inside the semiconductor region when the field-effect transistor operates, but the thickness of the depletion layer in a steady state is A sufficient effect can be obtained even if the thickness is large.

When the impurity concentration in the region on the drain side of the step portion in conductive layer 12 is uniform, the thickness of the depletion layer in the steady state is expressed by the following equation ( 1 ).

[0101]

[ Equation 1 ] Here, a is the thickness of the depletion layer, and ΦB is the gate electrode 7.
Is the height of the potential of the Schottky barrier, q is the amount of charge of electrons, ε is the dielectric constant of the region on the drain side of the step in the conductive layer 12, and N is the dielectric constant of the region in the conductive layer 12 from the step. Also, the impurity concentration in the region on the drain side is uniform.

When the impurity concentration in the region of the conductive layer 12 below the gate electrode 7 on the drain side of the step portion is not uniform, the thickness of the depletion layer in the steady state is
It is represented by the following mathematical formula shown in [Equation 2 ].

[0103]

[ Equation 2 ] Here, a is the thickness of the depletion layer, x is the distance of the depletion layer in the depth direction, ΦB is the height of the potential of the Schottky barrier of the gate electrode 7, and q is the charge amount of the electrons. Where ε (x) is the dielectric constant of the region on the drain side of the step portion in the conductive layer 12, and N (x) is the impurity concentration of the region on the drain side of the step portion in the conductive layer 12.

In the fourth embodiment shown in FIG. 30, for example, the gate length is 0.5 μm, the impurity concentration of the conductive layer 12 is 6 × 17 cm ⁻³ of n conductivity type, and the thickness of the conductive layer 12 is 0.0
7 μm, the etching depth of the lower portion of the gate electrode 7 in the conductive layer 12, that is, the height of the step portion of the conductive layer 12 is 0.02 μm, and the thickness of the channel region is 0.05 μm.
m indicates a field-effect transistor.

In the fourth embodiment, since the impurity concentration of the conductive layer 12 is uniform, the thickness of the depletion layer can be determined by the equation shown in [Equation 5]. That is, assuming that the height of the potential of the Schottky barrier is 0.73 V, the thickness of the depletion layer can be estimated to be 0.042 μm. Therefore, the fourth embodiment satisfies the requirement that the height of the step portion of the conductive layer 12 is equal to or less than the thickness of the depletion layer.

In the fourth embodiment, the contact region 13 is on the conductive layer 12 formed by the crystal growth method. Instead, the contact region 13 is formed on the conductive layer 12 formed by the ion implantation method. It may be on the side.

FIG. 31 shows an equipotential diagram as a result of a two-dimensional device simulation of the field-effect transistor according to the fourth embodiment. In FIG. 31, the denser the equipotential line, the stronger the electric field, and the rougher the equipotential line, the weaker the electric field.

FIG. 32 shows the structure of a field-effect transistor as a comparative example for comparison with the field-effect transistor according to the fourth embodiment. In the field-effect transistor according to the comparative example, the height of the step portion of the conductive layer 12 is 0.05 μm, and the thickness of the depletion layer is 0.042 μm.
The structure has a value larger than μm. Conductive layer 1
The conditions other than the height of the step portion 2 are the same as those of the fourth embodiment.

FIG. 33 shows an equipotential diagram as a result of two-dimensional device simulation of a field-effect transistor having a large step according to the comparative example. The bias condition is shown in FIG.
Is the same as

As is clear from the comparison between FIG. 31 and FIG. 33, the equipotential lines of the field-effect transistor according to the fourth embodiment having smaller steps are coarsely distributed, and It can be seen that the electric field concentration is further alleviated in FIG.

FIG. 34 shows a comparison of drain current-drain voltage characteristics in the fourth embodiment and the comparative example obtained by two-dimensional device simulation. In FIG. 34, the solid line indicates the characteristics of the field-effect transistor according to the fourth embodiment in which the height of the step portion is equal to or less than the thickness of the depletion layer, and the broken line indicates that the height of the step portion is smaller than the thickness of the depletion layer. 9 shows characteristics of a field-effect transistor according to a comparative example that is large. The reason why the drain current-drain voltage branches in the middle is that the physical model is changed in the device simulation, and the steep slope is when the physical model that causes a breakdown is adopted, The gradient indicates a case where a calculation that does not cause a breakdown is performed. From FIG. 34, it can be seen that the field-effect transistor according to the fourth embodiment has a higher drain voltage at which breakdown starts to occur than the field-effect transistor according to the comparative example.

[Table 1] shows a comparison between gain and device parameters obtained from the results of the two-dimensional device simulation. The bias condition is the same as when the equipotential lines are shown.

[0113]

[Table 1]

As is clear from Table 1, in the field-effect transistor according to the fourth embodiment, the height of the step portion of the gate electrode 7 is smaller than the thickness of the depletion layer. Higher bidirectional power gain and lower drain conductance than transistors. In the fourth embodiment, since the surface area of the gate electrode on the drain side is small, the capacitance between the gate and the drain is suppressed, and a high bidirectional power gain is obtained.

Therefore, when used in an amplifier or the like in which bidirectional power gain is important among gains, a field effect transistor having a small step portion is more effective as shown in the fourth embodiment. It turns out that there is a further effect.

In the fourth embodiment, the case where the gate electrode 7 is in contact with the step of the conductive layer 12 has been described.
Similar effects can be obtained even when there is a space between the gate electrode 7 and the step of the conductive layer 12.

Further, in the fourth embodiment, an example has been shown in which the gate electrode 7 is formed so as to straddle the step portion of the conductive layer 12 having a uniform impurity concentration. However, in the first embodiment or the second embodiment, The effect is the same even when an undoped layer is provided as in the embodiment.

[0118]

[0119]

[0120]

[0121]

[0122]

[0123]

[0124]

[Effect of the Invention] According to the method of manufacturing the field effect transistor according to the invention of claims 1 to 3, the surface portion of the undoped layer is selectively etched and the drain-side step portion such that a layer thickness than the source side Is formed, a gate electrode is formed in a region straddling the step portion on the undoped layer having a step portion such that the drain side is thicker than the source side in order to form a gate electrode in a region straddling the step portion. Can be done.

[0125] According to the manufacturing method of the field effect transistor according to the invention of claim 4 to 7, after exposing the area of the source side of the conductive layer by selectively etching the undoped layer, exposed in the conductive layer regions The gate electrode can be formed so as to extend over the conductive layer and the undoped layer formed only on the drain side .

According to the method of manufacturing a field-effect transistor according to the invention, the surface portion of the conductive layer is selectively etched to form a step portion such that the drain side is thicker than the source side. After that, in order to form a gate electrode in a region straddling the step portion, a gate electrode is formed in a region straddling the step portion on a conductive layer having a step portion such that the drain side is thicker than the source side. Can
You.

According to the method of manufacturing a field effect transistor according to the first, fifth or eighth aspect of the present invention, the impurity is ion-implanted at a high concentration using the gate electrode and its side wall as a mask, and the drain and source are self-aligned. Since the contact region is formed, the distance between the contact region and the gate electrode is reduced, so that a low source resistance and a low drain resistance can be obtained.

According to the method for manufacturing a field-effect transistor according to the second, sixth or ninth aspect of the present invention, a protrusion made of an insulator is formed on the source side of the gate electrode before the step of forming the gate electrode. Since the source-side contact region is formed in a self-aligned manner using the gate electrode and the projection as a mask, and the drain-side contact region can be regulated by the resist pattern, the degree of freedom in designing the source resistance and the drain withstand voltage increases.

According to the method of manufacturing a field effect transistor according to the third or seventh aspect of the present invention, after the source and drain contact layers are formed on the undoped layer by a crystal growth method, the undoped layer is etched. Therefore, the etching step for the undoped layer can be performed while monitoring the current.

According to the method of manufacturing a field effect transistor according to the tenth aspect of the present invention, after forming the source and drain contact layers on the conductive layer by a crystal growth method,
Since etching is performed on the conductive layer, the etching step on the conductive layer can be performed while monitoring the current.

According to the method of manufacturing a field-effect transistor according to the third, seventh or tenth aspect of the present invention, the gate electrode is formed after the source and drain contact layers are formed. There is no.

[0132]

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a field-effect transistor according to a first embodiment, which is a first type of the present invention.

FIG. 2 is a sectional view of a field-effect transistor according to a second embodiment, which is a second type of the present invention.

FIG. 3 is a sectional view of a field-effect transistor according to a third embodiment, which is a third type of the present invention.

FIG. 4 is a cross-sectional view showing each step of a first method of manufacturing a first type field effect transistor of the present invention.

FIG. 5 is a sectional view showing each step of a first method of manufacturing a first type field effect transistor of the present invention.

FIG. 6 is a cross-sectional view showing each step of a second method of manufacturing the first type field effect transistor of the present invention.

FIG. 7 is a cross-sectional view showing each step of a second method of manufacturing the first type field effect transistor of the present invention.

FIG. 8 is a cross-sectional view showing each step of a third method of manufacturing the first type of field-effect transistor of the present invention.

FIG. 9 is a cross-sectional view showing each step of a third method of manufacturing the first type field-effect transistor of the present invention.

FIG. 10 is a cross-sectional view showing each step of a fourth method for manufacturing a field-effect transistor of the first type according to the present invention.

FIG. 11 is a cross-sectional view showing each step of a fourth method for manufacturing a field-effect transistor of the first type according to the present invention.

FIG. 12 is a cross-sectional view showing each step of a first method for manufacturing a field-effect transistor of the second type according to the present invention.

FIG. 13 is a cross-sectional view showing each step of the first method of manufacturing the second type of field effect transistor of the present invention.

FIG. 14 is a cross-sectional view showing each step of a second method for manufacturing a field-effect transistor of the second type according to the present invention.

FIG. 15 is a cross-sectional view showing each step of a second method for manufacturing a field-effect transistor of the second type according to the present invention.

FIG. 16 is a cross-sectional view showing each step of a third method for manufacturing a field-effect transistor of the second type according to the present invention.

FIG. 17 is a cross-sectional view showing each step of a third method for manufacturing a field-effect transistor of the second type according to the present invention.

FIG. 18 is a cross-sectional view showing each step of a fourth method for manufacturing a field-effect transistor of the second type according to the present invention.

FIG. 19 is a cross-sectional view showing each step of a fourth method for manufacturing a field-effect transistor of the second type according to the present invention.

FIG. 20 is a cross-sectional view showing each step of the first method of manufacturing the third type of field-effect transistor of the present invention.

FIG. 21 is a cross-sectional view showing each step of the first method of manufacturing the third type of field effect transistor of the present invention.

FIG. 22 is a cross-sectional view showing each step of the second method of manufacturing the third type field effect transistor of the present invention.

FIG. 23 is a cross-sectional view showing each step of the second method of manufacturing the third type field effect transistor of the present invention.

FIG. 24 is a cross-sectional view showing each step of a third method for manufacturing a field-effect transistor of the third type according to the present invention.

FIG. 25 is a cross-sectional view showing each step of the third method of manufacturing the third type field-effect transistor of the present invention.

FIG. 26 is a cross-sectional view showing each step of the fourth method of manufacturing the third type field-effect transistor of the present invention.

FIG. 27 is a cross-sectional view showing each step of the fourth method of manufacturing the third type field effect transistor of the present invention.

FIG. 28 is a cross-sectional view showing each step of the fifth method of manufacturing the third type field effect transistor of the present invention.

FIG. 29 is a cross-sectional view showing each step of the fifth method of manufacturing the third type field effect transistor of the present invention.

FIG. 30 is a sectional view of a field-effect transistor according to a fourth embodiment, which is a fourth type of the present invention.

FIG. 31 is a diagram showing an equipotential diagram as a result of a two-dimensional device simulation in the field-effect transistor according to the fourth embodiment.

FIG. 32 is a sectional view of a field-effect transistor according to a comparative example of the fourth embodiment.

FIG. 33 is a diagram showing an equipotential diagram as a result of two-dimensional device simulation in a field-effect transistor according to a comparative example of the fourth embodiment.

FIG. 34 is a characteristic diagram showing a relationship between a drain current and a drain voltage obtained by a two-dimensional device simulation in the field-effect transistor according to the fourth embodiment and a comparative example of the fourth embodiment.

FIG. 35 is a cross-sectional view of a conventional field-effect transistor.

[Explanation of symbols]

Reference Signs List 1 semi-insulating substrate 2, 2A, 2B conductive layer 3, 3A, 3B undoped layer 4 contact layer 4A, 4B contact region 5 drain electrode 6 source electrode 7 gate electrode 8 element isolation region 9 insulating film 9A side wall 10 side wall 11 undoped buffer Layer 12 Conductive layer 13 Contact area 31, 32, 33, 34, 35, 36, 37, 38, 3
6,40 resist pattern

Continuation of the front page (72) Inventor Hiroyuki Masato 1006 Kazuma Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-6-224225 (JP, A) JP-A-59-84579 ( JP, A) JP-A-1-199471 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 29/812

Claims (10)

(57) [Claims] 1. A method according to claim 1, further comprising the steps of:
A step of sequentially forming a conductive layer doped with impurities and an undoped layer not doped with impurities; and selectively etching a surface portion of the undoped layer so that the drain side of the undoped layer is thicker than the source side. A step of forming a step portion so as to form; a step of forming a gate electrode made of a refractory metal in a region over the step portion on the undoped layer; and insulating the side surface of the gate electrode on the undoped layer. Forming a sidewall made of a material; and implanting high-concentration ions into the semi-insulating substrate using the gate electrode and the sidewall as a mask, followed by heat treatment to form a drain and source contact region. And a method for manufacturing a field-effect transistor. 2. A method according to claim 1, wherein a crystal growth method is used on a semi-insulating substrate.
A step of sequentially forming a conductive layer doped with impurities and an undoped layer not doped with impurities; and selectively etching a surface portion of the undoped layer so that the drain side of the undoped layer is thicker than the source side. A step of forming a step portion such that: a step of forming a protrusion made of an insulator at a lower portion of the step portion on the undoped layer at an interval from the step portion; Forming a gate electrode with a high melting point metal in a region above the step and on the undoped layer, and ion-implanting impurities into the semi-insulating substrate at a high concentration using the gate electrode and the protrusion as a mask. Forming a source contact region by performing a heat treatment after the heat treatment. Production method. 3. A method according to claim 1, wherein the semi-insulating substrate is formed on a semi-insulating substrate by a crystal growth method.
Forming a conductive layer doped with impurities, an undoped layer not doped with impurities and a contact layer doped with impurities at a high concentration, and selectively etching the contact layer to form the undoped layer. Partially exposing, the step of selectively etching the surface of the exposed region in the undoped layer to form a recess in the exposed region of the undoped layer, and Forming a gate electrode in a region straddling a step portion on the drain side of the concave portion. 4. A method according to claim 1, wherein a crystal growth method is used on a semi-insulating substrate.
Sequentially forming a conductive layer doped with impurities and an undoped layer not doped with impurities, exposing a source-side region in the conductive layer by selectively etching the undoped layer, Forming a drain and source contact region by performing heat treatment after high-concentration ion implantation of impurities into the semi-insulating substrate; and straddling over the exposed region of the conductive layer and over the undoped layer. Forming a gate electrode. 5. The method according to claim 5, wherein the semi-insulating substrate is formed by a crystal growth method.
Sequentially forming a conductive layer doped with impurities and an undoped layer not doped with impurities, exposing a source-side region in the conductive layer by selectively etching the undoped layer, Forming a gate electrode made of a refractory metal over an exposed region of the conductive layer and over the undoped layer; and forming an insulator on a side surface of the gate electrode over the conductive layer and the undoped layer. Forming a sidewall and forming a drain and source contact region by performing heat treatment on the semi-insulating substrate after ion-implanting impurities at a high concentration using the gate electrode and the sidewall as a mask. A method for manufacturing a field-effect transistor, comprising: 6. A method according to claim 6, wherein a crystal growth method is used on a semi-insulating substrate.
A step of sequentially forming a conductive layer doped with impurities and an undoped layer not doped with impurities, and a step of exposing a source-side region in the conductive layer by selectively etching the undoped layer; Forming a protrusion made of an insulator at an interval from the undoped layer in an exposed region on the conductive layer; and forming a protrusion on the exposed portion of the conductive layer and on the undoped layer on the protrusion. Forming a gate electrode with a high melting point metal over the semiconductor substrate; and ion-implanting impurities at a high concentration into the semi-insulating substrate using the gate electrode and the projection as a mask, and then performing a heat treatment, thereby performing Forming a contact region. 7. On a semi-insulating substrate, a crystal growth method is used.
Forming a conductive layer doped with impurities, an undoped layer not doped with impurities, and a contact layer doped with impurities at a high concentration; and selectively etching the contact layer to form the undoped layer. Partially exposing, and selectively exposing the exposed region in the undoped layer to expose a source-side region in the conductive layer; and exposing the exposed region in the conductive layer and the undoped region. Forming a gate electrode over the layer. 8. On a semi-insulating substrate, a crystal growth method is used.
A step of forming a conductive layer doped with impurities; and a step of selectively etching a surface portion of the conductive layer to form a step in the conductive layer such that the drain side is thicker than the source side. Forming a gate electrode made of a refractory metal in a region over the step on the conductive layer; and forming a side wall made of an insulator on a side surface of the gate electrode on the conductive layer. Forming a drain and a source contact region by performing heat treatment after high-concentration ion implantation of impurities into the semi-insulating substrate using the gate electrode and the side wall as a mask. Manufacturing method of a field-effect transistor. 9. On a semi-insulating substrate, a crystal growth method is used.
A step of forming a conductive layer doped with impurities; and a step of selectively etching a surface portion of the conductive layer to form a step in the conductive layer such that the drain side is thicker than the source side. Forming a protrusion made of an insulator at an interval from the step on the conductive layer below the step, and a region over the step on the conductive layer, Forming a gate electrode made of a refractory metal on the protrusion, and ion-implanting impurities into the semi-insulating substrate at a high concentration using the gate electrode and the protrusion as a mask, and then performing a heat treatment. Forming a source contact region. 10. A step of sequentially forming a conductive layer doped with an impurity and a contact layer doped with a high concentration of impurities on a semi-insulating substrate by a crystal growth method, and selectively etching the contact layer. Performing the step of partially exposing the conductive layer, and selectively etching the surface of the exposed region of the conductive layer to form a recess in the exposed region of the conductive layer; Forming a gate electrode in a region over the conductive layer over a step on the drain side of the recess.