JPH07130971A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To restrain a drop in an operating speed due to the addition of a transistor for logic verification in a gate array in which the transistor for logic verification is connected to every fundamental cell. CONSTITUTION:A cross-check transistor is a top gate-type TFT which is composed of a polycrystal silicon film which is composed of N<+> source-drain regions 9aa, 9ab and of a P-type channel region, of a gate oxide film and of a gate electrode 10a into which a part of a cross-check input interconnection 10b is converted. The N<+> type source-drain region 9aa is connected, via a direct contact hole 8, to an N<+> type diffused layer 6a as the output end of a gate array, and the N<+> type source-drain region 9ab is connected to a cross-check output interconnection 13f via a contact hole 12a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a CMOS gate array having a logic verification function.

[0002]

2. Description of the Related Art In recent years, LSIs for systems in various fields have been developed, and so-called gate arrays capable of small-volume production with short delivery time and low development cost have been remarkably growing. The gate array is formed by connecting a plurality of basic gates, and each basic gate is formed by connecting at least one basic sail by a power supply wiring, a ground wiring, an input wiring, and an output wiring.

Referring to FIG. 3 which is a plan view of a semiconductor integrated circuit device, one example of a basic cell of a CMOS gate array is a rectangular first element formation region 3aa and a rectangular first element formation region 3aa provided on the surface of a semiconductor substrate (not shown). A rectangular second element forming region 3b, a first gate electrode 5a provided on the first element forming region 3aa and a second element forming region 3b via a gate insulating film (not shown), 5b, three N ⁺ type diffusion layers 16 and three P ⁺ type diffusion layers 17 provided on the surface of the element forming region 3aa and the surface of the element forming region 3b.
It consists of and. The element forming regions 3aa and 3b are alternately arranged in parallel with the X direction on the surface of the semiconductor substrate and in parallel with the Y direction orthogonal to the X direction. The gate electrodes 5a and 5b
Cross over each of the pair of element forming regions 3aa and 3b in parallel with the Y direction via the gate insulating film. The N ⁺ type diffusion layer 16 and the P ⁺ type diffusion layer 17 are provided on the surface of the element forming region 3aa and the surface of the element forming region 3b which are divided by the gate electrodes 5a and 5b, respectively.

In the field of gate arrays, the degree of integration is increasing year by year, and a gate array of 600K gates or more in which 600 × 10 ³ or more basic cells as shown in FIG. 3 are connected by wiring is commercialized. . In such a large-scale gate array, logic verification and failure analysis when a failure occurs are very difficult. In order to solve such a problem, one MOS transistor (hereinafter referred to as a cross check transistor) is connected to each basic cell, and the logic verification is performed by detecting the output potential of each basic gate. I am doing it.

Referring to FIG. 4 which is a plan view of a semiconductor integrated circuit device, a basic gate having a logic verification function composed of a two-input NOR formed of basic cells obtained by slightly modifying one basic cell shown in FIG. Is as follows.

A P-type silicon substrate (not shown) has P on the surface.
A well (not shown) and an N well (not shown) are provided, and a plurality of first element formation regions 3ab and a plurality of rectangular second regions are formed on the P well surface and the N well surface, respectively.
The element forming region 3b is provided. Element formation area 3
The array of abs and 3b is substantially the same as the array of the element formation regions 3aa and 3b (shown in FIG. 3). Element forming region 3a
A field oxide film (not shown) is provided on the surface of the P-type silicon substrate on which b and 3b are not formed. Gate electrodes 5a and 5b respectively cross the pair of element forming regions 3ab and 3b in parallel with the Y direction via a gate insulating film (not shown). Further, the gate electrode 5ca of the cross check transistor is separated from the element isolation region 3ab through the gate insulating film.
It is provided above. A part of the cross check input wiring 5cb made of the same wiring layer as the gate electrodes 5a and 5b is diverted to the gate electrode 5ca, and the cross check input wiring 5cb is formed in the Y direction in the void portion in the X direction between the element formation regions 3b. It is installed in parallel with. Gate electrode 5
In the element formation region 3b divided by a and 5b, P ⁺
Type diffusion layer 17a (drain region) and P ⁺ type diffusion layer 17b
The (source region) and the P ⁺ type diffusion layer 17c are provided. Further, in the element forming region 3b divided by the gate electrodes 5a, 5b, 5ca, the N ⁺ type diffusion layer 16a (drain region), the N ⁺ type diffusion layer 16b (source region) and the N ⁺ type diffusion layer 16b are formed.
A mold diffusion layer 16c is provided.

Input wirings 23a and 23b are connected to gate electrodes 5a and 5b through contact holes 22 provided in an interlayer insulating film (not shown), and power supply wiring 23c.
Is connected to the P ⁺ type diffusion layer 17b, and the ground wiring 23d is N
^The output wiring 23e is connected to the ⁺ type diffusion layer 16b, and is connected to the N ⁺ type diffusion layer 16a and the P ⁺ type diffusion layer 17a. The cross check output wiring 23f is connected to the N ⁺ type diffusion layer 16c via a contact hole 22a provided in the interlayer insulating film. The cross check output wiring 23f is arranged parallel to the X direction.

Thus, in one basic cell, the N ⁺ type diffusion layer 16c, the gate electrode 5ca and the N ⁺ type diffusion layer 1 are included.
One N-channel MOS transistor 6a is provided as a cross-check transistor. In the case of FIG. 4, only one cross check transistor is provided in one basic gate, and the N ⁺ type diffusion layer 16a constituting this transistor is connected to the output wiring 23e. The output potential of this basic gate is detected as follows. The cross check input wiring belonging to the basic gates of the other columns and the cross check output wiring belonging to the basic gates of the other rows are respectively applied to the ground potential, and the cross check connected to the gate electrode 5ca of this cross check transistor. A positive potential is applied to the input wiring 5cb to turn on this transistor, and the potential of the N ⁺ type diffusion layer 16c at this time is detected by the cross check output wiring 23f. By repeating such an operation (in a matrix manner), the output potentials of all the basic gates can be detected, and even if the gate array becomes large in scale, it is possible to perform logic verification in detail. It will be possible.

For example, in a 3-input NAND gate composed of two basic cells, one basic gate has two
Two cross-check transistors are provided.
This one of the two cross-check transistor has connected N ⁺ -type diffusion layer to the output line, connected to the output wiring in the N ⁺ diffusion layer of the other one cross check transistor It has not been. In this case, since the detection method as described above is adopted, when detecting the cross-check transistor connected to the output wiring, the cross-check transistor not connected to the output wiring is turned off. Therefore, there is no problem in verifying the output potential.

[0010]

In the gate array, since CAD is used for automatic design, positions (lattices) where contact holes can be arranged in the diffusion layer are defined. Therefore, if a cross-check transistor is arranged in each basic cell, it is necessary to increase the number of lattices by one. Therefore, for example, a part of the element formation region in which the N-channel MOS transistor is formed protrudes from the rectangle. As a result, the area of the N ⁺ diffusion layer increases. Therefore, the parasitic capacitance added to the output of each basic gate increases. As a result, there arises a problem that the operation speed is lowered, which is an important performance required for the gate array.

[0011]

In a semiconductor integrated circuit device of the present invention, first elements are arranged parallel to the X direction on the surface of a semiconductor substrate and alternately arranged parallel to the Y direction orthogonal to the X direction. The first element formation region and the second element formation region forming a pair with the formation region and the second element formation region are traversed in parallel with each other in the Y direction via the first gate insulating film. At least one first gate electrode is provided for each pair, and N provided in each of the first element formation region and the second element formation region divided by the first gate electrode. First source / drain regions, each having a plurality of basic cells composed of a ⁺ type diffusion layer and a P ⁺ type diffusion layer, and directly connected to one of the N ⁺ type diffusion layers of each of the basic cells. X Second source-drain region connected to cross-check the output wiring provided in parallel with the direction, and the this first source-drain region second
And a polycrystalline silicon film provided with a channel region connecting to the source / drain region of the basic cell and the surface of the channel region via the second gate insulating film, and in the void portion in the X direction of the basic cell, respectively. A cross-check thin film transistor comprising a second gate electrode connected to a cross-check input wiring provided parallel to the Y direction,
At least one of the above basic cells has power wiring, input wiring,
A basic structure connected by an output wiring connected to one of the N ⁺ type diffusion layers connected to the thin film transistor and a ground wiring connected to at least one of the N ⁺ type diffusion layers not connected to the thin film transistor. It has a gate.

Preferably, the thin film transistor is a top gate type thin film transistor, and the first gate electrode is made of a polycrystalline silicon film in the same layer as the polycrystalline silicon film forming the thin film transistor. Alternatively, the thin film transistor is a bottom gate type thin film transistor, and the first gate electrode is formed of a conductor film in the same layer as the cross check input wiring.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 which is a plan view of the semiconductor integrated circuit device and FIG. 2 which is a sectional view taken along line XX of FIG.
In one embodiment of the present invention, a basic gate composed of a two-input NOR gate is composed of one basic cell, and this two-input NOR gate has a top gate type N-channel thin film transistor (TFT) as a cross-check transistor. is doing.

First, the basic cell of this embodiment will be described.

X is formed on the surface of the P-type silicon substrate 1.
A plurality of strip-shaped P wells 2 and a plurality of strip-shaped N wells (not shown) are provided parallel to the direction. A plurality of rectangular first element forming regions 3a and a plurality of rectangular second element forming regions 3b are provided on the surface of the P well 2 and the surface of the N well, respectively, in parallel to the X direction. Further, the element forming regions 3a and the element forming regions 3b are arranged alternately in parallel to the Y direction orthogonal to the X direction. Element forming region 3a and element forming region 3
A field oxide film 3 is provided on the surface of the P-type silicon substrate 1 not provided with b. The surface of the P well 2 and the surface of the N well are covered with a gate oxide film 4 which is a first gate insulating film. Is the first gate electrode,
Gate electrodes 5a, 5 made of N ⁺ type polycrystalline silicon film
b crosses over the pair of element forming regions 3a and 3b through the gate oxide film 4, respectively. Divided by these gate electrodes 5a and 5b, N ⁺ type diffusion layers 6a and 6b and P ⁺ type diffusion layer 7 are formed on the surface of element formation region 3a and the surface of element formation region 3b, respectively.
a, 7b, 7c are provided.

Next, the TFT which serves as the cross-check transistor of this embodiment will be described.

One TF is provided for each basic cell.
T is connected. This TFT has a gate electrode 5a,
5b, a polycrystalline silicon film 9 in the same layer, a gate oxide film 4A which is a second gate insulating film, and a gate electrode 10a which is a second gate electrode. The polycrystalline silicon film 9, first a source-drain region N ⁺ -type source and drain regions 9aa, second source-drain region and a N ⁺ -type source and drain regions 9ab, and N ⁺ -type source It is composed of a P-type channel region 9b connecting the drain region 9aa and the N ⁺ -type source / drain region 9ab. The N ⁺ type source / drain region 9aa is directly connected to the N ⁺ type diffusion layer 6a through the direct contact hole 8 formed in the gate oxide film 4. The N ⁺ type source / drain region 9ab is formed by the interlayer insulating film 1.
It is connected to one of the cross check output wirings 13f through the contact hole 12a provided in No. 1. The cross check output wiring 13f is provided in parallel with the X direction. The gate oxide film 4A is formed on the channel region 9c.
Covers the surface (top and side). The gate electrode 10a has the channel region 9 via the gate oxide film 4A.
c is covered. The gate electrode 10a is provided by diverting a part of one cross check input wiring 10b. The cross check input wiring 10b is provided in parallel with the Y direction in the void portion of the basic cell in the X direction. The cross check input wiring 10b is the second
The layer is made of an N ⁺ type polycrystalline silicon film.

Next, the basic gate of this embodiment obtained by wiring the above basic cell will be described.

The input wirings 13a and 13b are connected to the gate electrodes 5a and 5b, respectively, and the power supply wiring 13c is connected to the P ⁺ type diffusion layer 7b through the contact hole 12 provided in the interlayer insulating film 11, and the ground wiring. 13d is connected to the N ⁺ type diffusion layer 6b, the output wiring 13e is connected to the N ⁺ type diffusion layer 6a and the P ⁺ type diffusion layer 7a, and the two-input NOR gate according to the present embodiment is obtained. In this case, the N ⁺ type diffusion layer 6
The a and N ⁺ type diffusion layers 6b serve as the drain region and the source region of the N channel MOS transistor constituting this basic cell, respectively, and the P ⁺ type diffusion layer 7a and P ⁺ type diffusion layer 7b respectively form the P region constituting this basic cell. It becomes the drain region and the source region of the channel MOS transistor. The input wirings 13a and 13b, the power supply wiring 13
The c, the ground wiring 13d, the output wiring 13e and the cross check output wiring 13f are made of the same metal film.

The detection of the output potential of the basic gate in the above embodiment is performed as follows.

The cross-check input wiring 10b belonging to the basic gates in the other columns and the cross-check output wiring 13f belonging to the basic gates in the other rows are respectively applied to the ground potential, and the desired (connecting to the output end of the basic gate is connected. Yes) T
A positive potential is applied to the cross check input wiring 10b connected to the gate electrode 10a of the FT to turn on the TFT, and the potential of the N ⁺ type diffusion layer 6a at this time is detected by the cross check output wiring 13f. By repeating such an operation (in a matrix manner), the output potentials of all the basic gates can be detected, and even if the gate array becomes large in scale, it is possible to perform logic verification in detail. It will be possible.

In the above-described embodiment, as described above, since the cross-check transistor is composed of the TFT,
It is not necessary to locally project the first element formation region to provide the cross check transistor as shown in FIG. That is, in this embodiment, even if the cross check transistor is provided, the N channel M (which becomes the output end) is
It is not necessary to increase the area of the drain region of the OS transistor, and it is possible to avoid the decrease in operating speed, which is an important performance required for the gate array.

Next, the basic gate and TFT of the above embodiment
The main points of the manufacturing method up to the formation of are explained.

First, after the P well 2 and the N well are formed on the surface of the P type silicon substrate 1, the field oxide film 3 is formed. By forming the field oxide film 3, the element isolation regions 3a and 3b are also formed. Element isolation region 3
A gate oxide film 4 is formed on the surfaces of a and 3b by thermal oxidation. A direct contact hole 8 is formed by etching a predetermined portion of the gate oxide film. A low-concentration P-type polycrystalline silicon film is formed on the entire surface, and the polycrystalline silicon film other than the internal region is N ⁺ by ion implantation using the photoresist film that encloses the area where the TFT channel region is to be formed as a mask. Become a mold. This polycrystalline silicon film is patterned to form the gate electrodes 5a, 5b and the polycrystalline silicon film 9.

Subsequently, the gate oxide film 4A is formed by thermal oxidation. At this stage, the gate oxide film 4A is formed on the exposed surface of the gate oxide film 4, the exposed gate electrode 5a,
5b and the surface of the polycrystalline silicon film 9. Next, a second-layer N ⁺ -type polycrystalline silicon film is formed on the entire surface, and this polycrystalline silicon film is patterned by anisotropic etching to form the gate electrode 10a and the cross check input wiring 10b.

After that, ion implantation of N-type impurities and P-type impurities is selectively performed, and the element isolation regions 3a are formed.
N ⁺ type diffusion layers 6a, 6b and P ⁺ type diffusion layers 7a, 7b, 7c are formed on the surface and the surface of the element isolation region 3b, respectively. In these ion implantations, the gate electrodes 5a,
Since 5b and the cross check input wiring 10b also function as a mask, this N-type impurity ion implantation allows
In the polycrystalline silicon film 9, the N ⁺ type source / drain region 9 is formed.
aa and 9ab are formed, and a P-type channel region 9b is defined.

The gate electrode 10a (and the cross check input wiring 10b) which is the second gate electrode is N ⁺
It is not necessary to limit the type to a polycrystalline silicon film, and a silicide film or a polycide film may be used. Further, the second gate insulating film does not have to be the gate oxide film 4A, and may be formed of, for example, a silicon nitride film by the CVD method.

Identification of the position where the direct contact hole 8 is provided in the above embodiment will be described.

Direct contact hole 8 in this embodiment
Is provided in a portion including the boundary line of the element isolation region 3a on the right side of the gate electrode 5b, as shown in FIG.
Direct (cross check input wiring 10b)
The contact hole 8 may be provided in a portion including the boundary line of the element isolation region 3a on the left side of the gate electrode 5a. That is, the direct contact hole is preferably provided in a portion including the boundary line of the first element isolation region parallel to the first gate electrode.

If the basic gate is only NOR type, the element isolation region 3 between the gate electrode 5a and the gate electrode 5b is formed.
Although it may be provided at a portion including the boundary line of a, if the direct contact hole 8 is provided at such a position, it becomes extremely difficult to detect the output potential of the basic NAND gate.

Unless a gate array composed of BiCMOS is assumed, the N ⁺ type diffusion layer 6a (which is the drain region of the N channel MOS transistor) and the (P channel MO) are formed.
The drain region of the S transistor) P ⁺ type diffusion layer 7
Since a is directly connected to a and serves as the output end of the basic gate, the direct contact hole 8 has a portion including the boundary line of the element isolation region 3b on the left side of the gate electrode 5a,
Alternatively, it may be provided in a portion including the boundary line of the element isolation region 3b on the right side of the gate electrode 5b. BiCOS
Assuming a gate array consisting of, the N ⁺ type diffusion layer 6a connected to the P ⁺ type diffusion layer 7a via the bipolar transistor serves as an output end, so that the portion including the boundary line of the element isolation region 3b is directly contacted. Providing the holes 8 is not preferable.

Although the TFT in the above embodiment is of a top gate type, it is not limited to this.
The cross-check transistor in the present invention may be a bottom gate type TFT. Even in such a case, the same effect as that of the above-described embodiment can be obtained.

An outline up to the formation of such a bottom gate type TFT will be described.

First, a P well and an N well are formed on the surface of a semiconductor substrate, a field oxide film, a first element forming region and a second element forming region are formed, and then a surface covering these element forming regions is formed. 1 gate insulating film is formed. Next, a first conductor film is formed on the entire surface. The first conductor film is an N ⁺ type polycrystalline silicon film, a silicide film or a polycide film. Next, the first conductor film is patterned to form the first gate electrode and the cross check input wiring.

Then, a second gate insulating film is formed to cover at least the surfaces (top surface and side surfaces) of the first gate electrode and the cross check input wiring. When the first conductor film is an N ⁺ -type polycrystalline silicon film, a thermal oxide film can be used as the second gate insulating film, but the first conductor film is a silicide film or a polycide film. In some cases, the second gate insulating film is an insulating film formed by the CVD method or the like.
Subsequently, the portion of the first insulating film (and the second insulating film) including the boundary line of the first element isolation region parallel to the first gate electrode is removed to form a direct contact hole. . Next, a low concentration P-type polycrystalline silicon film is formed and patterned on the entire surface, and the polycrystalline silicon film is left only in the regions where the source / drain regions and the channel regions of the TFT are formed.

After that, a P ⁺ type diffusion layer is formed by ion implantation using a photoresist film having an opening in the second element formation region as a mask. Furthermore, by ion implantation using a photoresist film as a mask, which covers the second element formation region and the region where the TFT channel region is formed,
An N ⁺ type diffusion layer and a bottom gate type TFT are formed.

[0038]

As described above, in the semiconductor integrated circuit device of the present invention, since the cross-check transistor for logic verification is composed of TFT, it is not necessary to increase the area of the diffusion layer of the basic cell, Since the increase of the parasitic capacitance of the diffusion layer is suppressed, the reduction of the operating speed can be prevented.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the above-described embodiment, which is a cross-sectional view taken along line XX of FIG.

FIG. 3 is a plan view of a basic cell of a general COM gate array.

FIG. 4 is a plan view of a 2-input NOR gate having a conventional logic verification function.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P type silicon substrate 2 P well 3 Field oxide film 3a, 3aa, 3ab, 3b Element formation region 4, 4A Gate oxide film 5a, 5b, 5ca, 10a Gate electrode 5cb, 10b Cross check input wiring 6a, 6b, 16, 16a, 16b, 16c N ⁺ type diffusion layers 7a, 7b, 7c, 17, 17a, 17b, 17c
P ⁺ diffusion layer 8 Direct contact hole 9 Polycrystalline silicon film 9aa, 9ab N ⁺ type source / drain region 9b Channel region 11 Interlayer insulating film 12, 12a, 22, 22a Contact hole 13a, 13b, 23a, 23b Input wiring 13c , 23c Power supply wiring 13d, 23d Ground wiring 13e, 23e Output wiring 13f, 23f Cross check output wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/786 9056-4M H01L 29/78 311 C

Claims (4)

[Claims] 1. A pair of first element formation regions and second element formation regions, which are arranged parallel to the X direction on the surface of the semiconductor substrate and are alternately arranged parallel to the Y direction orthogonal to the X direction, are formed. The first element formation region and the second element formation region formed are crossed in parallel with each other in the Y direction through the first gate insulating film, and at least one pair is provided for each pair. Of the gate electrode, and N provided in each of the first element formation region and the second element formation region divided by the first gate electrode.
First source / drain regions each having a plurality of basic cells composed of a ⁺ type diffusion layer and a P ⁺ type diffusion layer, and being directly connected to one of the N ⁺ type diffusion layers of the respective basic cells, respectively. A second source / drain region connected to the cross check output wiring provided in parallel with the X direction, and a channel region connecting the first source / drain region and the second source / drain region. The polycrystalline silicon film provided is opposed to the surface of the channel region through the second gate insulating film, and Y is provided in each of the voids in the X direction of the basic cell.
A thin-film transistor for cross-check consisting of a second gate electrode connected to a cross-check input wiring provided in parallel to the direction, and at least one of the basic cells includes a power supply wiring, an input wiring,
A basic structure connected by an output wiring connected to one of the N ⁺ type diffusion layers connected to the thin film transistor and a ground wiring connected to at least one of the N ⁺ type diffusion layers not connected to the thin film transistor A semiconductor integrated circuit device having a gate. 2. The thin film transistor is a top-gate thin film transistor, and the first gate electrode is made of a polycrystalline silicon film in the same layer as the polycrystalline silicon film forming the thin film transistor. 1. The semiconductor integrated circuit device according to 1. 3. The second gate electrode is a silicide film,
Alternatively, the semiconductor integrated circuit device according to claim 2, comprising a polycide film. 4. The semiconductor integrated circuit according to claim 1, wherein the thin film transistor is a bottom gate type thin film transistor, and the first gate electrode is made of a conductor film in the same layer as the cross check input wiring. apparatus.