JPH07129636A - Logical simulation method - Google Patents

Abstract

PURPOSE:To efficiently detect an event to be invalid and to accurately perform logical simulation. CONSTITUTION:The propagation time 104 of signals, the identifier 105 of element information propagated by the signals and a propagated signal value 106 are provided as event information and the identification number 112 of an element kind, an element intrinsic title 113, an input terminal number 114, the list 131 of connection destination painters for the respective input terminals, the connection destination number 116 of output terminals, the list 133 of the connection destination pointers and an element output value 119 are provided as the element information. Further, the identifier 10'7 of the event is provided as the event information and the identifier 118 of a delay model, a succeeding output value 120, a propagation identifier, 121 and the list 135 of delay values corresponding to output signal change are provided as the element information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method for simulating the operation of a logic circuit on a computer, and more particularly to a method for performing a simulation for simultaneously processing a plurality of delay model elements.

[0002]

2. Description of the Related Art The event method is known as a logic simulation method for simulating a logic circuit with a computer. In the event method, the change in the signal value of a logic element is called an event,
Processing is performed by evaluating this event in order of the time at which the signal value change propagates. When all the basic elements are elements with one output, in the conventional event method, as the event information, as shown in FIG. 2A, the time at which the signal propagates, the identifier of the element information at which the signal propagates, and the propagation Has a signal value to As shown in FIG. 2B, the information of the logic element is also the identification number of the element type, the element unique name, the number of input terminals, a list of connection destination pointers for each input terminal, the number of connection destinations of the output terminals and the connection destinations. It has a list of pointers, element-specific delay values, and element output values.

Further, as shown in FIG. 3, the time at which the signal propagates to the output terminal of the element is the time XT + D obtained by adding the delay time D peculiar to each element to the time XT at which the signal change propagates to the input terminal.
Given in.

In an actual logic circuit, the output signal value changes from "0" to "1" at the time of rising and "1" to "0" depending on the method of forming the logic circuit and the characteristics of circuit elements such as transistors. The delay time at the fall is different.
Therefore, a logic simulation model that handles delays of rising and falling of signals is known. Also,
A model in which when a short pulse is applied to an input terminal and the output signal is not changed at all when the next input change is applied before the first input change is transmitted to the output is also known as an inertial delay model. Further, in a signal propagating through a long signal line, the signal propagates regardless of a change in input unless the pulse width becomes 0. Such a model is known as a propagation delay model. In the inertial delay model and the propagation delay model, an event generated by a signal change on the input side may become invalid during propagation.

FIG. 4 is an explanatory diagram of an example of an invalid event in the inertial delay model (b) and the propagation delay model (c) for the logic element 401 having a falling delay value of 4 and a rising delay value of 2. is there. In the inertial delay model (b), the next input signal change 413 occurs before the event 412 generated by the first input signal change 411 propagates. Therefore, the event 412 and the event 41 caused by the input change 413 are generated.
4 is invalid. On the other hand, in the propagation delay model (c), if the event 424 generated by the next input signal change 423 propagates before the event 422 generated by the first input signal change 421 propagates, the event 422 and the event 4
23 is invalid.

A method of detecting such an invalid event and performing a correct simulation is described in Japanese Patent Application No. 4-2752 and Japanese Patent Application Laid-Open No. 5-143669.

[0007]

The conventional method does not deal with the case where the elements of the inertial delay model and the elements of the propagation delay model coexist. Therefore, it is necessary to implement different processes in the program depending on the model of the device.

An object of the present invention is to provide a logic simulation method which can cope with the case where elements of inertial delay model and elements of propagation delay model are mixed.

[0009]

In order to solve the above problems, an event identifier for storing an identification number of an event is added to conventional event information, and the element information indicates which delay model the element is evaluated by. A delay model identifier for identification, a next output value holding a value at which the output signal changes next, and a propagation identifier for storing the identification number of the event are added. The delay value of each element information holds the rising and falling values.

When the delay model identifier is the "inertial delay model", the propagation identifier of the element information is used as a flag indicating the presence or absence of a valid registration event, and when the event is invalid, the value is identified as the event. Change it to a value outside the range of numbers, and if valid, use that value as the event identification number of the valid event. When the delay model identifier is the “propagation delay model”, the value of the event identifier of the latest event propagated to the element is stored in the element information propagation identifier. At the time of executing the logic simulation, the validity or invalidity of the event is determined by the values of the event identifier of each event, the delay model identifier of the element through which the event propagates, and the propagation identifier.

[0011]

[Operation] Whether the event is valid or invalid is determined by the following conditions.
In the case of the inertial delay model, when it is found that the output value changes due to the change when the input changes, if there is an already registered event, that event and the event generated by the input change become invalid events. . In the case of the propagation delay model, both the overtaken event and the overtaken event become invalid when the relationship between the event generation order and the propagation order is reversed.

By this means, when the registered event is invalid in the element of the inertial delay model, the value of the event identifier of the event information and the value of the propagation identifier of the element information are different, so that the process of propagating the event is performed. It is possible to judge whether the event is valid or invalid at the stage. In addition, when the registered event is invalid in the element of the propagation delay model, the order relationship between the value of the event identifier of the event information and the value of the propagation identifier of the element information is reversed. Similarly, the validity / invalidity of an event can be determined at the stage of processing for propagating the event.

[0013]

Embodiments of the present invention will be described below with reference to FIGS. 1 and 5 to 46. First, an embodiment of a simulation method of a logic circuit including a plurality of delay model elements will be described with reference to FIGS. 1 and 5 to 7. Next, the operation of the logic simulation according to the present embodiment will be described with reference to FIGS.

In this embodiment, three values of 0, 1 and an indefinite value X are handled as logical values, and a logic simulation model assuming a delay time is adopted for each element. Further, in the present embodiment, a portion which is not directly related to the present invention, for example, a process of analyzing a structure of a logic circuit necessary for the logic simulation and creating a data structure necessary for the simulation and a result of the simulation in a format that can be understood by the user. The description of the output process is omitted, and only the execution part of the logic simulation will be described.

Further, in the description of this embodiment, 0 is assigned to the first element of data having a plurality of elements, the 0th element to the next element, and the 1st element to the next element. The first.

FIG. 1 is an explanatory diagram of a data structure for realizing a logic simulation according to this embodiment. FIG. 1A is a data structure for storing event information. Reference numeral 101 is a data structure called a time wheel that has been conventionally used in logic simulation by the event method.
The time wheel classifies events according to the signal propagation time and holds them. Each event information 102 is connected by a link pointer 103 and can be sequentially read. The event information is composed of four pieces of information 104 to 107. The information of one event is the information that “the output terminal of a certain element changes to a certain value at a certain time”. The propagation time 104 is the time at which the event propagates, the propagation element identifier 105 is the identifier of the element through which the event is propagated, the propagation signal value 106 is the signal value of the element output propagated by the event, and the event identifier 107 is a continuous value in the order of event occurrence. Is a number that identifies the event.

Reference numeral 111 in FIG. 1B is a data structure for storing information on the logic element. Here, a basic element is a logic element having a plurality of input terminals and one output terminal. At the time of logic simulation, 111 data structures corresponding to the number of logic elements are prepared. In FIG. 1B, an element type identification number 112 is an element type identifier, an element unique name 113 is an element unique name represented by the element 111, and the number of input terminals 114.
Is the number of input terminals of the element, 115 is a pointer to the storage area of the input terminal information list, 116 is the number of elements connected to the output terminal, 117 is a pointer to the storage area of the output connection information list. is there. The delay model identifier 118 is an identifier indicating the type of delay model handled by the element 111, the output value 119 is the current output value of the element 111, and the next output value 120 is the future output value of the element 111. In the case of the inertial delay model, the propagation identifier 121 stores the event identification number of the event relating to the element currently registered, and in the case of the propagation delay model, the event identification number of the latest event propagated by the element is stored. Reference numeral 122 is a pointer that points to the storage area of the delay value information list.

The storage area 131 for the input terminal information list is
It is composed of input connection destination pointers and has 132 elements.
Is equal to the number of input terminals 114. The input connection destination pointer is a pointer that points to the beginning of element information that is connected to the tip of the input terminal of the element 111. Storage area 1 for output connection destination information list
33 is constituted by a pointer pointing to the head of the area for storing the element information of the output connection destination, and the number of elements 134 is equal to the number 116 of output connection destinations. Output connection pointer is element 1
11 is a pointer that points to the head of element information connected to the end of the output terminal 11. The storage area 135 of the delay value information list stores the delay value at each rising and falling of the element 111. The number of elements 136 is equal to the number of all kinds of signal changes that the output of the element 111 can take.

FIG. 5 is an explanatory diagram of a logic simulation process for implementing the present invention. The process of FIG. 5 is started after the elements of the logic circuit to be simulated and the connection information are created in advance in the format 111 of FIG. In the initial state, no event information is stored in the time wheel that stores the event information of FIG. First, 50
Simulation time XT and event identification number E in 1
Initialize the ID. The loop of 502 is processing 503 to 50
6 is repeated until the simulation time XT reaches the end time. The test vector addition process 503 is a process of adding a test vector given during simulation as an event. In this process, the test vector propagating at time XT is added to the time wheel as an event. The event propagation process 504 is a process of propagating an event to each element according to the event information at time XT held in the time wheel.

The element output value evaluation processing 505 determines a new input signal value for the element connected to the output terminal of the element in which the event has propagated, that is, the value of the output signal has changed, that is, the element whose input signal has changed. If a new output signal value is different from the previous output signal value and the change is not invalid, the change is added to the time wheel as an event. Reference numeral 506 is a process for updating the simulation time XT to the next time.

FIG. 6 shows the event propagation process 5 in FIG.
It is a detailed explanatory view of 04. FIG. 6A is an explanatory diagram of the data structure of the output destination connection element information 600 created by the event propagation processing. In the event propagation processing, the event stored in the time wheel is propagated to the element, and
A pointer pointing to the element connected to the output terminal of the element to which the event has propagated is listed in the table shown in FIG. That is, the output destination connection element information 600 is the reference pointer Q6.
01 and an output destination connection element table 602. The table 602 is composed of an output destination connection pointer 603 which is a pointer pointing to the head of the element information.

FIG. 6B is an explanatory diagram of the procedure of event propagation processing. First, at 611, the reference pointer Q is set to the table 6
Set to point to the beginning of 02. Loop 612 repeats for all events propagating at the current simulation time XT stored in the time wheel.
At 613, the event E is taken out from the time wheel. 6
14 branches to 615 to 617 when the value of the delay model identifier 118 of the element X is the inertial delay model, and to 618 to 620 when the value of the delay model identifier 118 of the element X is the propagation delay model. This is a conditional branch.
In 615, the event identifier 107 of the event E and the element X
Of the propagation identifiers 121 of the
If they are not equal, 617 is performed. At 616, the value of the flag is turned on, and the value of the propagation identifier of the element X is set to 0. At 617, the value of the flag is turned off.

At 618, the event identifier of the event E and the propagation identifier of the element X are compared, and if the value of the event identifier is equal to or larger than the value of the propagation identifier, 619.
Otherwise 620 is performed. At 619, the value of the flag is turned on, and the value of the propagation identifier of the element X is set as the value of the event identifier of the event E. At 620, the value of the flag is turned off. In 621, the value of the flag is checked, and 622 and subsequent steps are performed only when the flag is on. Element X at 622
Output value 119 and the propagation signal value 106 of event E are compared, and if the values are not equal, 623 and thereafter are performed. At 623, the output value of the element X is set as the propagation signal value of the event E. 6
In 24 to 625, the content of the output connection destination pointer 133 of the element X is added to the output destination connection element table 602. 62
The loop of 4 turns the number of times equal to the number of output destinations 116 of the element X.

FIG. 7 shows the element evaluation processing 505 in FIG.
FIG. In the processing procedure shown in the figure, first at 701, a pointer R pointing to the table 602 storing the output destination connection information of FIG. 6A is initialized to point to the head of the table 602. In the loop 702, the pointer R is the table 60
The processing of 703 to 713 is repeated by the range of the two elements, that is, the number registered in the event propagation processing 504. In 703, for the element Y pointed to by the output connection destination pointer 603 of the element pointed to by R, the element connected to the input terminal of the element Y,
That is, from the output value of the element pointed by the input connection destination pointer 131, the element type identification number 112 of the element Y, and the next output value 120 of the element Y, a new output value PV of each output terminal of the element Y is obtained.
Ask for. At 704, the output value of the element Y becomes P from the next output value.
The delay value D when changing to V is obtained by referring to the delay value information list of the element Y. In 705, if the new output value PV obtained in 703 and the output value of the element Y are not equal, 706
Perform the following processing.

Reference numeral 706 is a conditional branch that branches to 707 to 710 when the value of the delay model identifier of the element Y is the inertial delay model and to 711 to 712 when it is the propagation delay model. A conditional branch 707 branches to 708 if the value of the propagation identifier of the element Y is not 0 and the output value of the element Y is equal to PV, and branches to 709 and 710 otherwise. At 708, the value of the propagation identifier of the element Y is set to 0. 7
At 09, the value obtained by adding the delay value D to the current simulation time XT is the propagation time 104, and the pointer value pointing to the beginning of the area for storing the information of the element Y is the propagation element identifier 10
5, an event having PV as the propagation signal value 106 and the current event identification number EID as the event identifier 107 is added to the time wheel. In 710, the propagation identifier of the element Y is set to the current event identification number EID, and the EID
Update the value of (add 1).

At 711, an event is registered as in 709. At 712, the value of EID is updated (1 is added). At 713, the value of PV is set as the next output value of the element Y.
At 714, the value of the pointer R is updated to point to the next element.

An operation example of the embodiment of the present invention described with reference to FIGS. 5 to 7 will be described with reference to FIGS. FIG. 8 is a diagram showing an example of a logic circuit used for description. FIG. 8A shows an actual logic circuit, and FIG. 8B shows a circuit when the simulation is executed. In FIG. 8A, 801 is an input terminal of the circuit, 802 is an element having a unique name of G1, and its type is NOT. 803 is an output signal of the element 802, 804 is an element having a unique name of G2, and its type is NOT.
805 is an output signal of the element 804. The input terminal 801 of the circuit is connected to the input terminals of the element 802 and the element 803. Output terminals 803 and 805 of element 802 and element 803
Is not connected to anything. In FIG. 8B, a virtual input element 81 that represents an input terminal for logic simulation.
1 is added, but the structure of the other circuits is the same as that of FIG. The unique name of the virtual input element 811 is G0. Elements 812 and 804 corresponding to 802 in FIG.
The input terminal of the element 814 corresponding to
It is connected to the output terminal of. The output terminals of the element 812 and the element 814 are not connected to anywhere as in FIG.

FIG. 9 shows an example in which the circuit of FIG. 8 is expressed based on the data structure shown by 111 in FIG. 1 (b). Figure 8
Since the circuit (b) is composed of three elements including the virtual input element, three 111-type data structures are also required.

Reference numeral 9011 represents a virtual input element G0. The top address for storing the information is set to 0. 9
012 is a number for identifying the element type and stores a value (here, 0) corresponding to the virtual input element. 9013 stores G0 which is a unique name of the element. 9014 represents the number of input terminals of the virtual input element. Since there is no input terminal in the virtual input element, 9014 is 0, and the pointer 9015 to the pointer list of the connection destination of the input does not point anywhere. 90
16 stores the output destination connection number 2 of the virtual input element. 90
17 is a connection destination pointer list 90 for the output of the virtual input element
The pointer to 33 is stored. Reference numeral 9033 is an input connection destination pointer, and elements G1 and G2 connected to the output of the virtual input element.
The top addresses 11 and 22 of the area for storing the element information of are stored.

Reference numeral 9018 stores the delay model identifier of the virtual input element. Here, the delay model identifier of the virtual input element is “propagation”. 9019 and 9020 are the output value and the next output value of the virtual input element. The initial value of these is an undefined value "X". 9021 is a propagation identifier of the virtual input element, and its initial value is 0. Since the virtual input element has no delay value, the pointer 9 pointing to the storage area of the delay value information list
022 does not point anywhere.

Reference numeral 9111 represents the element G1. The top address of the area for storing the element information is 11. 91
12 stores 1 representing the NOT element type. A unique name G1 of the element is stored in 9113. 9114 stores 1 which is the number of input terminals of the element. Reference numeral 9115 stores a pointer to an area 9131 that stores an input connection destination pointer list of the element. 9131 has elements equal in number to the input terminals of the element, and stores the head address 0 of the element information storage area of the virtual input element connected to the input terminal of the element G1. 9116 stores the number of output connection destinations of the element G1. 9
Reference numeral 117 is a pointer to a list of output connection destination pointers of the element G1. Since the output terminal of the element G1 is not connected to anything, the value of 9116 is 0, and 9117 does not point to anything.

Reference numeral 9118 stores the delay model identifier "inertia" of the element G1. 9119 and 9120 are the output value and the next output value of the element G1. The initial value of these is an undefined value "X". Reference numeral 9121 denotes a propagation identifier of the element G1 and its initial value is 0. Here, the element G1 rises (0 →
1,0 → X, X → 1) delay value is 4, falling (1 →
The delay value of 0, 1 → X, X → 0) is 2, and the area 9135 pointed to by the pointer 9122 that points to the storage area of the delay value information list
Stores a value of 4 or 2 depending on the signal change.

Reference numeral 9211 represents the element G2. The head address of the area for storing the element information is 22. The information of the element G2 stores all the same values as the information of G1 except that the element proper name 9213 is G2 and the delay model identifier 9218 of the element is “propagation”.

FIG. 10 is an explanatory diagram of an example of a test vector given at the time of simulation. Test vector 100
0 is applied to the input terminal 801 of the circuit. Signal is time 0
At 0 (1001) and then at time 5 1 (100
2), 0 at time 10 (1003), 1 at time 13 (100
4), 0 at time 16 (1005), 1 at time 19 (100
6) At time 20, it changes to 0 (1007).

11 to 46, the progress of the simulation will be described in time sequence. Further, the simulation is performed at time 25, which is the range of the test vector in FIG.
Up to.

According to the processing of 502 in FIG. 5, the simulation starts with the time XT set to 0 and the event identification number EID set to 1. The processing of 503 to 505 in FIG.
If there is no test vector or event propagating to T, do nothing. At 506, the time XT is advanced by one. Nothing is registered in the time wheel at the initial stage.

The test vector adding process 503 is performed when the signals 1001 to 1007 shown in FIG. 10 change. First, at time 0, a signal value 0 is applied to the input terminal (801 in FIG. 8) of the circuit (1001 in FIG. 10).
In the process of adding the test vector, this signal change is added to the time wheel as an event to the virtual input element as shown in FIG. Propagation time of this event 11
04 is 0, the propagation element identifier 1105 is 0 at the start address of the virtual input element information, the propagation signal value is 0, and the event identifier is the current EID value 1. By adding this event in the process of adding the test vector, EID
Is updated to 2.

Subsequently, the event propagation processing 504 is performed. The process will be described with reference to FIG. First, the output destination connection element information is initialized (611), and the event at the current time (XT = 0) in the time wheel is processed. The element G0 (virtual input element) pointed to by the extracted event 1102 is a propagation delay element, and therefore 618 in the conditional branch of 614.
Branch to the side. Since the event identifier 1107 in the event is 1, the propagation identifier 9021 in the element information is 0, and the value on the event side is large, the conditional branch of 618 branches to the 619 side. At 619, the flag is turned on, and the value of the propagation identifier of G0 is set to the value 1 of the event identifier 1107. 62
At 1 the flag is on, at 622 the output value of G0 is the initial value "X" and the propagation signal value during the event is different from 0, so 623 and thereafter are executed. At 623, the output value of G0 is set as the event propagation signal value 0, and at 624 to 626, the value of the output connection destination pointer of G0 is copied to the output connection destination element information.

As a result of the above processing, the element information is such that the output value 1219 of G0 is 0 and the propagation identifier 1221 is 1 as shown in FIG. 12, and the output connection destination element information is the element connected to the output terminal of G0 as shown in FIG. The head addresses 11 and 22 of the element information of G1 and G2 are stored.

The element output evaluation processing 505 will be described with reference to FIG. In this processing, processing is performed for each element of the output connection destination element information in FIG. First, the first element “1
The processing is performed on the element G1 which is "1". 703, regarding the element G1, the output value 0 of the element G0 connected to the input terminal of G1 and the element type identification number 1 (representing NOT) of G1 and G
A new output value PV of G0 is obtained from the next output value "X" of 1. Since the output value of NOT is 1 for the input value 0, P
V becomes 1.

At 704, the delay value D when the output value of G1 changes from "X" to 1 is obtained by referring to the delay value information list 9135. The part to be referred to is the part (X → 1) indicated by 1536 in FIG. 15, and its value is 2. PV and G
Since the next output value of "1" (FIG. 9) "X" is different, steps 706 and thereafter are executed. Since the element G1 is the inertial delay model 9118, the conditional branch 706 branches to the 707 side. Since the initial value of the propagation identifier of G1 is 0, conditional branch 707 indicates 709-7.
Branch to side 10. In 709, the propagation time is 2, XT (=
0) + D (= 2) = 2, the propagation identifier 11 representing G1, the propagation signal value PV value 1, the event identifier EID value 2
The event that is set to is registered and the value of EID is updated to 3 at 710. Further, by 713, the next output value of G1 is set to PV value 1. Next, the second element “22” of the output connection destination device information
Processing is performed on the element G2 which is

In 703 and 704, PV =
1, D = 2. At 706, since G2 is a propagation delay model, it branches to the 711-712 side. 70 in 711
Similar to the process in 9, the event having the propagation time of 2, the propagation identifier of 22 representing G2, the propagation signal value of PV 1 and the event identifier of EID 3 is registered, and the EID value is 4 at 712. To update. Through the above processing, the event 1402 caused by G1 and the event 1412 caused by G2 are registered in the time wheel as shown in FIG. 14, and the element information is the next output value 15 of G1 (1511) as shown in FIG.
20 is 1, propagation identifier 1521 is 2, G2 (1561)
The next output value 1570 of 1 becomes 1.

Next, at 506 in FIG. 5, the time XT is updated to 1. At time 1, there is no event to be added in the process of adding the test vector, and there is no event at time 1 even in the time wheel (FIG. 14).
The processing of 05 is not performed and the time XT is updated to 506 at 506.

At time 2, there is no additional test vector, so nothing is done at 503 and the event propagation processing 50
Do 4. At 504, the two events 140 shown in FIG.
2, 1412 is processed. First, event 14
12 is an event related to the element G2, and since G2 is a propagation delay model, the conditional branch 614 branches to the 618 side. The event identifier 1417 of the event 1412 is 3,
Since the propagation identifier 1571 of G2 is 0, the conditional branch 618 branches to the 619 side. In 619, the flag is turned on, and G
The propagation identifier 1571 of 2 is updated to 3. In 621, the flag is on, and in 622, the output value 1569 of G2 is “X” and the propagation signal value 1416 of the event 1412 is 1, so 62
Perform 3 and later. At 623, the output value of G2 is set to 1. 6
Nos. 24 to 626 do nothing because the G2 output connection destination number 9216 is 0.

Next, the event 1402 is processed. The event 1402 is an event related to the element G1, and since G1 is the inertial delay model, 6 is executed in the conditional branch 614.
Branch to side 15. Since the event identifier 1407 of the event 1402 is 2 and the propagation identifier 1521 of G1 is also 2, the conditional branch 615 branches to the 616 side. In 616, the flag is turned on and the propagation identifier of G1 is set to 0. At 621, the flag is turned on, and at 622, the output value 1519 of G1 is “X” and the propagation signal value 1406 of the event 1402 is 1, so 623 and thereafter are performed. At 623, the output value of G1 is set to 1. Nothing is done in 624 to 626 because the number of output connection destinations 9116 of G1 is 0. As a result of the above processing, as shown in FIG. 16, the element information is such that the output value 1619 of G1 is 1, the propagation identifier 1621 of G1 is 0, the output value 1669 of G2 is 1, and the propagation identifier of G2 is 3. In this processing, since nothing is stored in the output connection destination element information, the element output evaluation processing 505
Then nothing is done, and since there is no event at times 3 and 4, nothing is done.

At time 5, as at time 0, virtual input element G
Add an event to 0. Figure 17 shows the event to be added.
As shown in, the propagation time 1704 is 5, the propagation element identifier 17
05 is 0, propagation signal value 1706 is 1, event identifier 17
07 is 4. The event identification number EID is updated to 5 by adding an event.

The event propagation processing is performed in the same manner as at time 0, and the output value 1819 is 1 and the propagation identifier 1821 is the event identifier 1707 value 4 as shown in FIG. The output destination connection element information is the same as in FIG.

The element output value evaluation processing is performed in the same manner as at time 0. As a result, as shown in FIG.
1902 and 1912 events for the element G2 are registered. Propagation times 1904 and 1914 are delay values 4 of 1 → 0 at the current time XT (= 5) 4 (2036, 2 in FIG. 20).
086) is added to be 9. The event identifiers 1907 and 5917 are 6. As for the element information, as shown in FIG. 20, the next output value 2020 of G1 is 0, the propagation identifier 2021 is 5,
The next output value 2070 of G2 becomes zero. The event identification number EID is 7.

Nothing is done from time 6 to time 8.

At time 9, two events 1902 and 1912 are propagated in the event propagation processing as in the case of time 2. As a result, as for the element information of G1 and G2, as shown in FIG. 21, the output value 2119 of G1, the propagation identifier 2121 is 0, the output value 2169 of G2 is 0, and the propagation identifier 2171 is 6. Further, as in the case of time 2, since nothing is stored in the output connection destination element information, nothing is done in the element output evaluation processing.

At time 10, as at time 0, an event is added to the virtual input element G0. Figure 2 shows the event to be added
2, the propagation time 2204 is 10, the propagation element identifier 2205 is 0, the propagation signal value 2206 is 0, and the event identifier 2207 is 7. The event identification number EID is updated to 8 by adding an event.

The event propagation processing is performed in the same manner as at time 0, and the output value 2319 is 0 and the propagation identifier 2321 is 7 as shown in FIG. The output destination connection element information is the same as in FIG.

The element output value evaluation processing is similar to that at time 0, and as shown in FIG. 24, 2402 events for element G1 and 2412 events for element G2 are registered. Propagation times 2404 and 2414 are 0 → 1 at the current time XT (= 10).
Delay value 2 (2536, 2586 in FIG. 25) is added to obtain 12. The event identifier 2407 is 8, and 2417 is 9. The element information is the next output value 25 of G1 as shown in FIG.
20 is 1, the propagation identifier 2521 is 8, and the next output value 2 of G2 is 2
570 becomes 1. Further, the event identification number EID is 10.

At time 11, nothing is done.

At time 12, two events of 2402 and 2412 are propagated in the event propagation processing as in the case of time 2. As a result, as for the element information of G1 and G2, the output value 2619 of G1 is 1, the propagation identifier 2621 is 0, the output value 2669 of G2 is 1, and the propagation identifier 2671 is 9 as shown in FIG. Further, as in the case of time 2, since nothing is stored in the output connection destination element information, nothing is done in the element output evaluation processing.

At time 13, as in the case of time 0, an event is added to the virtual input element G0. As for the event to be added, the propagation time 2704 is 13, as shown in FIG.
The propagation element identifier 2705 is 0, the propagation signal value 2706 is 1, and the event identifier 2707 is 10. The event identification number EID is updated to 11 by adding an event.
Then, in the event propagation processing, as shown in FIG.
The output value 2819 of 0 is 1 and the propagation identifier 2821 is 10.

Further, element output evaluation processing is performed for G1 and G2, and as shown in FIG.
2, 2912 events are registered for the element G2. Propagation time 2904, 2914 is current time XT (= 13)
Is added to the delay value 4 of 1 → 0 (3036, 3086 in FIG. 30) to be 17. The event identifier 2907 is 11 or 2.
917 is twelve. The element information is G as shown in FIG.
The next output value 3020 of 1 is 0, and the propagation identifier 3021 is 1
The next output value 3070 of 1 and G2 becomes 0. The event identification number EID is 13.

At times 14 and 15, nothing is done.

At time 16, an event is added to the virtual input element G0 as at time 0. The event to be added is the propagation time 310 as indicated by 3102 in FIG.
4 is 16, the propagation element identifier 3105 is 0, and the propagation signal value is 3
106 is 0, and the event identifier 3107 is 13. The event identification number EID is updated to 14 by adding an event. Then, in the event propagation processing, as shown in FIG. 32, the output value 3219 of G0 is 0, the propagation identifier 3221
Becomes 13.

Further, element output evaluation processing is performed for G1 and G2. For G1, the G1 propagation identifier 3021
Is 11, and the G1 output value 3019 is 1, and the PV value is 1
Therefore, the conditional branch 707 of FIG. 7 branches to the 708 side. In 708, the propagation identifier of G1 is set to 0 and the next output value is set to 1. For G2, as in the case of time 0, the event is registered in 711 to 712 in FIG. 7 and the value of EID is updated. The event to be registered is only the event related to the element G2 indicated by 3302 in FIG. Propagation time 33
04 is a delay value 2 of 0 → 1 at the current time XT (= 16) (see FIG. 34).
3486) is added to make 18. Event identifier 33
07 is 14. The element information is G1 as shown in FIG.
Next output value 3420 is 1, propagation identifier 3421 is 0, G
The next output value 3470 of 2 becomes 1. The event identification number EID is 15.

At time 17, events 2902 and 2912
About event propagation processing. As for the event 2912, the event propagates similarly to the case of the time 2 and the
As shown in FIG. 5, the output value 3569 is 0, and the propagation identification value 357.
1 becomes 12. But for event 2902,
The event identifier 2907 is 11, the propagation identifier 34 of G1
Since 21 is 0, the conditional branch 615 of FIG. 6 branches to the 617 side. In 617, the flag is turned off, so 62
The processing of 2 to 626 is not performed, and the output value does not change. Since the output connection destination element information is not stored as in the case of time 2, nothing is performed in the element output evaluation processing.

At time 18, an event 330 related to G2
2 propagates. This event propagates as in the case of time 2, and the output value 3669 is 1 and the propagation identification value 3671 is 14 as shown in FIG. Since the output connection destination element information is not stored as in the case of time 2, nothing is performed in the element output evaluation processing.

At time 19, as in the case of time 0, an event is added to the virtual input element G0. The event to be added is the propagation time 370 as indicated by 3702 in FIG.
4 is 19, the propagation element identifier 3705 is 0, and the propagation signal value is 3
706 is 1, and the event identifier 3707 is 15. The event identification number EID is updated to 16 by adding an event. Then, in the event propagation processing, as shown in FIG. 38, the output value 3819 of G0 is 1, the propagation identifier 3821.
Becomes 15.

Further, element output evaluation processing is performed for G1 and G2, and as shown in FIG.
2, 3912 events are registered for the element G2. Propagation time 3904, 3914 is current time XT (= 19)
Is added to the delay value 4 of 1 → 0 (4036, 4086 in FIG. 40) to obtain 23. Event identifier 3907 is 16,3
917 is 17. The element information is G as shown in FIG.
1 next output value 4020 is 0, propagation identifier 4021 is 1
6, the next output value 4070 of G2 becomes 0. The event identification number EID is 18.

At time 20, as in the case of time 0, an event is added to the virtual input element G0. The event to be added is the propagation time 410 as indicated by 4102 in FIG.
4 is 20, the propagation element identifier 4105 is 0, and the propagation signal value is 4
106 is 0, and the event identifier 4107 is 18. The event identification number EID is updated to 19 by adding an event. Then, in the event propagation processing, as shown in FIG. 42, the output value 4219 of G0 is 0, the propagation identifier 4221
Becomes 18.

Further, element output evaluation processing is performed for G1 and G2. For G1, the propagation identifier 4021 of G1
16 and G1 output value 4019 is 1, PV value is 1
Therefore, the conditional branch 707 of FIG. 7 branches to the 708 side. In 708, the propagation identifier of G1 is set to 0 and the next output value is set to 1. For G2, as in the case of time 0, the event is registered in 711 to 712 in FIG. 7 and the value of EID is updated. The event to be registered is only the event related to the element G2 shown by 4302 in FIG. Propagation time 43
04 is the delay value 2 of 0 → 1 at the current time XT (= 20) (see FIG. 40).
4086) is added to 22. Event identifier 43
07 is 19. Element information is G1 as shown in FIG.
Next output value 4420 is 1, propagation identifier 4421 is 0, G
The next output value 4470 of 2 becomes 1. The event identification number EID is 20.

At time 21, nothing is done.

At time 22, event propagation processing is performed on the event 4302. This event propagates as in the case of time 2, and the output value 45 as shown in FIG.
69 is 1, and the propagation identification value 4571 is 19. However, the value of the output value 4569 does not change before and after the propagation. Since the output connection destination element information is not stored as in the case of time 2, nothing is performed in the element output evaluation processing.

At time 23, events 3902 and 3912
About event propagation processing. In the case of the event 3912, since the event identifier 3917 is 17 and the propagation identifier 4571 of the element G2 is 19, the conditional branch 61 in FIG.
8 branches to the 620 side. At 620, since the flag is turned off, the processing of 622 to 626 is not performed and the output value does not change. Also in the case of the event 3902, since the event identifier 3907 is 16 and the propagation identifier 4421 of G1 is 0, the conditional branch 615 of FIG. 6 branches to the 617 side.
Since the flag is turned off in 617, the processing of 622 to 626 is not performed and the output value does not change. Since the output connection destination element information is not stored as in the case of time 2, nothing is performed in the element output evaluation processing.

At times 24 and 25, nothing is done. Time 25
Is the end time of the simulation, so 50 in FIG.
The loop of 2 is ended, and the processing of the simulation shown in FIG. 5 is ended.

As a result of the above simulation, the element G1
46 shows how the output value of the element G2 changes. In the figure, reference numeral 801 denotes an input terminal, which is the same as the event shown in FIG. 10, 803 is the output of the element G1, and 804 is the output of the element G2. 460 for input change 1001 at time 0
1,4611 is 4 for the input change 1002 at time 5.
602 and 4612 appear as output changes, and 4603 and 4613 appear as output changes with respect to the input change 1003 at time 10. With respect to the input change 1004 at time 13, since the input change 1005 occurs before the signal propagates at the output 803 of the element G1 of the inertial delay model, the output signal change 460
4 does not propagate. On the other hand, a signal propagates through the output 805 of the element G2 of the propagation delay model at time 17 (4614). For the input change 1005 at time 16, nothing propagates to 803, and a signal propagates to time 805 at 805 (46
15). 80 for input change 1006 at time 19
In No. 3, since the input change 1005 occurs before the signal propagates, the output signal change 4606 does not propagate. Also in 805, since the output change 4617 accompanying the input change at time 20 propagates before the output change 4616 accompanying the input change at time 19, 4616 does not propagate. Input change 1 at time 20
For 007, nothing is propagated to 803.

According to this embodiment, it becomes possible to correctly detect invalid event propagation and perform a logic simulation in a simulation of a logic circuit in which elements of the inertial delay model and elements of the propagation delay model coexist.

[0073]

According to the present invention, in a logic simulation in which elements having different delay models are mixed, an invalid event can be efficiently detected and the logic simulation can be correctly performed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a conventional data structure for logic simulation.

FIG. 3 is an explanatory diagram of a delay model of an element.

FIG. 4 is an explanatory diagram of events that become invalid in the inertial delay model and the propagation delay model.

FIG. 5 is an explanatory diagram of a logic simulation process according to the embodiment of this invention.

FIG. 6 is an explanatory diagram of event propagation processing.

FIG. 7 is an explanatory diagram of element output evaluation processing.

FIG. 8 is an explanatory diagram of a logic circuit for explaining the operation of the exemplary embodiment of the present invention.

9 is an explanatory diagram of element information of the circuit of FIG.

FIG. 10 is an explanatory diagram of an example of a test vector according to the embodiment of this invention.

FIG. 11 is an explanatory diagram of event information added at time 0.

FIG. 12 is an explanatory diagram of information of a virtual input element updated at time 0.

FIG. 13 is an explanatory diagram of output destination connection information created at time 0.

FIG. 14 is an explanatory diagram of event information created at time 0.

FIG. 15 is an explanatory diagram of element information updated at time 0.

16 is an explanatory diagram of element information updated at time 2. FIG.

FIG. 17 is an explanatory diagram of event information added at time 5.

FIG. 18 is an explanatory diagram of information of a virtual input element updated at time 5.

FIG. 19 is an explanatory diagram of event information created at time 5.

FIG. 20 is an explanatory diagram of element information updated at time 5.

FIG. 21 is an explanatory diagram of element information updated at time 9.

FIG. 22 is an explanatory diagram of event information added at time 10.

FIG. 23 is an explanatory diagram of information of a virtual input element updated at time 10.

FIG. 24 is an explanatory diagram of event information created at time 10.

FIG. 25 is an explanatory diagram of element information updated at time 10.

FIG. 26 is an explanatory diagram of element information updated at time 12.

FIG. 27 is an explanatory diagram of event information added at time 13.

FIG. 28 is an explanatory diagram of information of a virtual input element updated at time 13.

FIG. 29 is an explanatory diagram of event information created at time 13.

FIG. 30 is an explanatory diagram of element information updated at time 13.

FIG. 31 is an explanatory diagram of event information added at time 16.

FIG. 32 is an explanatory diagram of information of a virtual input element updated at time 16.

FIG. 33 is an explanatory diagram of event information created at time 16.

34 is an explanatory diagram of element information updated at time 16. FIG.

FIG. 35 is an explanatory diagram of element information updated at time 17.

36 is an explanatory diagram of element information updated at time 18. FIG.

FIG. 37 is an explanatory diagram of event information added at time 19.

FIG. 38 is an explanatory diagram of information of a virtual input element updated at time 19.

FIG. 39 is an explanatory diagram of event information created at time 19.

FIG. 40 is an explanatory diagram of element information updated at time 19.

FIG. 41 is an explanatory diagram of event information added at time 20.

42 is an explanatory diagram of information on the virtual input element updated at time 20. FIG.

43 is an explanatory diagram of event information created at time 20. FIG.

44 is an explanatory diagram of element information updated at time 20. FIG.

45 is an explanatory diagram of element information updated at time 22. FIG.

FIG. 46 is an explanatory diagram of a simulation result.

[Explanation of symbols]

101 ... Time wheel, 102 ... Event, 103 ...
Link pointer, 132 to 136 ... Number of elements.

Claims (1)

[Claims] 1. Event information includes a signal propagation time, an identifier of element information in which a signal propagates, and a value of a signal in which the signal propagates, and the element information includes an element type identification number, an element specific name, and an input terminal. Number, a list of connection destination pointers for each input terminal, a number of connection destinations of output terminals, a list of connection destination pointers, element output values, and a logic simulation method for simulating a logic circuit according to event information. Has an event identifier that stores an event identification number that identifies each event, a delay model identifier of the element as element information, a propagation identifier that stores the event identification number, a next output value, and a delay for each type of output change. Has a value, and when the simulation is executed, the event identifier of each event and the delay of the element through which the event propagates. A logic simulation method characterized by determining validity / invalidity of an event based on a value of an extended model identifier and a value of the propagation identifier.