JPH07129477A - Error detection correcting device - Google Patents

Abstract

PURPOSE:To expand a data width without increasing the number of the signal lines of a circuit and lowering capacity. CONSTITUTION:When data are written in a memory 2 from a processor 1, 64-bit data are bisected in a data width direction and is inputted as 32-bit division data in each separate error detection correction circuit 3. In each error detection correction circuit 3, the division data successively transmitted from the processor 1 is synthesized in a writing latch 3j and data of 64-bit width which is the same as before the division is prepared. A check bit is generated from the data by a hamming code, etc., and the data and the check bit are written as a set in the memory 2. When data are read from the memory 2 to the processor 1, the data and check bit are read every set. After data are corrected in each error detection correction circuit 3, the data are divided into a reading latch 3k and is successively transmitted to the processor 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection / correction device for detecting and correcting data errors in a data storage device.

[0002]

2. Description of the Related Art Conventionally, as a method of error detection and correction in a data storage device, there is a method of correcting a 1-bit error and detecting a 2-bit error by using a check bit which is an error detection and correction code such as a Hamming code. It is used. FIG. 2 is a block diagram showing a configuration example of a conventional error detection / correction circuit. The illustrated circuit includes a data processing device 21, a data storage device 22, an error detection / correction circuit 23.
Consists of. The error detection / correction circuit 23 includes a check bit generator 3a, a syndrome generator 3b, and an error detector 3
c, error corrector 3d for correcting 1-bit error during reading, data latch 3e, error corrector 3f for correcting 1-bit error during partial writing, memory side input / output buffer 3g, processor side input / output The buffer 3h includes a merge circuit 3i for writing data and reading data at the time of partial writing.

The operations of this device during normal writing, reading and partial writing will be described below. During normal writing, the merge circuit 3i and the error corrector 3f in the write data passing path only pass the data. That is, the write data from the data processing device 1 is passed through the merge circuit 3i, then input to the check bit generator 3a, and the check bit is output from the generator. After that, the write data and the check bit pass through the 1-bit error corrector 3f and are output to the data storage device 22. In this way, the check bit is added to the write data as shown in FIG.
Stored in.

At the time of reading, read data (before correction) and check bits read from the data storage device 22 are latched by the data latch 3e and then input to the syndrome generator 3b. Then, the syndrome bit is output from the generator. As a result, the read data (before correction) and the syndrome bit are input to the 1-bit error corrector 3d. Then, the read data corrected by the syndrome bits is output from the corrector. Further, this syndrome bit is also input to the error detector 3c. As a result, the detector outputs an error signal indicating the detection of a 1-bit error or a 2-bit error.

At the time of partial writing, the error detection / correction circuit 23
This is performed when the write data smaller than the check bit generation unit is output from the data processing device 21. At the time of partial writing, the check bit and read data (before correction) read from the data storage device 22 are input to the syndrome generator 3b, and the syndrome bit is output from the generator. Further, the write portion data from the data processing device 21 and the read data (before correction) are input to the merge circuit 3i, and all write data (before correction) are output from the circuit. Then, the write data (before correction) is input to the check bit generator 3a, and the check bit is output from the generator. Thereafter, the syndrome bit, the write data (before correction) and the check bit are input to the error corrector 3f, and the corrector writes a 1-bit error in the read data from the data storage device 22 and the related check bit. The data is output.

[0006]

However, the above-mentioned conventional device has the following problems. recent years,
The data processing unit in the data processing device is becoming larger, such as a 64-bit unit or a 128-bit unit. In addition, the number of data processing devices having a data transmission mechanism is increasing in order to speed up data transfer, and there is a demand for speeding up of data storage devices. In the device having the above configuration, the data processing unit in the data processing device is the same as the error detection and correction code creation unit. Therefore, when the circuit is implemented as a single integrated circuit in a gate array or the like in order to perform the processing collectively, the number of input / output pins becomes large and the implementation is becoming difficult. For example, in a memory device for a processor having a 64-bit data processing unit, an error detection / correction circuit having a 64-bit error detection / correction code creation unit and handling 8-bit check bits has a configuration shown in FIG. If implemented as one integrated circuit, at least 64 pins are required for data transfer with the processor and at least 64 + 8 pins are required for data transfer with the memory device.

Moreover, since the access speed of the normal memory is much slower than the data processing speed of the processor, the apparent access speed is increased by a method such as memory interleaving in order to cope with a high-speed processor. In order to realize such memory interleaving, as many error detection and correction circuits as the interleaving banks are required. Therefore, if a two-way interleaved memory device is used, the number of pins for data transfer with the memory is 72 × 2 = 144 pins, and 200 pins or more are required only for transmitting / receiving data.

Currently, in general packages such as gate arrays, there are the following upper limits depending on the type of package. For example, in QFP (Quad Flat Package),
As shown in FIG. 4, pins are projected from four side surfaces of the package, and the number of pins is a little over 200 at maximum. Also, P
In GA (Pin Grid Array), as shown in FIG. 5, pins are arranged in a grid pattern from the bottom of the package, and the number of pins is 4 at maximum.
It is a little over 00 pins. Of those pins, the number of usable I / O terminals is about 90%. Therefore, implementation of such an error detection and correction circuit requires a package of PGA, which is considerably more expensive than QFP.

Of course, it is possible to divide the data into data of a small width, generate check bits for each of the divided data, and perform error detection and correction. However, in the normal generation of a 1-bit error correction 2-bit error detection code, assuming that the data bit width is M and the necessary check bit bit width is K, as shown in FIG. (1) is established. 2 ^K-1 -1 ≧ N (however, N = M + K) (1)

According to this formula, for example, the check bit is 7 bits for 32-bit width data, the check bit is 8 bits for 64-bit width data, and the check bit is 9 bits for 128-bit width data. is necessary. That is, when M is small, the ratio of K to M is large. That is, the storage area required for the error detection / correction code decreases as the data storage unit for generating the code for a fixed amount of data increases. Therefore, generating a check bit for data with a large bit width reduces the storage area for holding the check bit,
Cost reduction. Nevertheless, the bit width could not be increased so much due to the above-mentioned constraint on the number of pins. The present invention solves the above-mentioned problems, and in a data storage device that handles multi-bit width data, an error detection and correction device that hardly causes an increase in cost due to an increase in the number of signal lines and does not reduce the processing speed. The purpose is to provide.

[0011]

An error detection / correction device of the present invention divides data in a data width direction and inputs a plurality of error detection / correction circuits, respectively.
A write latch provided in each of the error detection and correction circuits, for combining a plurality of divided data continuously sent from the data processing device into one, and generating a check bit from the combined whole data, And a read latch provided in each of the error detection / correction circuits for reading out together with the check bit from the data storage device and correcting and transmitting the data corrected by the check bit. It is a thing.

[0012]

In the error detection / correction device of the present invention, when data is written from the data processing device to the data storage device, the data is divided into, for example, two in the data width direction, and the data is input to separate error detection / correction circuits. . In each error detection / correction circuit, the divided data continuously sent from the data processing device is combined by the write latch to form, for example, data having the same width as before the division. Then, a check bit is generated from the data by a Hamming code or the like, and the data and the check bit are written as one set in the data storage device. On the other hand, when data is read from the data storage device to the data processing device, the data and check bit for each set are read and input to each error detection and correction circuit. In each error detection / correction circuit, a syndrome bit is generated from the check bit, and when a 1-bit error is included, the syndrome bit is corrected by the syndrome bit. Then, the corrected data is divided by the read latch and sent to the data processing device. At this time, the data output from each error detection and correction circuit is combined to restore the original data.

[0013]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram of an embodiment of a system including an error detection / correction device of the present invention. The illustrated apparatus includes a processor 1, a memory 2, and an error detection / correction circuit 3. The processor 1 writes and reads data to and from the memory 2. The processor 1 has a data transmission mechanism of two consecutive transmissions with a data width of 64 bits. The memory 2 is composed of a RAM (random access memory) and stores check bits together with data.

The error detection / correction circuit 3 includes a check bit generator 3a, a syndrome generator 3b, and an error detector 3.
c, error corrector 3d for correcting 1-bit error during reading, data latch 3e, error corrector 3f for correcting 1-bit error during partial writing, memory side input / output buffer 3g, processor side input / output It comprises a buffer 3h, a read latch 3k having a width of 32 bits, a read data selector 3l, a write latch 3j having a width of 32 bits, and a merge circuit 3i of write data and read data for partial writing. The check bit generator 3a generates a check bit at the time of writing using a Hamming code or the like. The syndrome generator 3b generates a syndrome bit for correcting the error when a 1-bit error is detected by the check bit.

The error detector 3c detects a 1-bit or 2-bit error and outputs an error signal to the processor 1. The error corrector 3d corrects a 1-bit error in the data read from the memory 2 by the syndrome bit. The data latch 3e latches the data read from the memory 2. The error corrector 3f corrects a 1-bit error of the data read during partial writing. Here, the partial writing refers to writing in a part of a writing unit to the memory 2. Therefore, when performing partial writing, the data in the unit is read from the memory 2 and a part of it is rewritten and written. The input / output buffers 3g and 3h temporarily store data and check bits that the processor 1 writes to or reads from the memory 2.

The read latch 3k is composed of, for example, a latch circuit of each 32 bit width, and temporarily stores the data of 32 bit width continuously sent from the processor 1 and synthesizes the data of 64 bit width. The write latch 3j is composed of, for example, a latch circuit having a width of 32 bits, and temporarily stores the data having a width of 32 bits read from the memory 2 and combines the data with a width of 64 bits, for example. The read data selector 3l divides the 64-bit width data of the read latch 3k into 32-bit width data and outputs a part of the data to be sent to the processor 1. The merge circuit 3i synthesizes the write data and the read data at the time of partial writing, and outputs the data of the write unit.

Next, when writing data, when reading data,
The operation at the time of partial writing will be described. At the time of writing the data of the processor 1, the processor 1 is set to 64 as shown in FIG.
It is assumed that bit-width data A, B, etc. are transmitted in two consecutive transmissions.
In each transmission, the write data A, B having a 64-bit width is the data A1, A having a 32-bit width as shown in FIG. 6B.
It is divided into 2, B1, B2, etc. and input to the two error detection / correction circuits 3. The write data input twice by two consecutive transmissions are accumulated in the two write latches 3j and are combined into 64-bit width data A1, B1, etc., and the merge circuit 3
It is input to i.

The 64-bit wide data A1, B1 and the like pass through the merge circuit 3i, which simply allows the data to pass through during normal writing, are input to the check bit generator 3a, and have an 8-bit width from the generator. The check bit CH is output. After that, the write data A1, B1 and the like and the check bit CH are output to the memory 2 after passing through the 1-bit error corrector 3f, which simply allows the data to pass through during normal writing. The write data A1, B1, A output from the two error detection / correction circuits 3
64 + 64 bits of 2, 2, B2, etc. and 8 + 8 bits of the check bit CH, that is, 144 bits in total, are collectively written in the memory 2.

When the data is read by the processor 1, first, the data A1, B1, A2 shown in FIG.
64 + 64 bits such as B2 and 8+ check bits CH
Eight bits, that is, 144 bits in total, are collectively read. These are divided into two sets of corresponding read data A1, B1, etc. having a 64-bit width and A2, B2, etc. and a check bit CH having an 8-bit width, and are input to two error detection / correction circuits 3 for each set. The 64-bit wide read data (before correction) and the 8-bit wide check bit that have been input are latched by the data latch 3e. Then, these are input to the syndrome generator 3b, and the syndrome bits are output from the generator. After that, the read data (before correction) and the syndrome bit are input to the 1-bit error corrector 3d, and the read data (after correction) is output from the corrector. These read data are stored in the read latch 3k with a 32-bit width.

The syndrome bits are also input to the error detector 3c, and the detector 3c outputs an error signal indicating the detection of a 1-bit error or a 2-bit error. The data stored in the read latch 3k is selected by the data selector 3l and is divided into two times, and the processor 1
Is output to. The processor 1 uses each error detection / correction circuit 3
Read data of 64 bits in total is read from each of 32 bits in two consecutive transmissions. As a result, the data shown in FIG. 6A is read.

At the time of partial writing, read data (before correction) and check bits are input from the memory 2 to the syndrome generator 3b, and the syndrome bits are output from the generator. Further, the write partial data from the processor 1 and the read data (before correction) are input to the merge circuit 3i, and all write data (before correction) are output from the circuit. The write data (before correction) is input to the check bit generator 3a, and the check bit is output from the generator. Then, the syndrome bit, the write data (before correction) and the check bit are input to the error corrector 3f, and the corrector outputs the write data in which the 1-bit error in the read data and the related check bit are corrected, It is written in the memory 2.

FIG. 7 is a block diagram of another embodiment of the system including the error detection / correction device of the present invention. The illustrated apparatus comprises a processor 1, a memory 2, an error detection / correction circuit 3 ', and an I / O unit 4. Processor 1 has 6
It has a 4-bit data transmission mechanism with 4-bit data width.
The memory 2 is composed of a RAM (random access memory) and stores 128-bit wide data and 16-bit wide check bits.

The error detection / correction circuit 3'is a circuit for detecting and correcting an error in the data when the memory 2 is accessed.
It includes a data bridge circuit for the processor bus and the I / O bus. That is, the error detection / correction circuit 3'is similar to the error detection / correction circuit 3 shown in FIG.
a, syndrome generator 3b, error detector 3c, error corrector 3d, data latch 3e, error corrector 3f,
The memory side input / output buffer 3g and the processor bus side input / output buffer 3h 'are provided. The detailed description of the parts having the same configurations as those in FIG. 1 is the same as the above description, and thus the duplicate description will be omitted. On the other hand, the error detection / correction circuit 3'is provided with the input / output buffer 3h "on the I / O bus side because it performs data bridge with the I / O unit.

The error detection / correction circuit 3'is a merge circuit 3 for writing data and reading data at the time of partial writing.
i, a write latch 3j 'on the side of the processor bus having a width of 32 bits, and a write latch 3j "on the side of the I / O bus having a width of 16 bits are provided. 1 in addition to the read latch 3k 'of
A read latch 3k ″ on the I / O bus side having a 6-bit width is provided. Further, in addition to the read data selector 3l ′ on the processor bus side, the read data selector 3 on the I / O bus side is provided.
l ″.

The write data selector 3m from the processor bus side and the I / O bus side, the I / O bus → data selector 3n for the processor bus, the data selector 3o for the processor bus, and the 32-bit width Write data selector / accumulator 3p that collects the data of the above into 64 bit width data,
Processor bus → Data selector 3q for I / O bus
A data selector 3r for the I / O bus is provided. I /
The O unit 4 is a unit for performing input / output with a disk device or the like, and has a data width of 32 bits.

Next, the operations of the above-mentioned device during writing, reading and partial writing will be described. When writing data in the processor 1, it is assumed that the processor 1 sends 64-bit width data in four consecutive transmissions. That is, the data A, B, C, and D in FIG. 6A become the transmission data for one time. The write data of 64-bit width in each transmission is shown in FIG.
It is divided into 32 bit widths as shown in (2) and input to the two error detection / correction circuits 3 '. The write data input four times are accumulated in the four write latches 3j ', and are combined into 64-bit width data by the write data selector / accumulator 3p. And this 64-bit width data is
After passing through the write data selector 3m from the processor bus side and the I / O bus side, it is input to the merge circuit 3i.

During the normal writing, this 64-bit wide data passes through the merge circuit 3i, which simply allows the data to pass through, and is input to the check bit generator 3a, which outputs 8-bit wide check bits. It afterwards,
The write data and the check bit are output to the memory 2 after passing through the error corrector 3f that allows the data to pass through during normal writing. Then, 64 of the write data output from the two error detection / correction circuits 3 '
8 + 8 bits of +64 bits and check bits, that is, 144 bits in total, are collectively written in the memory 2. This is 2 of 64-bit width data of processor 1.
Since it is worth the continuous transmission, the write data for four continuous transmissions is processed by two memory writes.

When data is read by the processor 1, first, 64 + 64 bits of data and 8 + 8 bits of check bits from the memory 2, that is, 144 bits in total are shown in FIG.
As shown in (b), the data is collectively read. These are divided into two sets of corresponding read data of 64-bit width and check bits of 8-bit width, and are input to two error detection / correction circuits 3'for each set. The input read data of 64-bit width (before correction) and the input check bit of 8-bit width are latched by the data latch 3e. Then, these are input to the syndrome generator 3b, and the syndrome bits are output from the generator. Then, the read data (before correction) and the syndrome bit are input to the error corrector 3d, and the read data (after correction) is output from the corrector. This read data is read latch 3
It is stored in k'with a width of 32 bits.

The syndrome bits are also input to the error detector 3c, and the detector outputs an error signal indicating the detection of a 1-bit error or a 2-bit error. The data stored in the read latch 3k 'is selected by the data selector 3l', passes through the data selector 3o to the processor bus, and is then output to the processor 1 in two steps. As a result, the data shown in FIG. 6A is read. In this case, the processor reads 32 bits from each error detection / correction circuit in a single memory read, for a total of 64 bits.
Data reading is performed by reading bit data for two consecutive transmissions. Therefore, read data for four consecutive transmissions is processed by reading the memory twice.

When writing data to the I / O unit 4, 32
The write data of bit width is divided into 16 bit width and divided into 2
It is input to one error detection / correction circuit 3 '. The write data input four times is accumulated in the four write latches 3j ″, passes through the write data selector 3m from the processor bus side and the I / O bus side, and then is input to the merge circuit 3i. This is the same as when writing to the processor.
The write data for 3 times or less of the / O unit is processed by the partial write.

When data is read from the I / O unit 4, first, 64 + 64 bits of data and 8 + 8 bits of check bits, that is, 144 bits in total, are collectively read. These are divided into two sets of corresponding read data of 64-bit width and check bits of 8-bit width, and are input to two error detection / correction circuits 3'for each set. After that, the process is almost the same as when the processor 1 reads. However, the read data is 16 in the read latch 3k ″.
The data accumulated in the bit width and stored in the latch is selected by the data selector 3l ″, passes through the data selector 3o to the I / O bus, and then is output to the I / O unit 4 in four times. The I / O unit reads a total of 32 bits of read data from each error detection / correction circuit 3'by 16 bits, so that one read of the memory processes four read data.

At the time of partial writing, read data (before correction) and check bits are input from the memory 2 to the syndrome generator 3b, and the syndrome bits are output from the generator. Further, the write partial data from the processor and the read data (before correction) are input to the merge circuit 3i, and all write data (before correction) are output from the circuit. The write data (before correction) is input to the check bit generator 3a, and the check bit is output from the generator. Then, the syndrome bit, the write data (before correction) and the check bit are input to the error corrector 3f, and the write data in which the data related to the 1-bit error in the read data or the error of the check bit is corrected from the corrector. (Corrected) is output and written in the memory 2.

As described above, a large-scale error detection / correction circuit can be realized by being divided, and the number of data input / output signal lines in each circuit can be made an appropriate size. Therefore, the amount of all hardware is almost the same as before, and the capacity load of this circuit connected to the data storage device and the data processing device is not different from before. Further, the access speed of the data storage device when the interleaving method is used can be maintained without impairing it.

For example, an error detection / correction circuit in a 2-way interleaved memory device for a processor having a data processing width of 64 bits has a conventional configuration with only data signal lines, 64 on the processor side, and on the memory side. (64 + 8) × 2 = 144, a total of 208 are required. This number is difficult to realize as one integrated circuit considering the current integrated circuit package. However, if the present invention is applied and divided into two error detection / correction circuits, the number of data signal lines in one error detection / correction circuit is 32 on the processor side and (64+) on the memory side.
8) = 72, totaling 104, which can be easily realized as one integrated circuit. Moreover, the access speeds seen from the processor are the same, and the loads on the circuit seen from the processor side and the memory side are the same.

Further, the error detection and correction circuit in the 4-way interleaved memory device for the processor having the data processing width of 64 bits has only the data signal line in the conventional structure and has 64 lines on the processor side and the memory side. (6
4 + 8) × 4 = 288, which requires 352 in total.
Considering the current integrated circuit package, this number is
It is difficult to realize as one integrated circuit. However, if the present invention is applied and divided into four error detection / correction circuits and configured, the number of data signal lines in one error detection / correction circuit is 16 on the processor side and (64 + 8) on the memory side.
= 72, which is 98 in total, which can be easily realized as one integrated circuit. Moreover, the access speeds seen from the processor are the same, and the loads on the circuit seen from the processor side and the memory side are the same.

An error detection / correction circuit in a 4-way interleaved memory device for a processor having a data processing width of 128 bits has 128 data lines on the processor side and 128 memory lines on the processor side in the conventional configuration. (128 + 9) × 4 = 548 lines, for a total of 676 lines. This number cannot be realized as one integrated circuit considering the current integrated circuit package. However, if the present invention is applied and divided into four error detection / correction circuits and configured, the number of data signal lines of one error detection / correction circuit is 32 on the processor side and 128+ on the memory side.
9) = 137, which is 169 in total, which can be easily realized as one integrated circuit. Moreover, the access speeds seen from the processor are the same, and the loads on the circuit seen from the processor side and the memory side are the same.

Further, a processor bus connected to a processor having a data processing width of 64 bits and an I / O connected to an I / O unit having a data processing width of 32 bits.
The error detection / correction circuit that handles memory access from the bus and is compatible with 2-way interleaving has 64 processor bus side, 32 I / O bus side, and memory side (64 + 8) with only the data signal line in the conventional configuration. 2 = 144, a total of 240 are required. This number is difficult to realize as one integrated circuit considering the current integrated circuit package. However, if the present invention is applied and divided into two error detection / correction circuits, the number of data signal lines of one error detection / correction circuit is 32 on the processor bus side, 16 on the I / O bus side, and on the memory side. (64 + 8) =
The total of 72 is 120, which can be easily realized as one integrated circuit. Moreover, the access speeds seen from the processor are the same, and the loads on the circuit seen from the processor bus side and the memory bus side are the same.

The data is divided into data of a small width and input to different error detection / correction circuits, and each error detection / correction circuit outputs a check bit when generating a check bit and a syndrome bit when generating a syndrome. By communicating with each other, it is possible to generate the check bit and the syndrome for the original data. In other words, each error detection / correction circuit shares the processing of check bit generation and syndrome generation with respect to the original data, and all the error detection / correction circuits receive the finally completed check bit and syndrome bit and perform the processing. Good. This also makes it possible to improve the processing speed under the constraint of the number of pins of the error detection / correction circuit. However, when implementing these error detection and correction circuits as separate integrated circuits, the number of pins to be increased may be at least (check bits + syndrome bits), but processing should be performed by communicating with different integrated circuits. Therefore, it is much slower than the circuit configuration in which one integrated circuit is closed, and its control is considerably complicated.

In the above embodiment, the case where two error detection / correction circuits 3'are provided has been described.
The present invention is not limited to this, for example, four, eight
Any number of two or more may be provided.

[0040]

As described above in detail, according to the error detection / correction device of the present invention, a large-scale error detection / correction circuit can be divided and realized, and the number of data input / output signal lines in each circuit can be set to an appropriate size. Can be Therefore, the amount of total hardware in the circuit according to the present invention is almost the same as the conventional one, the capacity load of this circuit connected to the data storage device and the data processing device is not different from the conventional one, and the interleaving method is used. In this case, the access speed of the data storage device can be maintained.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an error detection and correction device of the present invention.

FIG. 2 is a block diagram of an example of a conventional error detection and correction device.

FIG. 3 is an explanatory diagram of a relationship between data and check bits.

FIG. 4 is an explanatory diagram of QFP.

FIG. 5 is an explanatory diagram of PGA.

FIG. 6 is an explanatory diagram of a data writing and reading procedure.

FIG. 7 is a block diagram of another embodiment of the error detection and correction device of the present invention.

[Explanation of symbols]

 1 Processor (Data Processing Device) 2 Memory (Data Storage Device) 3, 3'Error Detection and Correction Circuit 4 I / O Unit (Data Processing Device) 3j, 3j ', 3j "Write Latch 3k, 3k', 3k" Read Latch

Claims (1)

[Claims] 1. A plurality of error detection / correction circuits for dividing data in the data width direction and inputting the divided data respectively, and a plurality of error detection / correction circuits provided in each of the error detection / correction circuits and continuously transmitted from a data processing device. Write latch for synthesizing the divided data of 1 into 1 and generating check bits from the synthesized total data, and read and read from the data storage device together with the check bits provided in each error detection and correction circuit. And a read latch for dividing and transmitting the data corrected by the check bit, the error detecting and correcting apparatus.