JPH0712890A - Socket for testing semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate electrical connection work between a semiconductor integrated circuit under test and a tester. CONSTITUTION:A semiconductor integrated circuit 8 under test is set with the electrodes 9 directing upward. A cap 12 is applied to the integrated circuit 8 and the position of the electrodes 9 is confirmed through the cap 12 before the contacts 4 on the cap 12 are superposed on the electrodes 9. Since the position of the electrode 9 can be confirmed, accuracy is enhanced in the alignment of the electrodes 9 and the contacts 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor chip and FTC.
The present invention relates to a socket for electrically connecting a semiconductor integrated circuit such as (Flipped TAB Carrier) and a test device.

[0002]

2. Description of the Related Art Sockets are used for conducting tests such as burn-in on semiconductor integrated circuits of this type.

In the conventional socket, as shown in FIG. 2, the pogo pin 11 penetrates the BT substrate 10 and the socket base 1 and projects upward, so that a semiconductor integrated circuit under test (Device Under Test, hereinafter referred to as DU) is used.
The DUT 8 is set in a socket with the electrode 9 of 8) directed downward, and the electrode 9 of the DUT 8 and the pogo pin 11 are butted against each other in a one-to-one correspondence, and then the DU is inserted through the heat sink 6.
The upper surface of T8 was pressed down by hook 7.

[0004]

In the method of electrically connecting using the pogo pin shown in FIG. 2, the pogo pin 11 needs to have a diameter of about 500 μmφ in order to maintain a certain degree of strength. Requires a distance of at least 250 μm between the pogo pins in order to fix it by penetrating the substrate. If the distance between the electrodes of the FTC to be tested is 250 μm or less, the FTC and the test equipment are electrically Couldn't connect successfully.

Further, in the socket shown in FIG. 2, the DUT8
Since it is impossible to perform the alignment by visually observing the positional relationship between the electrode 9 of the DUT 8 and the pogo pin 11, the alignment of the electrode 9 of the DUT 8 and the pogo pin 1 is required.
Skilledness was required for the alignment work with 1.

In the conventional socket, as a method for visually aligning the electrode 9 of the DUT 8 and the pogo pin 11, it is conceivable to form the socket base 1 and the BT substrate 10 with transparent materials (for example, JP-A-60
-10735 gazette). However, in this case
Since the pogo pin 11 protrudes upward, the DUT
Since the electrode 9 and the pogo pin 11 are aligned with the electrode 9 of 8 facing downward, it is impossible to perform the alignment by looking down from above the heat sink 6, and the alignment is performed on the BT substrate 10. Since it is necessary to look up from the lower side to the upper side, it is necessary to perform the visual inspection in an unnatural posture, which makes the alignment work difficult. To solve this, some technical means must be taken.

Further, in the socket shown in FIG. 2, the DUT8
Since the lower surface electrode 9 is abutted against the pogo pin 11 by pressing down, if the height position of the lower surface electrode 9 is not uniform on the order of μm, the electrode 9 and the pogo pin 11 cannot be brought into contact with each other. It is necessary to manage the height on the order of μm.

It is an object of the present invention to provide a semiconductor integrated circuit socket in which the electrodes of the DUT and the electrode terminals of the socket are visually aligned in a comfortable posture.

[0009]

To achieve the above object, a semiconductor integrated circuit socket according to the present invention has a cap, and a semiconductor integrated circuit for electrically connecting an electrode of a semiconductor integrated circuit under test and a test apparatus. A circuit test socket, wherein a semiconductor integrated circuit under test is held in a posture in which an electrode faces upward when performing a test, and a cap covers the electrode from above the semiconductor integrated circuit under test. It has a cover plate and an electrode portion, the cover plate is a transparent heat-resistant insulating material through which the electrodes of the semiconductor integrated circuit under test can be seen through,
The electrode portion of the cap has a height deviation absorber and a contact,
The height deviation absorber is a compressible and deformable transparent heat-resistant insulating material that allows the electrodes of the semiconductor integrated circuit under test to be seen through. , The semiconductor integrated circuit to be tested is provided so as to face the electrodes of the semiconductor integrated circuit to be tested, and the height deviation absorber is compressed and deformed according to the height position of the electrode of the semiconductor integrated circuit to be tested and vertically displaced. It comes into contact with the electrode.

The contacts of the cap have bumps.

Further, it has a heat sink, which diffuses heat generated by the semiconductor integrated circuit under test, and has a support portion for receiving and supporting the semiconductor integrated circuit under test on its upper end surface.

[0012]

The semiconductor integrated circuit under test holds the electrode in a posture in which the electrode faces upward during the test. Then, the semiconductor integrated circuit under test is covered with a transparent cap from above, and the electrodes of the semiconductor integrated circuit under test and the contacts of the cap are aligned in a posture looking down from above through the transparent cap.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention.

In FIG. 1, an opening 10a is provided in the central portion of a BT substrate 10, and a heat sink 6 is fitted and held in the opening 10a. The heat sink 6 is provided with a groove portion 6 a for receiving the DUT 8 on the upper end surface protruding above the BT substrate 10. Further, the socket base 1 is attached to the upper surface of the BT substrate 10 so as to surround the heat sink 6, and the hook 7 for pressing down the cap 12 is attached to the socket base 1 so as to be able to rise and fall. The DUT 8 is turned upside down, its upper surface is supported by the groove portion 8 of the heat sink 6, and the electrode 9 on the lower surface is held facing upward.

The cap 12 has a cover plate 2 and an electrode portion. The cover plate 2 is a transparent heat-resistant insulating material through which the electrodes 9 of the DUT 8 can be seen. The electrode portion includes a height deviation absorber 3, a contact 4, and a power feeding contact 4 '. The height deviation absorber 3 is a transparent heat-resistant insulating material that can be compressed and deformed so that the electrodes of the DUT can be seen through, and is attached to the lower surface of the cover plate 2. The contact point 4 is provided on the lower surface of the height deviation absorber 3 so as to face the electrode 9 of the DUT 8, and the height deviation absorber 3 is compressed and deformed according to the height position of the electrode 9 of the DUT 8 to be vertically displaced. Then, it comes into contact with the electrode 9 of the DUT 8. Inside the height deviation absorber 3, a transparent conductor wiring for connecting the contact 4 to a test device (not shown) is provided.

Further, the power feeding contact 4'is provided with the height deviation absorber 3
Is provided on the lower surface on the outer peripheral edge side of the socket so as to face the power supply terminal 5 of the socket base 1. In this embodiment, the contacts 4,
Although 4'is composed of a conductor pattern obtained by patterning a metallized layer, these contacts 4, 4'may have bumps as shown in FIG. Contact points 4, 4 '
By providing the bumps on the contacts, the contacts 4 can be brought into contact with the electrodes of the semiconductor chip via the bumps even when the DUT 8 is a semiconductor chip.

In the embodiment, in order to electrically connect the DUT 8 and a test device (not shown) by sockets, first, the front and back surfaces of the DUT 8 are reversed, and the electrode 9 on the back surface side of the DUT 8 is directed upward, and the DUT 8 is heat-sinked. The heat sink 6 supports the surface side of the DUT 8 by inserting the heat sink 6 into the groove 6 a of the DUT 6.

Next, the cap 12 is covered with the DUT 8.
Then, the contacts 4, 4 ′ of the cap 12, the electrode 9 of the DUT 8 and the power supply terminal 5 are aligned with each other in a posture looking down through the cover plate 2 and the height deviation absorber 3. Cap 12
Since the area excluding the contacts 4 and 4'is transparent, when the contacts 4 and 4'are misaligned with respect to the electrode 9 of the DUT 8 and the power supply terminal 5, the misalignment amount and the direction of the misalignment are easy. The cap 12 is moved horizontally and the DUT 8
The contacts 4 and 4'of the above are visually overlapped with the electrode 9 and the power supply terminal 5 of the DUT 8.

Next, the hook 7 is hooked on the outer peripheral edge of the cap 12, and the cap 12 is pressed down by the hook 7. The contact points 4, 4 ′ of the cap 12 are the height deviation absorber 3 that is compressed and deformed.
Since the contacts 4 and 4'are supported on the lower surface of the electrode 4, the height deviation absorber 3 is compressed and deformed in accordance with the height deviation of the electrode 9 and the power supply terminal 5, and the contacts 4 and 4'are displaced up and down. 4,4 '
The electrode 9, and the power supply terminal 5 are reliably electrically connected.

An example of the socket manufacturing method according to the present invention will be described. First, a transparent insulating plate having heat resistance, for example, quartz glass is used as the cover plate 2, and the height deviation absorber 3 is formed on one surface of the quartz glass 2. Height gap absorber 3
As a transparent insulating material having heat resistance and compressive deformation,
For example, silicon rubber or a polyimide film is used, and this is attached to one surface of the quartz glass 2 or laminated by spin coating or the like. The height deviation absorber 3 may have a single-layer or multi-layer structure.

Thereafter, a metallized layer of aluminum, gold or the like is formed on the surface of the height deviation absorber 3 by sputtering, vapor deposition, plating or the like. The formed metallized layer is DU
Patterning is performed so as to match the electrode 9 of T8, and this is used as contacts 4 and 4 '.

[0022]

As described above, according to the present invention, the semiconductor integrated circuit under test is held in a posture in which the electrodes are directed upward, and the transparent cap is covered with the semiconductor integrated circuit under test.
Since the electrode is aligned through the cap, the electrode position of the semiconductor integrated circuit can be confirmed from the top of the cap, and not only the electrode can be easily aligned, but also the electrode can be aligned in a comfortable posture. it can. Further, the contacts of the cap can be formed on the plate surface of the height deviation absorber by means such as sputtering and vapor deposition, and since it is not necessary to use pogo pins as in the conventional case, the distance between the contacts is about 100 μm or less. Electrical connection can be made even in the following cases.

Further, since the contact point of the cap has the bump, the electrode of the semiconductor chip of the unmanufactured level can be electrically connected to the test apparatus by using the bump, and the burn-in test at the unmanufactured level can be performed. It can be carried out.

Further, since the heat sink has a function of supporting the semiconductor integrated circuit in addition to the function of diffusing the heat generated by the semiconductor integrated circuit under test, a separate supporting mechanism for the semiconductor integrated circuit is not required and the structure is simplified. can do.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a sectional view showing a conventional example.

[Explanation of reference numerals] 1 socket base 2 cover plate 3 height deviation absorber 4, 4'cap contact 5 power supply terminal 6 heat sink 6a heat sink groove 7 hook 8 DUT 9 DUT electrode 10 BT substrate 12 cap

Claims (3)

[Claims] 1. A semiconductor integrated circuit test socket, which has a cap and electrically connects an electrode of a semiconductor integrated circuit under test and a test device, wherein the semiconductor integrated circuit under test is: The electrode is held in a posture facing upward, the cap covers the electrode from above the semiconductor integrated circuit under test, and has a cover plate and an electrode portion, and the cover plate is the semiconductor under test. It is a transparent heat-resistant insulating material that allows the electrodes of the integrated circuit to be seen through.The electrode part of the cap has a height deviation absorber and contacts, and the height deviation absorber is the electrode of the semiconductor integrated circuit under test. It is a transparent heat-resistant insulating material that is compressible and deformable to be seen through, and is attached to the lower surface of the cover plate. Depending on the height position of the electrode of the semiconductor integrated circuit under test A semiconductor integrated circuit test socket, characterized in that the height deviation absorber is compressed and deformed, and is vertically displaced to come into contact with an electrode of a semiconductor integrated circuit under test. 2. The socket for testing a semiconductor integrated circuit according to claim 1, wherein the contact of the cap has a bump. 3. A heat sink is provided, which diffuses heat generated by the semiconductor integrated circuit under test, and has a support portion for receiving and supporting the semiconductor integrated circuit under test on its upper end surface. 3. The semiconductor integrated circuit test socket according to claim 1 or 2.