JPH07128601A - Optical scanner - Google Patents

Abstract

PURPOSE:To provide the optical scanner which is low in cost and enables highly accurate writing control like heretofore. CONSTITUTION:This optical scanner has a phase locked loop means 14 which is inputted with a source clock f0 and a horizontal synchronizing signal s1 and outputs a synchronizing source clock fs, a first timing control means 15 which outputs a video clock fc controlled in writing timing of <=1 pixels formed by utilizing the leading edge or trailing edge of the inputted synchronizing source clock fs, a second timing control means 16 which is inputted with the video clock fc and outputs an image signal reading enable signal e1 controlling in writing timing by one pixel unit and an image signal memory means 17 which outputs the reading enable signal e1 and the image signal by the video clock fc by one pixel unit each to a laser driving means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical scanning device such as a laser printer, and more particularly to an optical scanning device which is individually provided on a plurality of photoconductors to perform optical scanning.

[0002]

2. Description of the Related Art As shown in FIG. 6, in an optical scanning device of a general laser printer, a laser beam emitted from a laser light source 1 is collimated by a collimator lens 2 and then converted into parallel rays by a rotary polygon mirror 3. Scanning is performed, the scanning speed is corrected through the fθ lens 4, and the surface of the photoconductor 5 is scanned to form a latent image according to an image signal. The position for detecting the image signal writing timing on the photoconductor. The detection sensor 6 is provided in the laser beam scanning region outside the photoconductor region.

On the other hand, as shown in FIG. 7, the rotary polygon mirror 3
a, 3b, 3c, and 3d, and fθ lenses 4a, 4b,
4c and 4d, and photoconductors 5a, 5b, 5c, and 5d
In a tandem-type multicolor printer that includes a plurality of optical scanning devices for black, yellow, magenta, and cyan printers that include
Due to the fact that an optical scanning device is provided for each photoconductor,
Variations in the scanning width occur due to variations in the characteristics of each optical system, which appear as positional deviation of the image in the scanning direction, causing a problem of color misregistration between colors.

Therefore, in order to correct the color misregistration with an accuracy of one pixel or less in order to obtain a highly accurate multicolor print, as a means for changing the image signal writing timing at the same time as horizontal synchronization, Japanese Patent Laid-Open No. Sho 63- In 296559 publication,
A method is disclosed in which a plurality of clocks having the same frequency as the video clock frequency and different phases in units of one pixel or less are generated, and an appropriate clock signal is selected from the clocks. That is, a plurality of pulse signal generation circuits that generate a large number of pulse signals having the same frequency as the frequency of the image clock and a phase sequentially shifted in units of 1 pixel or less are configured, and the pulses generated by the plurality of pulse generation circuits are generated. Among them, a pulse having a delay time corresponding to the positional deviation correction value is selected to obtain an image scanning clock. On the other hand, in Japanese Laid-Open Patent Publication No. 2-26174, a horizontal synchronizing signal is delayed in an analog manner, and the delayed signal is used as a trigger to generate a PLL.
A method of starting clock oscillation using a synthesizer is disclosed.

Further, as an image writing timing variable method, a method of generating X clocks having different phases from a source oscillation clock having a frequency X times as high as a video clock, and selecting an appropriate clock from the clocks, or a method of changing a period T. In order to generate Y clocks with the same frequency and different phases from the video clock, a delay line that has a delay amount ΔT satisfying ΔT = T / Y is used, and an appropriate clock is selected from them. Has been.

[0006]

By the way, Japanese Patent Laid-Open No. Sho 63-63
In the one described in Japanese Patent Publication No. 296559, there is a problem that the circuit scale becomes large due to the fact that a plurality of clocks having different phases are simultaneously generated in the plurality of pulse generating circuits, and therefore the cost becomes high. On the other hand, in the system in which the delayed horizontal synchronizing signal is used as a trigger to start the oscillation of the clock, it is necessary to pull in the PLL synchronously at high speed every time the horizontal synchronizing signal is generated. There is a drawback that it is very difficult to satisfy the requirement of making the variable precision of the clock highly accurate, and also there is a drawback that the circuit device for analog-delaying the horizontal synchronizing signal is very expensive.

Further, in the variable image writing timing system, the one using the frequency of X times has a simple circuit structure, but in order to make the variable precision of the image signal writing timing and the horizontal synchronization precision high. In this case, the frequency of the source oscillation clock needs to be extremely high, which increases the cost, and also has the drawback that the influence of leaked radio waves on external equipment is large due to the use of high frequencies. Further, in the method using the delay line, it is necessary to use a large number of expensive delay lines in order to make the variable precision of the image signal writing timing and the horizontal synchronization precision highly accurate, and similarly the cost becomes high. It has drawbacks.

The present invention has been made in view of the above problems, and an object of the present invention is to synchronize with the phase of the horizontal synchronizing signal for detecting the write start position in the main scanning direction and to have a frequency n times the video clock frequency. Phase synchronization means for generating a synchronization source clock having the same frequency as that of the source clock and a relatively low frequency, and a rising edge or a falling edge of the synchronization source clock with an accuracy of 1 / (2n) pixel unit. First timing control means for generating a video clock whose image signal writing timing is controlled, and second timing control means for receiving the video clock and controlling the image signal writing timing with an accuracy of one pixel unit. Therefore, it is an object of the present invention to provide an optical scanning device which is provided with low cost and enables high-precision writing control similar to the conventional one.

[0009]

According to the present invention, a source clock output from a PLL synthesizer system source clock generating means, which is individually provided on a plurality of photoconductors, is input to the video clock generating means, and the video clock generating means is supplied. In the optical scanning device for scanning the photoconductor by the laser beam of the laser driving means to which the image signal synchronized with the video clock output from the
N of the video clock output from the source clock generating means
A source clock having a doubled frequency, and a horizontal synchronizing signal generated by detecting the writing start position of the photoconductor in the main scanning direction by the laser beam are input, and the phase of the source clock is synchronized with the phase of the horizontal synchronizing signal, and , A phase synchronization means for outputting a synchronization source clock delayed by a predetermined time, a synchronization source clock from the phase synchronization means, and a horizontal synchronization signal are input, and the rising edge or the falling edge of the synchronization source clock is used. First timing control means for outputting a generated video clock whose writing timing is controlled in units of 1 / (2n) pixels, a horizontal synchronization signal, and a video clock output from the first timing control means are input. Second timing control means for outputting an image signal read permission signal whose writing timing is controlled on a pixel-by-pixel basis Input read enable signals, and is in synchronization with the video clock which is configured to include an image signal storage means for outputting an input image signal in units of one pixel by one laser driving means.

[0010]

In the first timing control means, the horizontal synchronization signal and the source clock generation means of the PLL synthesizer are supplied.
A synchronization source clock fs having a frequency n times that of the video clock fc is input, and a rising edge or a falling edge of this synchronization source clock fs is used to obtain (1/2
n) Generate a video clock fc whose write timing is controlled with pixel-by-pixel accuracy, and generate the video clock f
c and the horizontal synchronizing signal are input to the second timing control means, and an image signal read permission signal whose writing timing can be controlled in units of one pixel is output. Then, the video clock fc is stored in the image signal storage means to which the image signal is input.
And a read permission signal are input, and image data is output pixel by pixel.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the structure of the present invention will be described below based on an embodiment shown in the accompanying drawings. FIG. 1 is a circuit block diagram showing an embodiment of the device of the present invention, and FIG. 2 is a timing chart for generating a synchronous source clock by inputting a horizontal synchronizing signal and a source clock to a phase synchronizer in the device shown in FIG. And a horizontal sync signal and a sync source clock
And a timing chart for generating delay controlled video clocks fc1 to fc4 in units of 1/4 pixel or less, and FIG. 3 shows a horizontal synchronizing signal and a video clock signal. 3 is a timing chart for inputting to the timing control device of No. 2 and generating a read permission signal capable of delay control in pixel units.

In a known PLL type synthesizer,
The voltage controlled oscillator 8 includes a voltage controlled oscillator (not shown) that oscillates at a frequency twice as high as the source clock fo, and a ½ frequency divider for setting the duty ratio to 50%, and is generated from the crystal oscillator 7. The reference clock fr having a predetermined frequency is divided into 1 / M by the frequency divider 12 and input to the phase comparator 10 having a built-in charge pump, and the source clock fo generated from the voltage controlled oscillator 8 is also divided. 1 / N by 11
It is input to the phase comparator 10 after being divided into. The divided clocks are compared in phase, the gate is opened for the time width corresponding to the phase difference, and the phase difference is detected from the charging voltage of the passing pulse. The error signal fe corresponding to this phase difference is converted into an error voltage through the low-pass filter 9 and is used as a control voltage for the voltage controlled oscillator 8, which is a half of one pixel period T.
/ 2 cycle, that is, a relatively low frequency source clock fo = (N / M) fr having a frequency twice that of the video clock fc is oscillated and output.

At this time, even if the set values of both frequency division ratios are changed,
In order to continuously and stably oscillate the PLL synthesizer, the frequency bands used for both frequencies fo and fr are set not to overlap. Specifically, the oscillation frequency of the source clock fo is F1, and the variable range of F1 is Fmin. ≤F1 ≤Fmax. When the oscillation frequency of the reference clock fr is F2, F2 <Fmin. , Or Fmax. The oscillation frequency F2 that satisfies <F2 is set as the reference clock fr.

The horizontal sync signal generator 13 has a built-in horizontal sync detector (not shown) for generating a horizontal sync signal of a predetermined time width such as one shot multi, and the like.
When the position detection signal from the position detection sensor 6 shown in is input, the horizontal synchronizing signal s1 shown in FIG. 2 is generated.

The phase synchronizer 14 receives the horizontal synchronizing signal s1 shown in FIG. 2 and the source clock fo output from the PLL synthesizer, adjusts the phase of the source clock fo to the phase of the horizontal synchronizing signal s1, and at the same time, horizontally. Sync signal s
A series of synchronization source clocks fs delayed by a predetermined time from the trailing edge of 1 are output.

The first timing control device 15, based on the set value set in the register 22 described later,
Any one of the video clocks fc1 to fc4 for fine write timing control in units of ¼ pixel is selectively formed and output as a video clock.
As shown in FIG. 2, the horizontal synchronizing signal s1 for counting start command is issued.
And the synchronization source clock fs are input and delayed by ΔT 1
The video clock fc1 of the pixel period is the synchronization source clock fs
Is formed using the falling edge of. Furthermore, Δ
The video clock fc2 delayed by T + (T / 4) is formed by using the rising edge of the synchronization source clock fs,
The video clock fc3 delayed by ΔT + (2T / 4) is formed by using the falling edge of the synchronization source fs, and
The video clock fc4 delayed by + (3T / 4) is formed by using the rising edge of the synchronization source clock fs.

Specifically, the timing control device 15 is provided with two toggle latches, a falling edge detecting latch 41 and a rising edge detecting latch 42, as shown in the circuit diagram of FIG. A counter 43 for counting the synchronization source clock fs is provided. When the video clock fc1 or fc3 is generated, the signal of the register 22 described later is set and the counter 4
3 selectively operates the fall detection latch 41 by using the carry signal output after counting the synchronization source clock fs by a predetermined number, and generates the video clock fc1 or fc3 using the falling edge of the synchronization source clock fs. . Then, the video clock fc2 or f
When generating c4, the counter 43 selectively operates the rising edge detection latch 42 by using the carry signal output after the counter 43 counts the synchronization source clock fs by a predetermined number.
The video clock fc2 or fc4 is generated using the rising edge of the synchronization source clock fs.

As shown in FIG. 3, the second timing control device 16 receives the video clock fc output from the first timing control device 15 and the horizontal synchronizing signal s1 for the counting start command, and receives one pixel. The image signal read permission signal e1 that enables writing timing control in units is output. That is, when the video clock fc1 delayed by ΔT is input from the first timing control device 15, based on the setting value of the register 23 described later,
As shown in the circuit diagram of FIG. 4B, the counter 46A that counts the video clock fc has the video clock fc1.
Is set by the carry signal generated after the first predetermined number of counts, the edge detection latch 45 is set to generate a read enable signal, and similarly by the carry signal generated after the counter 46B counts the second predetermined number, The reset enable signal is reset by resetting the edge detection latch 45 and the counter 46A. By setting the first and second predetermined numbers, for example, the signals e11 and e12 in FIG. 3 can be generated.

The image buffer memory 17 stores the image signal for one line stored in the memory, the read permission signal e1 output from the second timing control device 16, and the first signal.
The timing control device 15 is provided with a gate (not shown) to which the video clock fc is input, and the read enable signal e1 and the video clock fc1 are input to output the image data d1 for one line for each pixel. .

The screen generator 18 modulates the image data d1 output from the image buffer memory 17 in synchronization with the video clock fc, and supplies the modulated image signal d2 to the laser driver 19 having a built-in laser light source. The light source scans the photoreceptor according to the modulated image signal d2 to form a latent image.

The registers 20 and 21 have a division ratio M,
Based on the data of the color misregistration detector 6 shown in FIG. 7, from the table of the ROM 25 in which the setting values of the frequency division ratios M and N calculated so as to satisfy the variable precision of N and the variable range are written, the CPU 24 The appropriate frequency division ratio selected by the command is set. Further, in order to cause the first timing control device 15 to generate any of the video clocks fc1 to fc4, the register 22 detects the synchronization source clock fs based on the count value of the synchronization source clock fs. A command signal (LSB) for selectively operating one of the rising edge detection latch 42 or the falling edge detection latch 41 is set, and an initial value (higher bit) for setting the counter value in the counter 43 is set. )
give. Further, in order to output e1 to the register 23, data for setting the initial values to the counter 46A and the counter 46B is given.

The operation of the apparatus thus constructed will be described with reference to FIG.
Will be described again. The frequency dividers 12 and 11 of the voltage controlled oscillator 8 have frequency division ratios M and N of, for example, 1/4.
When the write timing is controlled on a pixel-by-pixel basis, a predetermined variable precision is satisfied so that the source clock fo having a frequency twice that of the video clock fc is output, and a variable range is satisfied so that the used frequency bands do not overlap. The set frequency division ratios M and N calculated accordingly are set in the registers 20 and 21, and the video clock fc is also set to the registers 22 and 23 of the first and second timing control devices 15 and 16.
1, the set value for obtaining the read permission signal e11 is set.

The phase synchronizer 14 has a source clock fo = (N / N) that is stably output from the PLL synthesizer and has a frequency twice that of the video clock fc.
M) fr and the horizontal synchronization signal s1 output by the detection signal from the position detection sensor 6 of the horizontal synchronization signal generator 13.
Are input, and as shown in the timing chart of FIG. 2, the source clock fo is synchronized with the phase of the horizontal synchronization signal s1.
A series of synchronization source clocks fs delayed by a predetermined time from the trailing edge of the horizontal synchronization signal s1 are output at the same frequency as the above.

In the timing controller 15, the synchronization source clock fs and the horizontal synchronization signal s1 are input, and as shown in the timing chart of FIG. 2, the first shot, the second shot, the third shot, and the fourth shot. Synchronous source clock f of occurrence
The falling edge of s is used to generate the video clock signal fc1 whose writing position is delayed by ΔT time.
In addition, ΔT + (T / 4) or ΔT + (3T /
4) When the time-delayed video clocks fc2 and fc4 are generated, as described above, the second and third shots are ... And the subsequent shots, or the third and fourth shots,
... When the video clock fc3 generated by using the subsequent rising edge of the synchronization source clock fs and delayed by ΔT + (2T / 4) time is generated, the second and third shots are ... Generated by using the falling edge of the subsequent synchronization source clock fs. Therefore, register 2
Depending on the setting value of 2, any one of the video clocks fc1, fc2, fc3, or fc4, which is delay-controlled in 1/4 pixel units, is formed.

In the timing control device 16, the video clock fc1 and the horizontal synchronizing signal s1 are input from the first timing control device 15 and are input to the image buffer memory 17 as shown in the timing chart of FIG. The read permission signal e11 of the image signal is output. Also,
By changing the setting value of the register 23, one pixel cycle T
The read enable signal e12 delayed by the above is output.
It should be noted that the video clock fc2, fc3, or f output from the timing control device 15 is fed to the device 16.
When c4 is input, it is 1/4 that of the video clock fc1.
The read enable signal e1 delayed by each pixel cycle is generated, and the read enable signal e1 can be further generated by the read enable signal delayed by one pixel cycle T.

In the image buffer memory 17, the input image signal is read from the read permission signal e1 output from the timing control device 16 and the first timing control device 15.
The image data d1 is read out for each pixel by the video clock fc output from. The screen generator 18 modulates the image data d1 output from the image buffer memory 17 in synchronization with the video clock fc, and supplies the modulated image signal d2 to a laser driver 19 having a built-in laser light source. The photoconductor is scanned according to the generated image signal d2 to form a latent image. It should be noted that each optical scanning device performs its own writing timing control, thereby performing color misregistration-corrected printing.

The timing control device 15 described above causes the synchronization source clock fs to be n times the video clock fc.
It is needless to say that the write timing can be controlled in 1 / (2n) pixel units by using the rising edge or the falling edge of the synchronization source clock fs. For example, as shown in FIG. 5, when the synchronization source clock fs that is three times as high as the video clock is used, the synchronization source clock fs
, For example, the rising edge of the first pulse, and 2
The video clock fc1 delayed by ΔT is generated by using the falling edge of the fourth occurrence, the rising edge of the fourth occurrence, the falling edge of the fifth occurrence, ... And the falling edge of the first occurrence. Using the edge, the third rising edge, the fourth falling edge, the sixth rising edge, and so on, ΔT + (T /
6) The pixel-delayed video clock fc2 is generated, and the second rising edge, the third falling edge, the fifth rising edge, and the sixth falling edge are ...・ By using ΔT + (2T /
6) Generate the video clock fc3 with pixel delay.
Then, using the falling edge of the second shot, the rising edge of the fourth shot, the falling edge of the fifth shot, the rising edge of the seventh shot, ..., ΔT + (3T /
6) The pixel delayed signal fc4, the third rising edge, the fourth falling edge, the fifth falling edge, the sixth falling edge, ... The signal fc5 delayed by ΔT + (4T / 6) pixels is used to further generate the third falling edge, the fifth rising edge, the sixth falling edge, and the eighth rising edge. , And ... are used to delay the video clock f by ΔT + (5T / 6) pixels
c6 can be generated. 4 times the synchronization source clock f
Similarly, a write timing control signal delayed by 1/8 pixel is formed using s.

Further, since the timing control function is assigned to the timing control device 15 for fine timing control in units of 1 pixel or less and the timing control device 16 for coarse timing control in 1 pixel units, the conventional device is used. 1 pixel unit timing control, for example, 1 /
When timing control in units of 4 pixels is performed together by one circuit device, it is necessary to connect four 1-bit counters in cascade. According to the present embodiment, as described above, one pixel is used. The following units use the method of forming the video clock fc by using the rising edge and the falling edge of the synchronization source clock fs. Therefore, when the timing control is performed in 1/4 pixel units, Lower than the frequency used by the conventional device described above, that is, a relatively low frequency synchronization source clock fs that is 1/2 the video clock.
Even with the use of, it is possible to control the timing in the unit of 1/4 pixel with the same accuracy as the conventional one, and moreover, the counter only requires one 1-bit counter and a plurality of latches. In addition, the second timing control device for generating the read enable signal e1 shifts pixel by pixel using a video clock having a frequency lower than the synchronization source clock fs, instead of counting a high frequency clock as in the conventional device. It suffices to provide a 1-bit counter and a rising edge detection latch.

Further, by using a general-purpose phase synchronization IC such as M66235 manufactured by Mitsubishi Electric for the phase synchronization device 14, it becomes possible to easily generate a highly accurate synchronization source clock fs. For example, video clock fc = 1
When the frequency is 5 MHz, the synchronization accuracy is 1/10 pixel or less.

[0030]

As described above, according to the present invention, the phase synchronizing means synchronizes the source clock fo having a frequency n times the video clock stably output from the PLL synthesizer with the horizontal synchronizing signal, A synchronous source clock fs, which has the same frequency as the source clock fo and is delayed for a predetermined time, is formed, and further, as write timing control means,
(1 / 2n) First timing control means for controlling the image writing timing with a pixel-unit accuracy and second timing controlling means for controlling the image writing timing with a one-pixel accuracy are independent timing control accuracy. The coarse,
Since the first timing control unit is configured to enable write timing control of one pixel or less by utilizing the rising edge or the falling edge of the synchronization source clock fs, the first timing control unit is configured to finely divide the video. Synchronous source clock f having a frequency n times that of the clock fc
Using s, high-precision write timing control can be performed in 1 (/ 2n) pixel units as in the conventional case.

Then, the first timing control means is
Since the video clock fc whose timing is controlled in units of pixels or less is formed by using the rising edge and / or the falling edge of the synchronization source clock fs, the video clock in units of 1 pixel or less as in the conventional device. fc
Compared to what is done using a counter to form all,
The circuit scale can be reduced, and the synchronization source clock fs having a frequency relatively lower than the frequency used by the conventional device can be used for the timing control.
The timing control means of (1) does not process a high frequency and does not need to increase the circuit scale because the timing control means performs the timing control on a pixel-by-pixel basis using the video clock fc lower than the frequency of the synchronization source clock fs. Therefore, the circuit scale can be reduced to save space, and the cost of the optical scanning device can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the device of the present invention.

FIG. 2 is a block diagram showing a synchronization source clock f in the apparatus shown in FIG.
6 is a timing chart illustrating an operation of forming s and video clocks fc1 to fc4 whose write timing is controlled in units of ¼ pixel.

FIG. 3 is a timing chart for explaining an operation of controlling the write timing of the image data read permission signal in units of pixels in the device shown in FIG.

4A is a diagram exemplifying a circuit of a first timing control circuit 15, and FIG. 4B is a diagram exemplifying a circuit of a second timing control device 16. FIG.

FIG. 5 is a circuit diagram of the apparatus shown in FIG. 1, which uses a synchronization source clock fs having a frequency three times as high as that of a video clock,
Write timing control signal fc1 with a precision of 6 pixels
8 is a tying chart for forming fc6.

FIG. 6 is a schematic perspective view of a conventional optical scanning device.

FIG. 7 is a schematic configuration diagram of a conventional multicolor laser printer having a plurality of optical scanning devices.

[Explanation of symbols]

1 laser light source, 2 collimator lenses, 3, 3a, 3
b, 3c, 3d rotating polygon mirror 4, 4, 4a, 4b, 4c,
4d fθ lens, 5, 5a, 5b, 5c, 5d photoconductor, 6 position detection sensor, 7 crystal oscillator, 8 voltage controlled oscillator, 9 low pass filter, 10 phase comparator, 1
1, 12 frequency divider, 13 horizontal synchronizing signal generator, 14
Phase synchronization device, timing control device of 15 1 pixel or less, 16 1 pixel unit timing control device, 17 image signal buffer memory, 18 screener generator,
19 laser driver, 20, 21, 22, 23 register, 24 CPU, 25 ROM, fr reference clock, fo source clock, fs synchronous source clock, fc
Video clock, d1 image data, e1 read enable signal.

Claims (1)

[Claims] 1. A PLL provided on each of a plurality of photoconductors individually.
The source clock output from the synthesizer type source clock generating means is input to the video clock generating means, and the image signal synchronized with the video clock output from the video clock generating means is input by the laser beam of the laser driving means. In the optical scanning device for scanning the photoconductor, the video clock generating means writes the photoconductor in the main scanning direction by a source clock having a frequency n times as high as the video clock output from the source clock generating means and a laser beam. Phase synchronization means for inputting a horizontal synchronization signal generated by detecting a position, synchronizing the phase of the source clock with the phase of the horizontal synchronization signal, and outputting a synchronization source clock delayed by a predetermined time; The sync source clock and the horizontal sync signal from the synchronizing means are input, and the sync source clock rises. First timing control means for outputting a video clock whose write timing is controlled in 1 / (2n) pixel units generated by using a rising edge or a falling edge, the horizontal synchronization signal, and the first timing control means. Second timing control means for inputting the video clock output from the timing control means and outputting an image signal read permission signal whose write timing is controlled in pixel units; and the read permission signal input,
And an image signal storage means for outputting an input image signal to the laser driving means in units of one pixel in synchronization with a video clock.