JPH07123297A - Dispersal signal eliminating circuit - Google Patents

Abstract

PURPOSE:To prevent deterioration in picture quality by calculating a mutual difference from clamp results at different points of time in a field, generating a correction signal with an amplitude depending on the difference and having the same period as that of a dispersal signal and reducing the signal from a video input signal. CONSTITUTION:A noise reduction circuit 22 eliminates noise superimposed on a video input signal SIN in a dispersal signal elimination circuit. A level difference detection circuit 23 calculates a level difference of clamp level signals at different timing points when noise components are eliminated. An integration device 24 integrates a level difference signal S23 and an inverse phase generating circuit 25 inverts the polarity. A signal holding circuit 26 holds an inverted phase signal S25 and a DAC 27 converts the signal into an analog signal. A triangle wave generating circuit 28 generates the same correction signal S28 as a dispersal signal and gives it to an adder 21, in which the signal is subtracted from the video input signal SIN thereby preventing production of flicker on a screen.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to transmitting an FM-modulated signal in satellite broadcasting such as high-definition television.
The present invention relates to a circuit that removes the adverse effect of a dispersal (dispersion) signal superimposed on a video signal in order to prevent power from being concentrated.

[0002]

2. Description of the Related Art For example, in satellite broadcasting such as high-definition broadcasting, a video signal is transmitted by performing FM modulation. However, in order to prevent power concentration due to FM modulation, a dispersal signal is converted into a video signal. It is superimposed and transmitted. FIG. 4 shows the waveform of such a dispersal signal S _DSP . The period τ of this dispersal signal S _DSP is 1
/ 30 seconds, its waveform is a triangular wave, and its frequency deviation range f _RANG is 600 kHz of the range for performing FM modulation.
It is _Z. The MUSE decoder in the receiver for high-definition broadcasting is generally provided with a circuit for clamping a video signal as shown in FIG.

The clamp circuit shown in FIG. 5 includes an amplifier circuit 11, a capacitor 12, a resistor 13, a switch circuit 14, a variable voltage power source for amplifying a video input signal SIN in which the dispersal signal S _DSP is superimposed on a video signal. An amplifier circuit 16 and an amplifier circuit 16 are connected as shown. The operation of this clamp circuit will be described. The switch circuit 14 is closed (turned on) only while the horizontal synchronizing signal HD included in the video signal (MUSE signal) is present, and the incoming video signal is clamped by the capacitor 12, the resistor 13 and the amplifier circuit 16. While the horizontal synchronizing signal HD is not present, the switch circuit 14 is opened (turned off), and the MUSE signal is DC-corrected by the amount of charge stored in the capacitor 12. The clamp circuit of FIG. 5 has a capacitor 12 and a resistor 13
And constitute a differentiating circuit. Therefore, there is a problem that the DC component differentiated by the CR differentiating circuit affects the level clamp. As a specific example of this effect, flicker or the like is generated on the screen of the television receiver, and the image quality of the image on the television receiver is degraded. The level of DC that affects the clamp level is (capacitor 1
2 capacitance C) × (resistance value R of resistor 13) × (slope of dispersal signal S _DSP )
If the time constant of the differentiating circuit specified by is reduced, it becomes closer to the hard clamp circuit and is easily affected by noise. Therefore, it is not easy to adopt a measure to reduce the time constant.

The inventor of the present application is, for example, Japanese Unexamined Patent Publication No.
As disclosed in Japanese Patent Laid-Open No. 216460, there is proposed a dispersal signal removing circuit which solves the above-mentioned problems. That is, a dispersal signal removing circuit having a simple circuit configuration is proposed, which maintains the values of the capacitor 12 and the resistor 13 and does not receive the influence of the DC component of the differentiating circuit. The dispersal signal removing circuit is shown in FIG. This dispersal signal removal circuit is a clamp circuit in which an A / D conversion circuit (ADC) 17 is added to an amplifier circuit 11, a capacitor 12, a resistor 13, a switch circuit 14, a power supply 15 and an amplifier circuit 16 which form a clamp circuit. 1 and an amplifier circuit 121 designed with the same circuit configuration and the same circuit conditions as the clamp circuit 1,
Capacitor 122, resistor 123, switch circuit 12
4, power supply 125, amplifier circuit 126, and ADC 12
7, a dispersal signal detection circuit 100 in which an arithmetic control circuit 128 realized by a micro computer or the like is added,
Further, it comprises a signal addition circuit 103.

The basic operation of the dispersal signal removing circuit shown in FIG. 6 will be described. The clamp circuit 1 operates as a circuit for clamping the video signal, and the dispersal signal detection circuit 100 generates the signal by differentiating the dispersal signal by the differentiating circuit formed by the capacitor 12 and the resistor 13 in the clamp circuit 1. The DC component is detected and output to the signal addition circuit 103. In the signal addition circuit 103, the DC component included in the clamp signal is subtracted from the clamp signal from the ADC 17, and the clamp output signal SO
Output as UT. The operation of the clamp circuit 1 is similar to that of the clamp circuit shown in FIG. The dispersal signal D _SP shown in FIG. 7A is similar to the _dispersal signal S _DSP shown in FIG. 4, and the frequency deviation range f _RANG = 600 k.
H _Z is a triangular wave with a period τ = 1/30 seconds, and this dispersal signal S _DSP is superimposed on the video signal to obtain the input signal S.
It is input to the amplifier circuit 11 of the clamp circuit 1 as IN. When the horizontal synchronizing signal HD is on, the capacitor 12,
Input signal SIN in the circuit of resistor 13 and amplifier circuit 16
Is clamped, converted into a digital signal by the ADC 17, and applied to the signal addition circuit 103. Due to the influence of the differentiating circuit composed of the capacitor 12 and the resistor 13, the DC component due to the differentiating circuit composed of the capacitor 12 and the resistor 13 is also superimposed on the digital clamp signal applied to the signal adding circuit 103. There is.

Since the dispersal signal detecting circuit 100 detects the DC component detected by the differentiating circuit, the amplifying circuit 121, the capacitor 122, the resistor 123, the switch circuit 124, the variable voltage power source in the dispersal signal detecting circuit 100. 125, amplifier circuit 126 and ADC 127
Are designed under the same conditions as the circuits in the corresponding clamp circuit 1, and operate similarly to the clamp circuit 1. The time constant of the differentiation circuit composed of the capacitor 122 and the resistor 123 is the same as the time constant of the differentiation circuit composed of the capacitor 12 and the resistor 13. There are two types of operation timing of the switch circuit 124 that is on / off controlled by the arithmetic control circuit 128. The first method is the switch circuit 124.
And the switch circuit 14 are simultaneously switched, and the second method is to turn on the switch circuit 124 when the MUSE signal is at the clamp level.

The operation timing of the switch circuit 124 will be described with reference to the MUSE transmission signal format shown in FIG. M
In the USE transmission signal, the clamp level is defined in the line 563 and the line 1125, which is one line before the line 1, and the dispersal signal S _DSP is superimposed on the gray level signal. These lines are L1 indicating the zero-cross position of the dispersal signal S _DSP shown in FIG.
Corresponds to the beginning of and the midpoint of L563. The DC component of the dispersal signal can be accurately detected by detecting the DC component resulting from the dispersal signal at the gray level. The arithmetic control circuit 128 turns on the switch circuit 124 at the timing of the line 1125, which is one line before the line 1 in the television receiver, and inputs the clamp value when the dispersal signal S _DSP has a negative slope.
Further, the switch circuit 124 is turned on at the timing of the line 563 to input the clamp value when the dispersal signal S _DSP has a positive slope.

The arithmetic control circuit 128 calculates the difference between the clamp values input at these timings to calculate the capacitor 122.
And the dispersal signal S _DSP by the resistor 123
The DC component generated by differentiating is detected, the DC component is output to the signal addition circuit 103, subtracted from the clamp value, and D included in the clamp signal in the clamp circuit 1 is detected.
Compensate for the C component. As a result, the DC component included in the clamp signal is compensated and the clamp result for the video signal is obtained.

Further, since the DC component contained in the clamp signal shows a transition state by the transient response obtained by differentiating the dispersal signal by the differentiating circuit by the capacitor 12 and the resistor 13, the transition component due to this transient response can also be compensated for. The arithmetic control circuit 128 performs the processing described below.
The waveform shown in FIG. 7B is expressed by the following equation 1 when the slope of the dispersal signal including the line 563 is positive,
When the slope of the dispersal signal including the line 1125 is negative, it is expressed by the following equation 2.

2α (1-exp (-t / CR))-α (1) -2α (1-exp (-t / CR)) + α (2) where α is the above deviation Yes, C is the capacitance of the capacitor 12, R is the resistance value of the resistor 13, and t is the time.

The arithmetic control circuit 128 uses the transition state compensation signal based on the above equation to determine the signal addition circuit 10
Compensation of the DC component in 3 performs accurate compensation in consideration of transition states.

[0012]

In the above-mentioned dispersal signal elimination circuit, the capacitor 12 and the resistor 1 are provided.
3, the capacitor 12, which operates exactly the same as the clamp circuit 1 including the switch circuit 14 and the variable voltage power supply 15,
2, resistor 123, switch circuit 124 and power supply 12
It is necessary to provide the second clamp circuit 100 consisting of 5 and the circuit manufacturing conditions are strict. In addition to the high-speed operation ADC 17 such as a video signal, the same high-speed operation AD 17
It is necessary to provide C127. Furthermore, the arithmetic control circuit 128 that performs the above-described complicated control processing must be provided to control the switch circuit 124 at strict timing.

An object of the present invention is to provide a dispersal signal removing circuit having a simple circuit configuration, which has substantially the same effect as the above-mentioned dispersal signal removing circuit.

[0014]

In order to solve the above-mentioned problems, in the present invention, in addition to a signal clamp circuit for clamping a video signal including a differentiation circuit element and on which a dispersal signal is superimposed, different signals in the field are provided. A difference between the clamp results at a time point is calculated, a correction signal having an amplitude according to the difference and having the same cycle as the dispersal signal is generated, and the correction signal is subtracted from the dispersal signal to obtain the signal. A correction circuit for applying to the clamp circuit is provided.

[0015]

The difference between the levels of the clamp signals is calculated, and a correction signal having an amplitude corresponding to the level difference and a waveform similar to the dispersal signal and having a similar waveform is generated, and the correction signal is subtracted from the video input signal. As a result, the level difference caused by the dispersal signal is eliminated.

[0016]

1 shows the configuration of a dispersal signal removing circuit according to an embodiment of the present invention. This dispersal signal removal circuit includes a capacitor 12, a resistor 13, and a switch circuit 1.
4, a clamp circuit 1 including a variable voltage power supply 15, an amplifier circuit 11, an amplifier circuit 16, and an ADC 17. The circuit configuration is similar to that illustrated in FIGS. 5 and 6.
The dispersal signal removal circuit also includes an adder circuit 21, a noise reduction (noise removal) circuit 22, a level difference detection circuit 23, an integrator 24, an anti-phase wave generation circuit 25, a signal holding circuit 26, a digital-analog converter (DAC). )
27 and a triangular wave generation circuit 28. Further, the dispersal signal removal circuit has a switch 32 for enabling or disabling the AND gate 31 and the signal holding circuit 26.

In this embodiment, the video input signal SIN also has the MUSE signal format illustrated in FIG. 3A to 3E show signal waveforms in the dispersal signal removing circuit shown in FIG.
For the MUSE transmission signal, the line 56 in the same field
3 and the line 1125, which is one line before the line 1, define the clamp level, and the dispersal signal S _DSP is superimposed on the gray level signal. These lines correspond to the beginning of L1 and the midpoint of L563 indicating the zero-cross position of the dispersal signal S _DSP shown in FIG. By detecting the DC component due to the dispersal signal at the gray level, the DC component of the dispersal signal can be accurately detected. The dispersal signal D _SP shown in FIG. 3A is similar to the _dispersal signal S _DSP shown in FIG. 4, and the frequency deviation range f _RANG = 600 k.
H _Z is a triangular wave with a period τ = 1/30 seconds. Specific numerical values of the clamp circuit 1 will be illustrated. Dispersal signal S
The output when the _DSP passes through the clamp circuit 1 (differential circuit) is expressed by the following equation.

(A) When the slope of the dispersal signal is positive: -2α (1-exp (-t / CR)) + α (1) (b) When the slope of the dispersal signal is negative: 2α (1 −exp (−t / CR)) − α (2) where α is the deviation, C is the capacitance of the capacitor 12, R is the resistance value of the resistor 13, and t is the time. Indicates.

Here, R = 1 KΩ and C = 0.01 μF, and the clamp time in the HD period, that is, the time for turning on the switch per line is τ ₀ = 0.5 μs. Α that can be detected in the line 1125 is t = 281 (line) × τ
₀ , and the apparent switch on-time is 281 × τ
₀ = 140.5 μs. Similarly, for the line 563, the on time of the switch is 140.5 μs. Using the above data, the following is obtained, the transient phenomenon is almost completed, and the DC component can be detected.

(1-exp (−281τ ₀ /CR))=0.99999992

[0021] Thus, since the DC component caused by the CR differentiating circuit provided in the clamping circuit 1 is differentiated dispersal signal S _DSP can be accurately removed from the clamp results of dispersal signal S _DSP The video signal can be clamped with high accuracy without being affected by the superposition.

The adder circuit 21 adds the video input signal SIN and the correction signal S28 output from the triangular wave generation circuit 28 and applies the corrected video signal S21 to the amplifier circuit 11. Amplifier circuit 11, clamp circuit 1, amplifier circuit 16 and AD
Since the operation of C17 is the same as the above-mentioned operation, its explanation is omitted. If the signal subtraction circuit 21 and the noise reduction circuit 22 to the triangular wave generation circuit 28 are not provided and the dispersal signal S _DSP shown in FIG. As illustrated in FIG. 3B, which is similar to that illustrated in FIG.
The clamp output signal S17 from 7 has the waveform shown in FIG.

Since the noise reduction circuit 22 performs signal processing by the level difference detection circuit 23 to the triangular wave generation circuit 28, it removes noise components. In the present embodiment, the noise reduction circuit 22 uses the MUS as shown in FIG.
The noise components on the lines 563 and 1125, which indicate the gray level that is the clamp level of the E signal, are removed. As the noise component, there can be a noise component superimposed in the video input signal SIN and a noise component superimposed in the dispersal signal removing circuit. Since the clamp output signal S17 of the ADC 17 (that is, the clamp output signal SOUT) is a digital value, the noise reduction circuit 22 removes the respective noise components contained in the signals of the line 563 and the line 1125 by digital filtering.

The level difference detection circuit 23 includes the line 5 from which the noise component is removed in the noise reduction circuit 22.
The level difference of the signal between 63 and the line 1125 is calculated.
That is, the level difference detection circuit 23 calculates the level difference of the clamp level signal at different timings and times.
This level difference is also a digital signal. The integrator 24 is
Digital level difference signal S from level difference detection circuit 23
Integrate 23. In the present embodiment, the integrator 24 is composed of an up / down counter, and when the value of the level difference signal S23 is a positive value, the value of the up / down counter is increased by a value corresponding to the magnitude of the level difference signal S23 and the level difference signal S23 If it is a negative value or a negative value, the value of the up / down counter is decremented by the value corresponding to that value.

The anti-phase wave generation circuit 25 generates an anti-phase signal S25 of the integrated signal S24 integrated by the integrator 24. In this embodiment, as shown in FIG. 3D, the polarity of the input integrated signal S24 is inverted in the anti-phase wave generation circuit 25. The signal holding circuit 26 inputs and holds the anti-phase signal S25. The signal holding circuit 26 is a data latch in this embodiment. This input hold operation is
The switch 32 is closed to the contact a side only while the anti-phase signal S25 is input to the signal holding circuit 26, and the AND gate 3
The clock CLK applied to 1 shifts the anti-phase signal S25 to the signal holding circuit 26 and holds it. Thereafter, the switch 32 is closed to the contact b side, the switch 32 is grounded, the shift operation is stopped, and the shifted antiphase signal S25 is maintained in the signal holding circuit 26.

The DAC 27 converts the holding signal S26 from the signal holding circuit 26 into an analog signal. As illustrated in FIG. 3E, the triangular wave generation circuit 28 has a triangular wave shape, that is, a dispersal signal S _DSP , having an amplitude proportional to the magnitude (amplitude) of the integrated antiphase signal S27 in the analog signal form. The same triangular wave correction signal S28 is generated. Specifically, the triangular wave generating circuit 28 is configured as an integrating circuit having good linearity using an operational amplifier circuit, and increases the output voltage thereof when a positive integration anti-phase signal S27 is applied, and a negative integration When the integrated anti-phase signal S27 is applied, its output voltage is reduced. As a result, in response to the application of the integrated anti-phase signal S27 illustrated in FIG.
A triangular wave correction signal S28 whose direction changes in accordance with the timing of the horizontal synchronizing signal of the SE signal is output.

The correction signal S28 is the video input signal SIN applied to the adder circuit 21, as illustrated in FIG.
Is the opposite of the polarity. Therefore, the adder circuit 21 finally subtracts the correction signal S28 due to the difference in clamp level between the line 563 and the line 1125 of the MUSE signal from the video input signal SIN and outputs the corrected video signal S21. The clamp circuit 1 clamps the corrected video signal S21, and the clamped signal passes through the clamp output signal S17 to the clamp output signal S17 (clamp output signal SO
UT) is output. The corrected video signal S21 is shown in FIG.
Since the level difference illustrated in FIG. 3B is eliminated, the clamp output signal SOUT has no level difference due to the presence of the dispersal signal S _DSP component shown in FIG. 3B. As a result, flicker can be prevented from occurring on the screen of the television receiver.

Comparing the dispersal signal elimination circuit of the embodiment of the present invention illustrated in FIG. 1 with the dispersal signal elimination circuit described in the prior application shown in FIG. 6, the following differences are recognized. (1) In the dispersal signal removal circuit shown in FIG. 1, the signal subtraction circuit 21 is provided in the preceding stage of the clamp circuit 1, and the noise reduction circuit 2 is provided for the video input signal SIN.
2-Correction signal S detected by triangular wave generation circuit 28
The circuit configuration is such that 28 is fed back. On the other hand, the dispersal signal removing circuit shown in FIG. 5 has a feedforward circuit configuration in which the adder 103 is provided in the subsequent stage of the clamp circuit 1. That is, the circuit configuration of this embodiment converges so that there is no level difference. (2) In the present embodiment, a DAC 27 having a simple circuit configuration and a low cost is provided in place of the high-speed ADC 127 in the dispersal signal removing circuit shown in FIG. (3) The noise reduction circuit 22 and the level difference detection circuit 23 can be realized by existing signal processing circuits, the integrator 24 is a normally used up / down counter, and the anti-phase wave generation circuit 25 is simply a polarity conversion circuit. The signal holding circuit 26 is a register, and the triangular wave generating circuit 28 is an operational amplifier circuit, so that it can be realized by an existing conventional circuit, and the operation control circuit 128 for performing the expensive and complicated processing shown in FIG.
No need to use.

The implementation of the dispersal signal removing circuit of the present invention is not limited to the above-described one, but various modifications can be adopted. The dispersal signal removal circuit illustrated in FIG. 1 will be described. In the path of the level difference detection circuit 23 to the triangular wave generation circuit 28, the difference between the clamp level signals at different timings is calculated, and the correction of the inverse phase relationship with the video input signal SIN is performed. Signal S28
The antiphase wave generation circuit 25 is not necessarily required as a method of generating a signal having an antiphase relationship. As an alternative method, the integrator 2
4, the polarity of the level difference signal S23 applied to the up / down counter may be increased / decreased and inverted, or the triangular wave generation circuit 28 may be increased / decreased. That is, the anti-phase wave generation circuit 25 can be deleted. Further, since the adder circuit 21 is used, the noise reduction circuit 2
2 to the triangular wave generation circuit 28, the video input signal SIN
The correction signal S28 having the opposite phase is generated by the addition circuit 2
If a subtraction circuit is used instead of 1, the level difference detection circuit 2
The signal having the same phase as the video input signal SIN may be generated in the 3-waveform generator 28.

In the dispersal signal removing circuit of the present invention, the signal holding circuit 26 is not always necessary, and the anti-phase signal S25 may be directly converted by the DAC 27. Further, from the operating principle of the present invention,
The noise reduction circuit 22 is not always necessary.

It is not always necessary to correct the video input signal SIN using the correction signal S28 described above. For example, when performing the above-mentioned correction intermittently, the switch 32 is caused to perform the above-described switching operation only at the timing of performing the correction. When the value thus obtained is continuously used until the next cycle, switch 32 is set to contact b.
It is closed to prevent the clock CLK from being applied to the signal holding circuit 26.

As described above, MUSE is used as the video input signal SIN.
Although the signal has been exemplified, the dispersal signal removing circuit of the present invention can detect the MU if the phase relationship is known even if the frequency deviation of the dispersal signal S _DSP is unknown.
Not only the BS such as the SE signal but also the CS having a large amplitude can effectively suppress the fluctuation of the clamp level due to the dispersal signal S _DSP component.

[0033]

According to the present invention, an output signal that is not affected by the dispersal signal component can be provided. Further, the dispersal signal removing circuit of the present invention can be realized with a relatively simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a dispersal signal removing circuit according to an embodiment of the present invention.

FIG. 2 is a MUSE in which a dispersal signal is inserted.
It is a figure which shows a transmission signal format.

3A and 3B are signal waveform diagrams in the dispersal signal removing circuit shown in FIG. 1, where FIG. 3A is a waveform diagram of a dispersal signal, and FIG. 3B is a waveform diagram showing a DC level shift;
(C) is a diagram showing the value with the timing of integrating the shift shown in (B), (D) is a diagram in which the polarity of the integrated value is reversed,
(E) is a waveform diagram of a correction signal having an opposite phase to the dispersal signal according to the integrated value.

FIG. 4 is a waveform diagram of a dispersal signal superimposed on a video signal.

FIG. 5 is a circuit diagram of a conventional clamp circuit.

FIG. 6 is a circuit configuration diagram of a conventional dispersal signal removal circuit.

7A and 7B are signal waveform diagrams in the dispersal signal removal circuit shown in FIG. 6, where FIG. 7A is a waveform diagram of a dispersal signal, and FIG. 7B is a waveform showing a DC level shift caused by the dispersal signal. It is a figure.

[Explanation of symbols]

1 ... Clamp circuit 11, 21 ... Amplification circuit 12 ... Capacitor 13 ... Resistor 14 ... Switch circuit 15 ... Power supply 16 ... Amplification circuit 17 ... AD converter 21 ... Addition circuit 22 ... Noise Reduction circuit 23 .. Level difference detection circuit 24 .. Integrator 25 .. Anti-phase wave generation circuit 26 .. Signal holding circuit 27 .. DAC 28 .. Triangle wave generation circuit 31 .. AND gate 32 .. Switch

Claims (1)

[Claims] 1. A signal clamp circuit which clamps a video signal including a differentiation circuit element and on which a dispersal signal is superimposed, and a difference between the clamp results at different points in the same field is calculated, and an amplitude corresponding to the difference is calculated. And a correction circuit that generates a correction signal having the same cycle as the dispersal signal, subtracts the correction signal from the dispersal signal, and applies the correction signal to the signal clamp circuit.