JPH07123207B2 - amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an amplifier.

[Prior Art] Here, a conventional example of this type of amplifier will be described with reference to the drawings.
FIG. 3 is a block diagram showing a circuit system of a conventional example.

In the figure, 1 is a buffer amplifier, 2 and 3 are drive amplifiers, SW is a switch for switching a recording head, υ _in is an input signal, and CH1 and CH2 are output terminals connected to a load such as a magnetic recording head.

The input signal υ _in is amplified by buffer amplifier 1 and the changeover switch SW
Supplies the output of the amplifier 1 to the driving amplifiers 2 and 3 in a time division manner. The output of the drive amplifier 2 is supplied to the terminal CH1 and the output of the drive amplifier 3 is supplied to the terminal CH2.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional example, (1) the switch SW is an analog switch, but generally, in the analog switch, its frequency characteristic deteriorates with respect to a signal of several MHz or more. To do.

(2) The load circuit connected to the drive amplifiers 2 and 3 is
Since the load is relatively heavy when viewed from the buffer amplifier 1, the output resistance is deteriorated due to the influence of the contact resistance of the analog switch SW connected between them in the ON state.

There was a drawback.

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, and when the amplified erasing signal is switched and supplied to two recording heads, erasing is performed by a current transiently generated with switching of the recording heads. An object of the present invention is to provide an amplifier capable of preventing a signal from being deteriorated.

[Means for Solving the Problems] In order to achieve such an object, the amplifier of the present invention comprises:
Feedback amplification means for inputting a video signal and having a feedback input end for inputting a feedback signal, amplifying the video signal input to the input end, and outputting the output signal from an output end, Amplifying the signal output from the feedback amplifying means,
First buffer amplifying means for outputting the amplified signal to the first recording head, and for amplifying the signal outputted from the feedback amplifying means and outputting the amplified signal to the second recording head. Of the second buffer amplifying means and the output end of the feedback amplifying means are connected to the input end of the first buffer amplifying means and the input end of the second buffer amplifying means by switching. In the connection switching means and the first connection switching means, when the output end of the feedback amplification means is connected to the input end of the first buffer amplification means, the first connection
The output end of the buffer amplifying means is connected to the feedback input end of the feedback amplifying means, and the output end of the feedback amplifying means is connected to the input end of the second buffer amplifying means when the second end is connected.
Second connection switching means for connecting the output terminal of the buffer amplifying means to the feedback input terminal of the feedback amplifying means.

[Operation] With the configuration as described above, the amplified erase signal is
When switching and supplying to each recording head, it becomes possible to prevent the erase signal from being deteriorated by a current which is transiently generated due to the switching of the recording heads.

EXAMPLES The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment in which the amplifier of the present invention is applied to an apparatus for magnetic recording and erasing with a plurality of heads.

In FIG. 1, Q1 to Q16 are transistors, and C1 to C14, C
f ₁ and Cf ₂ are capacitors, R1 to R40, R _f1 and R _f2 are resistors, and SW1 to
SW4 is an analog switch, D1 to D4 are diodes, and υ ₁ to
υ ₄ is an input signal, CH1 and CH2 are magnetic heads H1 as a load
This is the terminal to which H2 is connected.

In this embodiment, the input signal υ ₁ is connected to the base of the transistor Q1 via the capacitor C1 and the resistance R1 and
Connect to R2. The other end of the resistor R1 is connected to the constant voltage power supply Vcc, and the other end of the resistor R2 is grounded. The collector of the transistor Q1 is connected to the constant voltage power supply Vcc, the emitter of the transistor Q1 is connected to the resistor R10 via the resistor R3 and the capacitor C4, and the other end of the resistor R3 is grounded. As a result, the signal υ ₁ passes through the buffer amplifier consisting of the transistor Q1 and the resistors R1, R2, R3, and the emitter of the transistor Q1 changes to
It is output to the resistor R10 via C4. Similarly, the signal υ ₂ is
The signal is output from the emitter of the transistor Q2 to the resistor R11 via the capacitor C5 through the capacitor Q2, the buffer amplifier including the transistor Q2 and the resistors R4, R5, and R6. Signal υ ₃
In the same manner, the signal also passes through the buffer amplifier formed by the transistor Q3 and the resistors R7, R8, and R9, and is output from the emitter of the transistor Q3 to the resistor R12 via the capacitor C6. These 3
The other ends of the two output resistors R10, R11 and R12 are connected, and further connected to the emitter of the transistor Q4 and the resistor R14, respectively, and the other end of the resistor R14 is grounded. Transistor Q
The collector of 4 is the resistance R13 and H of analog switch SW1.
Side terminal and the L side terminal of analog switch SW4,
The other end of the resistor R13 is connected to the constant voltage power supply Vcc. Further, the base of the transistor Q4 is connected to the switching terminal of the analog switch SW2 and the resistor R _f1 , and the other end of the resistor R _f1 is grounded via the capacitor C _{f 1} .

Next, the switching terminal of analog switch SW1 is transistor Q5.
Connected to the base of. The collector of the transistor Q5 is connected to the constant voltage power supply Vcc, and the emitter thereof is also connected to the base of the transistor Q7 and the resistor R15 via the diodes D1 and D2, and the other end of the resistor R15 is grounded.

The collector of the transistor Q6 is connected to the constant voltage power supply Vcc, and the collector of the transistor Q7 is grounded.

The emitter of transistor Q6 is connected to resistor R17
The other end of 17 is connected to resistors R16 and R18 and capacitors C7 and C8, respectively. The other end of the resistor R18 is connected to the emitter of the transistor Q7. Further, the resistor R16 is a feedback resistor, and the other ends thereof are connected to the H side terminal of the analog switch SW2 and the L side terminal of SW3, respectively.

The transistor Q4 and the amplifier circuits of Q5 to Q7 described above constitute a feedback amplifier incorporating the analog switches SW1 and SW2.

The other end of the above-mentioned capacitor C7 is connected to the base of the transistor Q8 and at the same time connected to the resistors R19 and R20. Resistor R19
The other end of is connected to a constant voltage power supply Vcc. Also the capacitor C
The other end of 8 is connected to the base of the transistor Q9 and simultaneously connected to the resistors R21 and R22. The other end of R22 is grounded. The other ends of the resistors R20 and R21 are connected to each other, and the connection point is connected to the collectors of the transistors Q8 and Q9. The transistors Q8 and Q9 form a load drive amplifier.
Then, it is connected to the supply terminal CH1 of the load H1 via the capacitor C9.

Next, the input signal υ ₄ is connected to the base of the transistor Q10 via the capacitor C10, and the transistor Q10 is connected to the resistor R by the circuit corresponding to the transistors Q1, Q2 and Q3 described above.
A buffer amplifier consisting of 26, R25 and R27 is constructed.

The emitter of the transistor Q10 is connected to the emitter of the transistor Q11 via the resistor R28 via the capacitor C11, and is also grounded via the resistor R29. This transistor Q
11 corresponds to the amplifier circuit of the transistor Q4 described above,
The collector is connected to the resistor R30, and is also connected to the H side terminal of the analog switch SW4 and the L side terminal of SW1, respectively, and the other end of the resistor R30 is connected to the constant voltage power supply Vcc. Further, its base is grounded via a resistor R _f2 and a capacitor C _f2 and is connected to a switching terminal of an analog switch SW3.

The switching terminal of the analog switch SW4 is connected to the base of the transistor Q12. Where transistors Q12 and Q14, Q
The amplifier circuit of 13 corresponds to the amplifier circuit of the transistors Q5, Q6, and Q7 described above, and R32 corresponding to its feedback resistor R16 also serves as a feedback resistor as the analog switch SW3.
Is connected to the H side terminal of SW2 and the L side terminal of SW2. As a result, the amplification circuits of the transistors Q11 and Q12 to Q14 form a feedback amplifier incorporating the analog switches SW4 and SW3, like the amplification circuits of the transistors Q4 and Q5 to Q7 described above.

Further, C12 and C13 corresponding to the capacitors C7 and C8 are coupled to the drive amplifier formed by the transistors Q15 and Q16. Further, the output of the drive amplifier is connected to the supply terminal CH2 of the load H2 via the capacitor C14.

Next, the operation of the circuit of the embodiment shown in FIG. 1 will be described.

The three input signals υ ₁ , υ ₂ and υ ₃ pass through a buffer amplifier consisting of transistors Q1, Q2 and Q3, respectively, and then are added in the form of current to the emitter of transistor Q4 through resistors R10, R11 and R12. Is entered.

Where capacitors C4, C5, C6 and Cf ₁ are
_It is assumed that ₁ , ₁ , ₂ and ₃ are sufficiently small so that their impedances are small.

1) First, the case where all the analog switches SW1 to SW4 are connected to the H side terminals by the switching control signal will be described. This state is called "A".

The collector of the transistor Q4 is connected to the base of the transistor Q5, and the base of the transistor Q4 is connected to the resistor R16. At this time, transistors Q4, Q5, Q6 and Q7
Constitutes a feedback amplifier having a feedback resistor R16.

In this amplifier, the amplification gain G1 for the input signal υ ₁
Is defined by the resistors R10, R13, R16, R _f1 , the input impedance γ _ib on the emitter side of the grounded-base transistor Q4, the input impedance γ _ie on the base side of the transistor Q4, and the contact resistance γ _s2 of the analog switch SW2 in the ON state. Almost determined, and its value is as follows.

Where γ _ie = h _fe × (R10R11R12R14) γ _ie R _f1 is the combined resistance value of γ _ie and R _f1 connected in parallel, h
_fe is the current amplification of transistor Q4, R10R11R12R14
Represents a combined resistance value in which resistors R10, R11, R12 and R14 are connected in parallel.

Where R1 is such that γ _ie ≫R8, R16≫γ _s2 , R13≫γ _ib
Properly choosing the values of 0, R11, R12, R13, R14, R16 and R _f1 , Becomes Amplification gain G2 for the input signal upsilon ₂ in a similar manner,
The amplification gain G3 for the input signal υ ₃ is Becomes

As described above, by setting the input impedance on the emitter side of the transistor Q4 to be small, the amplification gain G1, G2
And G3 can be set to a relatively wide range independent by changing the respective values of the resistors R10, R11, R12 and R _f1.

Further, the frequency characteristics become flat in a predetermined range by configuring the feedback amplifier.

Further, the contact resistance of the analog switch SW2 in the ON state generally differs depending on the frequency, but according to this configuration, it is difficult to be affected by the contact resistance, and the frequency characteristic of the output of the feedback amplifier is not adversely affected.

The output of the feedback amplifier constructed based on the transistors Q4, Q5, Q6 and Q7 passes through capacitors C7 and C8,
The current is amplified by being guided to the drive amplification stage composed of the transistors Q8 and Q9, and output from the capacitor C9.

On the other hand, the transistors Q11, Q12, Q13 and Q14 similarly form a feedback amplifier. Here, each resistance value is R29 ＝ R14, R30 ＝ R1
If 3, R31 = R15, R32 = R16, R33 = R18, R34 = R17, the operating point of this amplifier is equal to the amplifier composed of transistors Q4, Q5, Q6 and Q7.
The base potential and collector potential of Q11 are equal. The output of the feedback amplifier composed of the transistors Q11 to Q14 is connected to the drive amplifier composed of the transistors Q15 and Q16, but when the input signal υ ₄ is no signal, nothing is output to the load H2.

In this state, when an input signal υ ₄ (for example, an erase signal) is input, the signal υ ₄ is voltage-amplified by, for example, an amplification gain G4 represented by the following equation, and then the driving amplifier composed of the transistors Q15 and Q16 is used. Flows through to the load H2.

2) Next, a case will be described where the analog switches SW1 to SW4 are all connected to the L-side terminal by the switching control signal. This state is hereinafter referred to as "B".

In this case, the collector of transistor Q4 is transistor Q12.
The base of transistor Q4 is connected to resistor R3
Connected with 2. Therefore, the transistors Q4, Q12, Q13 and Q14 form a basic feedback amplifier. The collector of the transistor Q11 is connected to the base of the transistor Q5, and the base of the transistor Q11 is connected to the resistor R16.

Therefore, the transistors Q11, Q5, Q6 and Q7 form the basic feedback amplifier.

In this case, the three input signals υ ₁ , υ ₂ and υ ₃ are summed at the input side of the emitter of transistor Q4 and then fed back by the feedback amplifier, transistors Q15 and Q16, which are based on transistors Q4, Q12, Q13 and Q14. By means of the configured drive amplifier, it is output to the load H2 via the capacitor C14, and the input signal υ ₄ is likewise output to the load H1 via the capacitor C9. When the input signal υ ₄ is no signal, nothing is output to the load H1. At this time, R13 = R30, R14 = R29, R15 = R31, R16 = R32, R17 = R34, R18 =
R33, R19 = R38, R20 = R37, R21 = R36, R22 = R35, R23 = R40, R
If 24 = R39, C7 = C13, C8 = C12, C9 = C14, the load H2 outputs exactly the same current as that flowing to the load H1 in the above-mentioned state "A". Further, in the state "A", the load H1 outputs exactly the same current as that flowing to the load H2.

In state "A" and state "B", transistors Q4 and Q1
The biases of 1 are exactly the same. Therefore, even if the state is switched from the state "A" to the state "B" or from the state "B" to the state "A" momentarily, there is no change in the bias.
No transient current flows to 1 or H2 due to switch change.

3) Next, the case where the analog switches SW1 and SW2 are connected to the L side terminal by the switching control signal and the SW3 and SW4 are connected to the H side terminal by the switching control signal will be described. This state will be referred to as "C" hereinafter.

At this time, the collector of transistor Q11 is
Connected to the base of 5 and the base of transistor Q12. The base of the transistor Q11 is connected to the resistor R32.

In this case, a feedback amplifier composed of transistors Q11, Q12, Q13 and Q14 is formed, and transistor Q1
A buffer amplifier composed of transistors Q5, Q6 and Q7 is connected to the output of 1.

Although the load on the grounded-base amplifier of the transistor Q11 is increased, the amplification gain of the transistor Q11 hardly changes because it forms a feedback path composed of the transistors Q12, Q13, and Q14. Therefore, the same current as the state "B" is output to the load H2. On the other hand, on the side of the load H2, the same signal as the signal supplied to the base of the transistor Q12 is supplied to the base of the transistor Q5, and thus a current substantially the same as that of the load H2 is output.

As described above, in the state "C", the same output current as in the state "A" or the state "B" can be obtained even when the currents are simultaneously applied to the loads H1 and H2.

Next, FIGS. 2A to 2C are block diagrams respectively corresponding to the three states "A", "B" and "C" in the above-described embodiment.

In the figure, a is a differential amplifier composed of the transistor Q4 in FIG. 1, and b is also the transistor in FIG.
A buffer amplifier composed of Q5, Q6 and Q7, c is a differential amplifier composed of the transistor Q11 in FIG. 1,
Similarly, d is the transistor Q12, Q13 and Q in FIG.
It is a buffer amplifier composed of 14.

In FIG. 2A, the input υ ₀₁ is output to the terminal CH1 via the feedback amplifier in which the output of the buffer amplifier b is fed back to the differential amplifier a, and the input υ ₀₂ is output to the differential amplifier c and the output of the buffer amplifier d. The state of being output to the terminal CH2 via the fed back feedback amplifier is shown.

In FIG. 2B, the input υ ₀₁ is output to the terminal CH2 via the feedback amplifier to which the output of the buffer amplifier d is fed back to the differential amplifier a, and the input υ ₀₂ is fed back to the differential amplifier c and the output of the buffer amplifier b. It shows the state of being output to the terminal CH1 via the feedback amplifier.

In FIG. 2C, the input υ ₀₂ is output to the terminal CH2 via the feedback amplifier to which the output of the buffer amplifier d is fed back to the differential amplifier c, and the output of the differential amplifier c is connected to the terminal via the buffer amplifier b. It shows the status output to CH1.

The operation of the magnetic recording device in each state will be described below. When a video signal is input as the input υ ₀₁ in FIG. 2 and no input signal is supplied to the input υ ₀₂ , the video signal is recorded by the head H1 in the state “A” and the state “B” is input. Is recorded by the head H2. If the state "A" and the state "B" are switched every 1/60 seconds, the first video signal
The field may be recorded by the head H1 and the second field may be recorded by the head H2.

If an erasing signal is input as input υ ₀₂ and no input signal is supplied to input υ ₀₁ , the status is “A”.
In the state "B", erasing is performed, in the state "B", erasing is performed by the head H1, and in the state "C", erasing is performed by the heads H1 and H2 at the same time.

In the embodiment as described above, particularly when the input video signal υ ₀₁ is switched and output to the head H1 and the head H2, the characteristics of the video signal supplied to the head are not deteriorated and the video signal can be recorded well. it can.

[Effects of the Invention] As described above, according to the present invention, when the amplified erase signal is switched and supplied to the two recording heads, it transiently occurs with the switching of the recording heads. It is possible to provide an amplifier capable of preventing the erase signal from being deteriorated by the current.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment according to the present invention, FIGS. 2A, 2B and 2C are block diagrams of a circuit system corresponding to the states in the circuit shown in FIG. 1, and FIG. It is a block diagram showing an example circuit system. Q1 to Q16 …… Transistor, C1 to C14, Cf ₁ , Cf ₂ …… Capacitor, R1 to R40, Rf ₁ , Rf ₂ …… Resistor, SW1 to SW4 …… Analog switch, D1 to D4 …… Diode, υ ₁ ~ Υ ₄ , υ
₀₁ , υ ₀₂ …… Input signal, CH1, CH2 …… Load, Vcc …… Constant voltage power supply, a, c …… Differential amplifier, b, d …… Buffer amplifier, a ₀ ….
… Buffer amplifier, b ₀ , c ₀ …… Drive amplifier, SWa …… Switch, Ca …… Capacitor, υ _in …… Input signal, 1 …… Buffer amplifier, 2,3 …… Drive amplifier.

Claims (1)

[Claims] 1. An amplifier for inputting an erase signal and a feedback input terminal for inputting a feedback signal, for amplifying an erase signal input to the input terminal and outputting the amplified signal from an output terminal. Feedback amplification means, first buffer amplification means for amplifying the signal output from the feedback amplification means and outputting the amplified signal to the first recording head, and signal output from the feedback amplification means Second buffer amplifying means for amplifying the signal and outputting the amplified signal to the second recording head; an output end of the feedback amplifying means and an input end of the first buffer amplifying means and a second buffer. A first connection switching means for switching and connecting to an input end of the amplifying means; and in the first connection switching means, an output end of the feedback amplifying means is an input end of the first buffer amplifying means. If connected to the first The output end of the buffer amplification means is connected to the feedback input end of the feedback amplification means, and the second buffer is connected when the output end of the feedback amplification means is connected to the input end of the second buffer amplification means. An amplifier comprising: a second connection switching means for connecting the output end of the amplifying means to the feedback input end of the feedback amplifying means.