JPS62272709A - Amplifier - Google Patents

Abstract

PURPOSE:To reduce the adverse effect on the output characteristic due to the presence of a switch by forming a switch in the inside of a feedback amplifier with respect to a load. CONSTITUTION:An amplifier comprising a transistor (TR) Q4 and TRs Q5-Q7 constitute a feedback amplifier together with analog switches SW1, SW2 incorporated inside. An amplifier comprising TRs Q11 and Q12-Q14 constitute a feedback amplifier also together with analog switches SW4, SW3 incorporated inside. Through the constitution above, the feedback amplifier is immune to the effect of the contact resistance of the analog switches and no adverse effect is given onto the frequency characteristic of the output of the feedback amplifiers.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an amplifier, and particularly to an amplifier in a system that outputs Daichi No. 8 through a switch.

[Conventional technology] Here, a conventional example of this type of amplifier will be explained with reference to the drawings.

FIG. 3 is a block diagram showing a conventional circuit system.

In the figure, 1 is a buffer amplifier, 2 and 3 are drive amplifiers, SW
is the recording head switching switch, υ1n is the input signal, C
111 and CH2 are output terminals connected to a load such as a magnetic recording head.

The input signal υIn is amplified by the buffer amplifier 1 and supplied to the switching signal, and the output of the drive amplifier 3 is supplied to the terminal C112.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional example, (1) the switch SW is an analog switch, or in general, in an analog switch, its frequency characteristics are low for a signal of several Mllz or more. deteriorates.

(2) The load circuit connected to drive amplifiers 2 and 3 is
Since the load is relatively heavy when viewed from the buffer amplifier 1, the output characteristics deteriorate due to the influence of the contact resistance in the on state of the analog switch Sw connected therebetween.

There was a drawback.

Therefore, the purpose of the present invention is to (1) prevent the deterioration of the frequency characteristics of the output No. The purpose is to prevent properties from deteriorating.

Means for Solving Problem E] To achieve these objects, the present invention configures a feedback amplifier and incorporates a switch into its feedback loop.

That is, an amplifying means for amplifying an input signal, a buffer amplifying means for amplifying the output of the amplifying means via a switch, a feedback means for taking out a bias from the buffer amplifying means to be fed back to the amplifying means, and a bias taken out from the feedback means. The device is characterized in that it includes means for feeding back the signal to the amplifying means via a switch.

[Function] Even if the configuration as described above allows the output of the signal to the load to be cut off using a switch, since the switch for the load is formed inside the feedback amplifier,
The adverse effect on the output characteristics due to the presence of the switch can be reduced.

[Example] The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment in which the amplifier of the present invention is applied to a device that performs magnetic recording and erasing using a plurality of heads.

In FIG. 1, Q1 to Q16 are transistors, C1 to
CI4. Cf, , Cf2 are capacitors, old ~ R40, R
1+, Rr2 is a resistor, 5WI-SW4 is an analog switch, DI-D4 is a diode, V1-V4 is an input signal, C11l, CH2 is an old magnetic/magnetic head as a load, H
2 is the terminal to be connected.

In this embodiment, the input signal tji is connected to the base of the transistor Ql via a capacitor C1 and to resistors R1 and R2. The other end of the resistor R1 is connected to the constant voltage power supply Vcc, and the other end of the resistor R2 is grounded. The collector of transistor 01 is connected to constant voltage power supply Vcc, the emitter of transistor Q1 is connected to resistor 0 via resistor R3 and capacitor C4, and the other end of resistor R3 is grounded. This causes the signal v1 to be transferred to the transistor Q
l, resistor, through the buffer amplifier by R2, R3,
It is output from the emitter of transistor Q1 to resistor 0 via capacitor C4. Similarly, the signal υ2 is passed through the capacitor C2 to the transistor Q2, the resistors R4, R5, and R
6, and is output from the emitter of transistor Q2 to resistor R11 via capacitor C5. Signal v3 similarly passes through a buffer amplifier made up of transistor Q3 and resistors R7, R8, and R9, and is output from the emitter of transistor 03 to resistor 2 via capacitor C6. These three output resistors 0. The other ends of R11 and RI2 are connected, and further connected to the transistor Q4.
and the resistor R14, respectively, and the other end of the resistor R14 is grounded. The collector of the transistor 04 is connected to the resistor R13, the H side terminal of the analog switch SWI, and the L side terminal of the analog switch SW4, and the other end of the resistor 3 is connected to the constant voltage power supply Vcc. Further, the base of the transistor Q4 is connected to the switching terminal of the analog switch SW2 and the resistor 1 (ft), and the other end of the resistor Rfl is grounded via the capacitor Cf.

Next, the switching terminal of the analog switch SWI is connected to the base of the transistor Q5. The collector of the transistor Q5 is connected to the constant voltage power supply Vcc, and the emitter is also connected to the constant voltage power supply Vcc.
Base of transistor Q6 and tie auto DI, D
The base of the transistor q7 and the resistor R15 are connected through the transistor 2, and the other end of the resistor R15 is grounded and connected to the base of the transistor q7 and the resistor R15.
The collector of transistor Q6 is connected to constant voltage power supply νCC, and the collector of transistor Q7 is grounded.

The emitter of the I transistor q6 is connected to the resistor port 7,
The other end of the resistor RI7 is the resistor port 6. Old 8, capacitor C7,
08 respectively. The other end of resistance port 8 is connected to the emitter of transistor Q7. Furthermore, the resistor port 6 is a feedback resistor, and the other end is connected to the H side terminal of the analog switch 5112 and the L side terminal of SW3.

The transistor Q4 and the amplifier circuits 05 to Q7 described above constitute a feedback amplifier incorporating analog switches Swl and 51112.

The other end of the capacitor C7 mentioned above is connected to the base of the transistor Q8 and at the same time to the resistor R19,820. The other end of resistor R19 is connected to constant voltage power supply Vcc. Further, the other end of the capacitor C8 is connected to the base of the transistor q9, and simultaneously connected to the resistors R21 and R22. The other end of R22 is grounded. Resistors R20 and 82 mentioned above
1 is connected, and the connection point is connected to the collectors of transistors Q8 and Q9. These transistors q8 and Q9 constitute a load driving amplifier. It is then connected to the load supply terminal CHI via a capacitor C9.

Next, the input signal υ4 is connected to the base of the transistor QIO via the capacitor CIO, and the transistor QIO constitutes a buffer amplifier with the resistors R2fi, R25 and R27 by a circuit corresponding to the above-mentioned transistors Q1, Q2 and 03.

The emitter of the transistor QIO is connected to the emitter of the transistor Qll via a resistor R211 via a capacitor C11, and is grounded via a resistor R29.

This transistor Qll corresponds to the amplifier circuit of the transistor Q4 described above, and its collector is connected to the resistor R30, and is also connected to the H-side terminal of the analog switch SW4 and the L-side terminal of SWI, and is also connected to the resistor R30.
The other end of 30 is connected to constant voltage power supply Vcc. Furthermore, its base is resistor Rr2. It is grounded through the capacitor Cf2 and connected to the switching terminal of the analog switch SW3.

The switching terminal of analog switch 5114 is transistor Q.
Connected to 12 bases. Here transistor Q12
The amplifier circuit of Q14 and Q10 is the transistor Q5 and Q6. It corresponds to the amplifier circuit of Q7, and R32, which corresponds to the feedback resistor RI6, is similarly connected as a feedback resistor to the H-side terminal of analog switch 5VI3 and the L-side terminal of SW2. Therefore, the transistor Qll and the amplifier circuit of Q12 to Q14 constitute a feedback amplifier incorporating the analog switches SW4 and SW3, similar to the amplifier circuit of the transistors q4 and 05 to q7 described above.

Furthermore, C12 corresponding to capacitors C7 and C8
, Cf3 are transistors Q15. Q16. Furthermore, the output of the drive amplifier is connected to the load supply terminal C11 via the capacitor C14.
Connected to 2.

Next, the operation of the circuit of the embodiment shown in FIG. 1 will be explained.

Three input signals υ1. After passing through a buffer amplifier consisting of transistors Ql, Q2 and Q3, respectively, υ2 and υ3 are added in the form of current to the emitter of transistor q4 through resistors RIG, R11 and R12, and inputted.

Here, capacitors C4, C5, C6 and Cf are:
It is assumed that the impedance is selected to be a small value so that the input signals vl, υ2, and υ3 can pass through sufficiently.

1) First, a case will be described in which the analog switches SWI to Sw4 are all connected to the H side terminal by a switching control signal. This state is called "A".

The collector of transistor Q4 is connected to the base of transistor q5, and the base of transistor 04 is connected to resistor R16.
It is connected to the. At this time, transistors Q4, Q
5, Q6 and Q7 constitute a feedback amplifier with feedback resistor 6.

In this amplifier, the amplification gain G for the input signal υ1
l are resistors RIG, R13, RI6 . Rr+ and the input impedance γ11.1 on the emitter side of the common-base transistor Q4 to the human input impedance γla+ on the base side of the run transistor It becomes like the expression.

However, γ, e-11. IIX (RIO spear R11/'
R12//Old 4) γre//Rt+ is the combined resistance value of γ18 and Rfl connected in parallel, hfa is the transistor Q4
Current amplification factor of +110//R11iR12//R14
represents a combined resistance value in which resistors RIO, old 1, RI2 and R14 are connected in parallel.

Here, γIe>R8, R16>γs2, RI3>
γ1ゎ and t, so R10, R1+. R12, R1
3, old 4. If the values of R16 and Rfl are chosen appropriately, the following results. Similarly, the amplification gain G2 applied to the input signal v2
, the amplification gain G3 for the input signal υ3 is as follows.

As described above, by setting the human input impedance on the emitter side of the run transistor 04 to a small value, the amplification gains Gl, G2 and G3 are respectively set to 0. Old 1, R
By changing the values of 12 and L+, they can be set independently over a relatively wide range.

Furthermore, by configuring a feedback amplifier, the frequency characteristics also become flat within a predetermined range.

In addition, the contact resistance of the analog switch SW2 in the on state generally varies depending on the frequency, and this configuration makes it less susceptible to the influence of the contact resistance and does not adversely affect the frequency characteristics of the output of the feedback amplifier. .

Transistor Q4. (The output of the feedback amplifier configured based on 15, 06, and 07 is led through capacitors C7 and C8 to the drive amplifier stage consisting of transistors Q8 and Q9, where it is current-amplified, and output from capacitor C9. be done.

On the other hand, transistor Q11. Q]2. Q13 and 01
4 similarly constitutes a feedback amplifier. Here, each resistance value is R
29=RI4. R30=RI3. R31=R15,R3
2=R16, R33=old 8. If R34=RI7, then the operating point of this amplifier is the transistor Q4. Q5. Q
8 and G7,]
- The base potential and collector potential of the run transistors Q4 and Qll are equal to each other. Transistor Qll~Q
The output of the feedback amplifier consisting of transistor Q15
If the force signal v4 from Q10 is no signal, nothing is output to the load H2.

In this state, when an input signal υ4 (for example, an erasure signal) is input, the signal v4 has an amplification gain of 6 expressed by the following equation.
After the fourth voltage is amplified, it passes through the drive amplifier consisting of transistors QI5 and Q10 to the load +12
flows to

2) Next, a case will be described in which the analog switches 5WI-5W4 are connected to the upper terminal without depending on the switching control signal. This state will be referred to as "B" below.

In this case, the collector of transistor Q4 is
The base of transistor q4 is connected to the base of transistor q4, and the base of transistor q4 is connected to resistor R32. Therefore, transistor Q4.
Q12. Q13 and Q10 form the basic feedback amplifier. Further, the collector of the transistor Qll is connected to the base of the transistor q5, and the base of the transistor Qll is connected to the resistor 6.

Therefore, transistors Qll, Q5 . Q6 and G7 basically constitute a feedback amplifier.

In this case, the three input signals vl, υ2 and v3 are summed at the input side of the emitter of transistor o4 and then at the input side of the emitter of transistor Q4. Q12. Q13 and R14 are the basic feedback amplifier, and the drive amplifier consisting of transistors Q15 and 6 is output to the load 112 through the re-capacitor C14, and the Jinkai No. 3 v4 is similarly output through the capacitor C9. It is output to load I11. Also, when the input signal is v4 or no signal, nothing is output to the load Ill.
J. At this time, R13=R30, R111=R29, R31 in RI5,
R16 = R32゜ Old 7 = R34, R18 = R33, R
19=R3B, R20=R37, R21=R36, R2
2=R35,1t23=R40,R24=R39,C
7=C13°C8=C12, C9=CI4, then load) 12 has load I in the above state 'AJ'.
Exactly the same current that flows through I+ is output. In addition, exactly the same current as that flowing through the state [AJ, load) 12 is outputted to the load 11''.

In state "A" and state "rB", the biases of transistor Q4 and old I are completely equal. Therefore, even if you instantaneously switch from state rAJ to state "B" or from state rB to state rA, 1, the bias will not change.
No transient current accompanying the switching of the switch flows through the load I11 or ][2.

3) Next, a case will be described in which the analog switches SWI and SW2 are connected to the L side terminal by the switching control signal, and the analog switches SW3 and SW4 are connected to the H side terminal by the switching control signal. This state will be referred to as r□ below.

At this time, the collector of transistor Qll is connected to the base of transistor Q5 and the base of transistor 0]2. Furthermore, the base of the transistor Qll is connected to the resistor R32.
connected to.

In this case, transistors Q11.012. A feedback amplifier consisting of R13 and 014 is formed, and further a transistor Q5.0 is connected to the output of the transistor Qll.
6 and R7 are connected to each other.

Although the load on the base-grounded amplifier of the transistor Qll increases, its amplification gain hardly changes because a feedback path is formed by the transistors Q12, Q10, and Q10. Therefore, the state rB and current are output to the load 1 (2).On the other hand, on the load I11 side, the same signal as that supplied to the base of the transistor Q12 is supplied to the base of the transistor 05. Therefore, almost the same current as the load 112 is output.

In this way, in state "C", loads 111 and 11
Even if a current is simultaneously applied to both 2 and 2, it is possible to obtain the same output current as in state ``A'' or ``state rB''.

Next, FIGS. 2A to 2C are block diagrams corresponding to the three states "A", state rB, and state "c" of the above-described embodiment, respectively.

In the figure, a is a differential amplifier constituted by the transistor Q4 in FIG. 1, b is a differential amplifier constituted by the transistor Q5. a buffer amplifier consisting of Q6 and q7;
C is a differential amplifier composed of transistor 011 in FIG. 1, and d is transistor Q, also in FIG.
12. This is a buffer amplifier composed of Q13 and Q10.

Figure 2 A is human power V. 1 is output to the terminal C111 via the feedback amplifier in which the output of the buffer amplifier S is fed back to the differential amplifier a, and the human power V is output. 2 shows a state in which the output of the buffer amplifier d is fed back to the differential amplifier C and outputted to the terminal C112 via the feedback amplifier.

Figure 2B shows human power V. 1 or the output of the buffer amplifier d is fed back to the differential amplifier a and is output to the terminal C112 via the feedback amplifier, and the human power V is output. 2 shows a state in which the output of the buffer amplifier S is fed back to the differential amplifier C and is output to the terminal C111 via the feedback amplifier.

Figure 2 C is human power V. 2, the output of the buffer amplifier d is fed back to the differential amplifier C, and is output to the terminal C1 (2) via the feedback amplifier, and the output of the differential amplifier C is output to the terminal C111 via the buffer amplifier. It shows the condition.

Below, the operation of the magnetic recording device in each state will be explained. Human power υ in Figure 2. If a video signal is input manually as 1, and no input signal is supplied to the input signal υo2, in the above-mentioned state "A" the video signal is recorded by the head 112, and in state "B" the video signal is recorded by the head 112. be done. and state 'A'
'' and the state r[3J every 1760 seconds, it is possible to create a configuration in which the first field of the video signal is recorded by the head 112, and the second field is recorded by the head 112.

Also human power v0. If the erasing signal is input as , and no input signal is supplied to human power vo+, the state "
In state "A", erasing is performed by head H2, in state "B", erasing is performed by head H1, and further in state "C".
In the head 111. Erasing can be performed simultaneously using the head (2).

In particular, in the embodiments described above, the input video signal υ. 1
Even when switching between the old head and the head 112 for output, the characteristics of the video signal supplied to the head do not deteriorate, and the video signal can be recorded satisfactorily.

[Effects of the Invention] As is clear from the above, even when supplying input signals to loads in a time-division manner, the deterioration of frequency characteristics and the negative effect on output characteristics due to the presence of a changeover switch can be overcome by feedback amplification. It can be absorbed and prevented.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the configuration of an embodiment according to the present invention, Fig. 2 is a block diagram of a circuit system corresponding to the state in the circuit shown in Fig. 1, and Fig. 3 is a conventional circuit diagram. FIG. 2 is a block diagram showing an example circuit system. Ql~Q16...transistor, CI A-C14, Cf,, Cf2...capacitor,
R1-R40, Rf,, Rf2...Resistance, 5WI-S
W4...Analog switch, DI-D4...Diode, v1~υ4+vO1+υ. 2...Input signal, CI, C
H2...Load, Vcc...Constant voltage power supply, a, c...Differential amplifier, b, d...Buffer amplifier, ao...Buffer amplifier, bQ +CG...Drive amplifier, SWa・...Switch, Ca...Capacitor, υTodoroki. ...Input signal, 1...Buffer amplifier, 2.3...Drive amplifier. Stuttering [Table Iguri's tatami -nail LL is exhausted ゛ D, Tsuku Fig. 3

Claims (1)

[Scope of Claims] Amplifying means for amplifying an input signal; buffer amplifying means for amplifying the output of the amplifying means via a switch; feedback means for extracting a bias from the buffer amplifying means to be fed back to the amplifying means; An amplifier comprising means for feeding back the bias taken out from the feedback means to the amplification means via a switch.