JPH0812978B2 - amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an amplifier.

[Prior Art] Here, a conventional example of a magnetic recording apparatus using this type of amplifier will be described with reference to the drawings. FIG. 3 is a block diagram showing a circuit system of a conventional example.

In the figure, υ _s is a recording signal, υ _e is an erasing signal, SWa and S
Wb is a switch, a ₀ , d ₀ , e ₀ and f ₀ are buffer amplifiers, b ₀ , c ₀ ,
g ₀ and h ₀ are drive amplifiers, R1 and R2 are resistors, and CH1 and CH2 are output terminals to which a magnetic head as a load is connected.

In FIG. 3A, the recording signal υ _s and the erase signal υ _e are switched by the switch SWa. Also, output terminals CH1 and CH2 for the dual recording / erasing head are switched SW.
Switched by b.

In FIG. 3B, the recording signals υ _s and υ _e are amplified by buffer amplifiers d ₀ and e ₀ , respectively, and then the resistors R1 and R2 are added.
Is added through. In this case, the recording signal υ _s and the erasing signal υ _e are connected to the buffer amplifier f ₀ while the adding circuit is still connected. When recording, only the recording signal υ _s is input, and when erasing, only the erasing signal υ _e is input. Further, the input signals are switched to the terminals CH1 and CH2 by the switch SWb and are supplied via the drive amplifiers g ₀ and h ₀ , respectively.

[Problems to be Solved by the Invention] However, the above-described conventional example has the following problems.

That is, in the case of FIG. 3A, (1) the frequency characteristic of the recording signal υ _s is deteriorated by passing the switch SWa.

(2) Distortion occurs due to the switch SWa.

 There was a drawback.

Further, in the case of FIG. 3B, there is a drawback that the signal-to-noise ratio of the recording signal ν _s is deteriorated due to the inclusion of noise from the input circuit of the erasing signal ν _e .

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, and when either one of the amplified video signal and the erasing signal is switched and supplied to the two recording heads, a transition is accompanied by the switching of the recording heads. An object of the present invention is to provide an amplifier capable of preventing the recorded video signal or erased signal from being deteriorated by the electric current that is generated.

[Means for Solving the Problems] In order to achieve such an object, the amplifier of the present invention has an input end for inputting a video signal and a feedback input end for inputting a feedback signal. A first feedback amplifying means for amplifying the video signal input to the input end and outputting from the output end, an input end for inputting an erase signal and a feedback input end for inputting the feedback signal Second feedback amplifying means for amplifying the erased signal input to the input end and outputting the amplified signal from the output end, and amplifying the input signal and outputting the amplified signal to the first recording head. First buffer amplifying means for outputting to the second recording head and second buffer amplifying means for amplifying the input signal and outputting the amplified signal to the second recording head.
The buffer amplifying means and the output end of the first feedback amplifying means are connected to the input end of the first buffer amplifying means and the input end of the second buffer amplifying means by switching.
First connection switching means for switching and connecting the output end of the second feedback amplification means to the input end of the first buffer amplification means and the input end of the second buffer amplification means, respectively. In the first connection switching means, the output end of the first feedback amplification means is connected to the input end of the first buffer amplification means, and the output end of the second feedback amplification means is connected to the second buffer. When connected to the input end of the amplification means,
The output end of the first buffer amplification means is connected to the feedback input end of the first feedback amplification means, and the output end of the second buffer amplification means is connected to the feedback input end of the second feedback amplification means. The output end of the first feedback amplification means is connected to the input end of the second buffer amplification means, and the output end of the second feedback amplification means is connected to the input end of the first buffer amplification means. When connected, the output end of the second buffer amplification means is connected to the feedback input end of the first feedback amplification means, and the output end of the first buffer amplification means is connected to the second feedback amplification means. And a second connection switching means for connecting to the feedback input terminal of.

[Operation] With the configuration as described above, when either one of the amplified video signal and the erase signal is switched and supplied to the two recording heads, it is transiently changed with the switching of the recording heads. It is possible to prevent the recorded video signal or erase signal from being deteriorated by the generated current.

EXAMPLES The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment in which the amplifier of the present invention is applied to an apparatus for magnetic recording and erasing with a plurality of heads.

In FIG. 1, Q1 to Q16 are transistors, and C1 to C14, C
f ₁ and Cf ₂ are capacitors, R1 to R40, R _f1 and R _f2 are resistors, and SW1 to SW
4 is an analog switch, D1 to D4 are diodes, and υ _{1 to} υ
₄ is an input signal, CH1 and CH2 are magnetic heads H1 and H2 as loads.
Is a terminal to be connected.

In this embodiment, the input signal υ ₁ is connected to the base of the transistor Q1 via the capacitor C1 and also to the resistors R1 and R2. The other end of the resistor R1 is connected to the constant voltage power supply Vcc, and the other end of the resistor R2 is grounded. The collector of the transistor Q1 is connected to the constant voltage power supply Vcc, and the emitter of the transistor Q1 is connected to the resistor R10 via the resistor R3 and the capacitor C4.
And the other end of the resistor R3 is grounded. As a result, the signal υ ₁ passes through the buffer amplifier including the transistor Q1 and the resistors R1, R2, and R3, and is output from the emitter of the transistor Q1 to the resistor R10 via the capacitor C4. Similarly the signal υ
₂ is a transistor Q2 and resistors R4 and R via a capacitor C2
The signal is output from the emitter of the transistor Q2 to the resistor R11 via the capacitor C5 through the buffer amplifier of R5. Similarly for signal υ ₃ , transistor Q3 and resistors R7 and R
The signal is output from the emitter of the transistor Q3 to the resistor R12 via the capacitor C6 through the buffer amplifiers of R8 and R9. The other ends of these three output resistors R10, R11 and R12 are connected, further connected to the emitter of the transistor Q4 and the resistor R14 respectively, and the other end of the resistor R14 is grounded. The collector of the transistor Q4 is connected to the resistor R13 and the H side terminal of the analog switch SW1 and the L side terminal of the analog switch SW4, and the other end of the resistor R13 is connected to the constant voltage power supply Vcc.
Furthermore, the base of transistor Q4 is analog switch SW2.
It is connected to the switching terminal, and the resistor R _f1, the other end of the resistor R _f1 is grounded via the capacitor Cf _1.

Next, the switching terminal of analog switch SW1 is transistor Q
Connected to the base of 5. The collector of the transistor Q5 is connected to the constant voltage power supply Vcc, and the emitter thereof is also connected to the base of the transistor Q7 and the resistor R15 via the diodes D1 and D2, and the other end of the resistor R15 is grounded.

The collector of the transistor Q6 is connected to the constant voltage power supply Vcc, and the collector of the transistor Q7 is grounded.

The emitter of the transistor Q6 is connected to the resistor R17, and the other end of the resistor R17 is connected to the resistors R16 and R18 and the capacitors C7 and C8, respectively. The other end of the resistor R18 is connected to the emitter of the transistor Q7. Furthermore, the resistor R16 is a feedback resistor,
The other end is connected to the H side terminal of the analog switch SW2 and the L side terminal of SW3, respectively.

The transistor Q4 and the amplifier circuits of Q5 to Q7 described above constitute a feedback amplifier incorporating the analog switches SW1 and SW2.

The other end of the above-mentioned capacitor C7 is connected to the base of the transistor Q8 and at the same time connected to the resistors R19 and R20. Resistance R
The other end of 19 is connected to a constant voltage power supply Vcc. The other end of the capacitor C8 is connected to the base of the transistor Q9 and at the same time connected to the resistors R21 and R22. The other end of R22 is grounded.
The other ends of the resistors R20 and R21 are connected to each other, and the connection point is connected to the collectors of the transistors Q8 and Q9. The transistors Q8 and Q9 form a load drive amplifier. And supply terminal CH1 of load H1 via capacitor C9
Connected to.

Next, the input signal υ ₄ is connected to the base of the transistor Q10 via the capacitor C10, and the transistor Q10 constitutes a buffer amplifier by the resistors R26, R25 and R27 by the circuit corresponding to the above-mentioned transistors Q1, Q2 and Q3.

The emitter of the transistor Q10 is connected to the emitter of the transistor Q11 via the resistor R28 via the capacitor C11, and is also grounded via the resistor R29. This transistor Q11 corresponds to the amplifier circuit of the transistor Q4 described above, and its collector is connected to the resistor R30, and is also connected to the H-side terminal of the analog switch SW4 and the L-side terminal of SW1, respectively, and also to the resistor R30. The other end is connected to the constant voltage power supply Vcc. Furthermore the base resistor R _f2, capacitor Cf ₂
It is grounded via and is connected to the switching terminal of the analog switch SW3.

The switching terminal of the analog switch SW4 is connected to the base of the transistor Q12. Where transistors Q12 and Q1
The amplifying circuit of 4, Q13 is the above-mentioned transistors Q5 and Q6, Q7.
R32 corresponding to the feedback resistor R16 of the analog switch S
It is connected to the H side terminal of W3 and the L side terminal of SW2. As a result, the amplification circuits of the transistors Q11 and Q12 to Q14 form a feedback amplifier incorporating the analog switches SW4 and SW3, like the amplification circuits of the transistors Q4 and Q5 to Q7 described above.

Further, C12 and C13 corresponding to the capacitors C7 and C8 are coupled to the drive amplifier formed by the transistors Q15 and Q16. Furthermore, the output of the drive amplifier is the capacitor C14.
Is connected to the supply terminal CH2 of the load H2 via.

Next, the operation of the circuit of the embodiment shown in FIG. 1 will be described.

After the three input signals υ ₁ , υ ₂ and υ ₃ pass through a buffer amplifier consisting of transistors Q1, Q2 and Q3 respectively,
It is added to the emitter of the transistor Q4 in the form of current through the resistors R10, R11 and R12 and input.

Here, it is assumed that the capacitors C4, C5, C6 and Cf ₁ are selected so that their impedances are small values so that the input signals υ ₁ , υ ₂ and υ ₃ can sufficiently pass therethrough.

1) First, the case where all the analog switches SW1 to SW4 are connected to the H side terminals by the switching control signal will be described. This state is called "A".

The collector of the transistor Q4 is connected to the base of the transistor Q5, and the base of the transistor Q4 is connected to the resistor R16. At this time, transistors Q4, Q5, Q6 and Q7
Constitutes a feedback amplifier having a feedback resistor R16.

In this amplifier, the amplification gain for the input signal υ ₁
G1 is a resistor R10, R13, R16, R _f1 and an input impedance γ _ib on the emitter side of the grounded base transistor Q4, an input impedance γ _ie on the base side of the transistor Q4, and a contact resistance γ _s2 of the analog switch SW2 in the ON state. Is determined by the following equation and its value is as follows.

Where γ _ie = h _fe × (R10R11R12R14) γ _ie R _f1 is the combined resistance value of γ _ie and R _f1 connected in parallel,
h _fe is the current amplification factor of transistor Q4, R10R11R12R1
Reference numeral 4 represents a combined resistance value in which resistors R10, R11, R12 and R14 are connected in parallel.

Here, if the values of R10, R11, R12, R13, R14, R16 and R _f1 are properly selected so that γ _ie >> R8, R16 >> γ _s2 , R13 >> γ _ib , Becomes Amplification gain G2 for the input signal upsilon ₂ in a similar manner,
The amplification gain G3 for the input signal υ ₃ is Becomes

As described above, by setting the input impedance on the emitter side of the transistor Q4 to be small, the amplification gain G1, G
2 and G3 can be independently set in a relatively wide range by changing the values of the resistors R10, R11, R12 and R _f1 , respectively.

Further, the frequency characteristics become flat in a predetermined range by configuring the feedback amplifier.

Further, the contact resistance of the analog switch SW2 in the ON state generally differs depending on the frequency.
It is less affected by the contact resistance and does not adversely affect the frequency characteristic of the output of the feedback amplifier.

The output of the feedback amplifier formed based on the transistors Q4, Q5, Q6 and Q7 passes through the capacitors C7 and C8, is guided to the drive amplification stage formed by the transistors Q8 and Q9 and is current-amplified, and the capacitor C9 Is output from.

On the other hand, the transistors Q11, Q12, Q13 and Q14 similarly form a feedback amplifier. Here, each resistance value is R29 ＝ R14, R30 ＝
If R13, R31 = R15, R32 = R16, R33 = R18, R34 = R17,
The operating point of this amplifier is transistors Q4, Q5, Q6 and Q7.
Equal to an amplifier composed of a transistor Q4
And Q11 have the same base potential and collector potential. The output of the feedback amplifier composed of the transistors Q11 to Q14 is connected to the drive amplifier composed of the transistors Q15 and Q16, but nothing is output to the load H2 when the input signal υ ₄ is no signal.

In this state, when an input signal υ ₄ (for example, an erasing signal) is input, the signal υ ₄ is, for example, an amplification gain G4 shown by the following equation.
After being voltage-amplified only, it flows to the load H2 through the driving amplifier composed of the transistors Q15 and Q16.

2) Next, the case where all the analog switches SW1 to SW4 are connected to the L side terminal by the switching control signal will be described. This state is hereinafter referred to as "B".

In this case, the collector of transistor Q4 is transistor Q1
It is connected to the base of 2 and the base of transistor Q4 is resistor R
Connected with 32. Therefore, the transistors Q4, Q12, Q13 and Q14 form a basic feedback amplifier. The collector of the transistor Q11 is connected to the base of the transistor Q5, and the base of the transistor Q11 is connected to the resistor R16. Therefore, the transistors Q11, Q5, Q6 and Q7 form the basic feedback amplifier.

In this case, the three input signals υ ₁ , υ ₂ and υ ₃ are summed at the input side of the emitter of transistor Q4 and then fed back by the feedback amplifier, transistors Q15 and Q16, which are based on transistors Q4, Q12, Q13 and Q14. By means of the configured drive amplifier, it is output to the load H2 via the capacitor C14, and the input signal υ ₄ is likewise output to the load H1 via the capacitor C9. When the input signal υ ₄ is no signal, nothing is output to the load H1. At this time, R13 = R30, R14 = R29, R15 = R31, R16 = R32, R17 = R34, R18
= R33, R19 = R38, R20 = R37, R21 = R36, R22 = R35, R23 = R4
When 0, R24 = R39, C7 = C13, C8 = C12, C9 = C14, the same current as that flowing to the load H1 in the above-mentioned state “A” is output to the load H2. Further, in the state "A", the load H1 outputs exactly the same current as that flowing to the load H2.

In state "A" and state "B", the transistor Q4 and
The biases of Q11 are exactly the same. Therefore, even if the state is switched from the state "A" to the state "B" or from the state "B" to the state "A" momentarily, there is no change in the bias.
No transient current flows to 1 or H2 due to switch change.

3) Next, the case where the analog switches SW1 and SW2 are connected to the L side terminal by the switching control signal and the SW3 and SW4 are connected to the H side terminal by the switching control signal will be described. This state will be referred to as "C" hereinafter.

At this time, the collector of the transistor Q11 is connected to the bases of the transistor Q5 and the transistor Q12. The base of the transistor Q11 is connected to the resistor R32.

In this case, a feedback amplifier consisting of transistors Q11, Q12, Q13 and Q14 is formed, and
A buffer amplifier composed of transistors Q5, Q6 and Q7 is connected to the output of Q11.

Although the load on the grounded-base amplifier of the transistor Q11 is increased, the amplification gain of the transistor Q11 hardly changes because it forms a feedback path composed of the transistors Q12, Q13, and Q14. Therefore, the same current as the state "B" is output to the load H2. On the other hand, on the load H1 side, the same signal as the signal supplied to the base of the transistor Q12 is supplied to the base of the transistor Q5, and thus a current substantially the same as that of the load H2 is output.

As described above, in the state "C", even if the currents are simultaneously applied to the loads H1 and H2, the state "A" or the state "B" is generated.
The same output current as can be obtained.

Next, FIGS. 2A to 2C are block diagrams respectively corresponding to the three states "A", "B" and "C" in the above-described embodiment.

In the figure, a is a differential amplifier composed of the transistor Q4 in FIG. 1, b is a buffer amplifier composed of the transistors Q5, Q6 and Q7 in FIG. 1, and c is a first amplifier.
A differential amplifier composed of the transistor Q11 in the figure, and d is a buffer amplifier composed of the transistors Q12, Q13 and Q14 in FIG.

In FIG. 2A, the input υ ₀₁ is the differential amplifier a and the buffer amplifier b.
The output of is output to the terminal CH1 via the fed back feedback amplifier, and the input υ ₀₂ is output to the terminal CH2 via the feedback amplifier to which the output of the buffer amplifier d is fed back to the differential amplifier c. There is.

In FIG. 2B, the input υ ₀₁ is output to the terminal CH2 via the feedback amplifier to which the output of the buffer amplifier d is fed back to the differential amplifier a, and the input υ ₀₂ is fed back to the differential amplifier c and the output of the buffer amplifier b. It shows the state of being output to the terminal CH1 via the feedback amplifier.

In FIG. 2C, the input υ ₀₂ is output to the terminal CH2 via the feedback amplifier to which the output of the buffer amplifier d is fed back to the differential amplifier c, and the output of the differential amplifier c is connected to the terminal via the buffer amplifier b. It shows the status output to CH1.

The operation of the magnetic recording device in each state will be described below. When a video signal is input as the input υ ₀₁ in FIG. 2 and no input signal is supplied to the input υ ₀₂ , the video signal is recorded by the head H1 in the state “A” and the state “B” is input. Is recorded by the head H2. By switching the state "A" and the state "B" every 1/60 seconds, the first field of the video signal can be recorded by the head H1 and the second field can be recorded by the head H2.

Further, when an erasing signal is input as the input υ ₀₂ and no input signal is supplied to the input υ ₀₁ , erasing by the head H2 in the state “A” and erasing by the head H1 in the state “B” are performed. Further, in the state "C", the head H1 and the head H2 can simultaneously erase.

In the configuration of the embodiment as shown in FIG. 1, the switch
SW1 and switch SW4 play a role of selecting one of the two input signals and a function of supplying each input signal to each head in a time division manner.
Through only the switch SW4, two input signals can be supplied to each head only when desired.

Particularly when two heads are shared for recording and erasing, recording and erasing can be performed by each head at a desired timing, which is extremely useful.

[Effects of the Invention] As described above, according to the present invention, when either the amplified video signal or the erase signal is switched and supplied to the two recording heads, the recording heads are switched. It is possible to provide an amplifier capable of preventing the recorded video signal or erased signal from being deteriorated by a current which is transiently generated due to the above.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment according to the present invention, FIGS. 2A, 2B and 2C are block diagrams of a circuit system corresponding to the states in the circuit shown in FIG. 1, FIG. 3A and FIG. B is a block diagram showing a circuit system of a conventional example. Q1 to Q16 …… Transistor, C1 to C14, Cf ₁ , Cf ₂ …… Capacitor, R1 to R40, R _f1 , RF ₂ …… Resistance, SW1 to SW4 …… Analog switch, D1 to D4 …… Diode, υ ₁ ~ Υ ₄ , υ ₀₁ , υ ₀₂ …… Input signal, CH1, CH2 …… Load, Vcc …… Constant voltage power supply, a, c …… Differential amplifier, b, d …… Buffer amplifier, a ₀ …… Buffer Amplifier, b ₀ , c ₀ ...... Drive amplifier, SWa ...... Switch, Ca _{・ ・ ・} Capacitor, υ _{s ・ ・ ・} Record signal, υ _{e ・ ・ ・} Erase signal, SWa, SWb …… Switch, a ₀ , d ₀ , e ₀ , f ₀ ...... buffer amplifier, b ₀ , c ₀ , g ₀ , h ₀ ...... driving amplifier.

Claims (1)

[Claims] 1. An input terminal for inputting a video signal and a feedback input terminal for inputting a feedback signal, wherein the video signal input to the input terminal is amplified and output from an output terminal. It has a first feedback amplification means, an input terminal for inputting an erasing signal and a feedback input terminal for inputting a feedback signal, amplifies the erasing signal input to the input terminal, and outputs from the output terminal. Second feedback amplification means for amplifying the input signal, first buffer amplification means for outputting the amplified signal to the first recording head, and amplifying the input signal, Second buffer amplification means for outputting the amplified signal to the second recording head, and an output end of the first feedback amplification means and an input end of the first buffer amplification means and a second buffer amplification means. The input terminals of the means are respectively switched and connected, and the second terminal The output end of the feedback amplifying means of the first buffer amplifying means and the second end of the feedback amplifying means of the first buffer amplifying means.
First connection switching means for switching and connecting to the input ends of the buffer amplification means, and in the first connection switching means, the output end of the first feedback amplification means is the first buffer. When the output end of the second feedback amplifying means is connected to the input end of the amplifying means and the input end of the second buffer amplifying means, the output end of the first buffer amplifying means is connected. The output of the first feedback amplifying means is connected to the feedback input terminal of the first feedback amplifying means and the output terminal of the second buffer amplifying means is connected to the feedback input terminal of the second feedback amplifying means. The second buffer if the end is connected to the input end of the second buffer amplification means and the output end of the second feedback amplification means is connected to the input end of the first buffer amplification means. The output end of the amplification means is the feedback input end of the first feedback amplification means. And a second connection switching means for connecting the output terminal of the first buffer amplification means to the feedback input terminal of the second feedback amplification means.