JPH07122867B2 - Data transfer controller - Google Patents

Description

The present invention relates to a data transfer control device for a computer system,
In particular, the present invention relates to a data transfer control device suitable as a data transfer device between two semiconductor memory devices connected to a computer.

[Conventional technology]

As a method for realizing high-speed data transfer between storage devices of a computer system, especially between semiconductor storage devices
As described in the publication, a method is known in which data is directly transferred between a main storage device and an expansion storage device by an instruction from a processing device.

If the same kind of asynchronous instruction as for the input / output device such as a disk storage device is issued to these storage devices and the end processing is performed by issuing an input / output interrupt to the processing device after the data transfer is completed, the start of the instruction is started. The processing and termination processing take time, and the high speed of the semiconductor memory device cannot be fully utilized. Therefore, according to the above-mentioned known example, the processing device uses a command for a high-speed semiconductor memory device as a synchronous command. In this case, since the processing device cannot move to another instruction processing from the issuance of the instruction to the end of the data transfer, it is important to shorten this period as much as possible in order to improve the system performance.

[Problems to be solved by the invention]

The above-mentioned prior art does not consider a system in which a plurality of processing devices share two types of semiconductor memory devices and perform data transfer between these memory devices while competing with each other.

A first-come-first-served system can be considered as a system for processing the synchronization commands received from the plurality of processing devices. This is to process multiple instructions in the order in which they were received. If an instruction with a large amount of data transfer comes first in an instruction with a small amount of data transfer, the processing device that issued the latter instruction must wait longer than necessary. There is a problem of becoming long.

In order to solve this problem, a method (hereinafter referred to as a shuffle method) is conceivable in which, when a plurality of instructions compete with each other, the data transfer amount required by each command is divided into specific transfer amounts and alternately processed.

FIG. 2A is a time chart showing a state in which data transfer proceeds by the shuffle method when two instructions compete with each other. Instruction 1 has a data transfer amount of n ₀ blocks, and instruction 2 has a data transfer amount of n ₁ (n ₀ ≤n ₁ ) blocks. As is clear from this figure, it takes (2n ₀ −1) × unit block transfer time until the data transfer of the instruction 1 having a small data transfer amount is completed, and the waiting time is small for the processor issuing the instruction 1. I can't say.

It is an object of the present invention to provide a data transfer control device that minimizes the waiting time of a processing device when synchronization commands issued from a plurality of processing devices compete with each other.

[Means for solving problems]

The above object is achieved by predicting the data transfer time and preferentially processing an instruction having a small predicted value of the data transfer time when synchronization commands from a plurality of processing devices compete with each other.

As the data transfer time prediction value, for example, the data transfer amount can be used.

[Action]

By implementing a data transfer control device that preferentially processes an instruction with a small data transfer amount, the waiting time of the processing device is minimized. FIG. 2B is a time chart when the method of the present invention is adopted, and shows that it takes only n ₀ × unit block transfer time until the data transfer of the instruction 1 having a small data transfer amount is completed.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 3.

FIG. 1 is a configuration diagram showing the overall configuration of the present embodiment. The command receiving units 11 to 1n are provided corresponding to the processing devices with respect to n processing devices.
Is provided. Each instruction receiving unit operates independently of each other, prepares a transfer direction, a transfer source address, a transfer destination address, a data transfer amount, etc. according to an instruction from a corresponding processing device, and reports to the instruction selecting unit 20 when the preparation is completed. To do. The instruction selection unit 20 preferentially selects an instruction with a small data transfer amount among the instructions in the ready state, and activates the instruction processing unit 30 for the instruction processing. The instruction processing unit 30 is a unit that actually controls data transfer. The instruction processing unit 30 requests the source device A (or B) to read data at a designated address according to the instruction selected by the instruction selection unit 20, and transfers the destination device B ( Alternatively, it requests A) to write the read data.

FIG. 3 is a more detailed block diagram of this embodiment. The instruction receiving units 11 to 1n receive an instruction including a transfer direction, a transfer start address of the device A, a transfer start address of the device B, and a transfer amount from the corresponding processing devices. For simplicity,
It is assumed that the data transfer amount is instructed in a block unit which is a transfer processing unit of the instruction processing unit 30.

When the instruction accepting units 11 to 1n receive an instruction from the corresponding processing device in the above format, the instruction receiving units 11 to 1n1, A address registers 112 to 1n2, B address registers 113 to 1n3, and transfer amount registers 114 respectively. Through 1n
4 and set the instruction selection unit 20 via lines 1151 to 1n51.
Report to the ready state. Also the command reception section
When receiving the block-by-block acceptance report from the instruction selecting unit 20 through the lines 2071 to 207n, the 11 to 1n increment the contents of the A address register 112 to 1n2 and the B address register 113 to 1n3 by one block, and transfer amount. Register 1
Decrement the contents of 14 to 1n4 by 1. As a result, when the contents of the transfer amount registers 114 to 1n4 become 0, the instruction receiving units 11 to 1n release the ready state and report the instruction processing completion to the corresponding processing device.

When the instruction processing unit 30 receives a block transfer start command from the instruction selecting unit 20 via the line 2083, the transfer direction, the transfer start address of the device A, and the transfer start address of the device B for the selected command sent via the line 2041. The transfer start address is set to the direction register 301, the A address register 302, and the B address register 30, respectively.
Set to 3 and start the transfer process. For example, when the transfer direction is from device A to device B, a read request for one block is first issued to device A with the contents of the A address register 302 as the start address. Next, when the read data is sent from the device A, a write request for one block is issued to the device B with the contents of the B address register 303 as the head address. When the transfer process is completed,
It reports to the instruction selector 20 via block 3041 that the block transfer is complete.

Next, an instruction selection unit characteristic of the data transfer control device of the present invention
The configuration of 20 will be described. The transfer amount of each instruction sent via the lines 1141 to 1n41 is calculated by the addition circuit 2011.
Through 201n, α is added according to the condition described later, and the result is input to the comparison circuit 202. Comparing circuit 202 is line 1151
Through 1n51 to determine whether or not each instruction is in the ready state, compare the transfer amount added as necessary for the instruction in the ready state, and select the instruction with the smallest number 1 to n) are output. The instruction number output from the comparison circuit 202 is set in the instruction number register 203 under the control of the control circuit 208. The selector 204 determines the transfer direction of each command sent via the lines 1111 to 1n11 and the device A.
The transfer direction of the instruction designated by the instruction number register 203, the device A address, and the device B address are selected from the address and the device B address, and are delivered to the instruction processing unit 30 via the line 2041. OR gate 206 ORs lines 1151 through 1n51 to notify control circuit 208 that any of the instructions are in a ready state. The demultiplexer 207 is
One line designated by the instruction number register 203 is selected from the lines 2071 to 207n in order to deliver the acceptance report from the control circuit 208 to the selected instruction reception unit, and the selected line and the line 208 are selected.
Connect 4 The decoder 205 instructs addition circuits 2011 to 201n to perform addition via lines 2051 to 205n. This addition instruction is issued to an instruction other than the instruction given by the instruction number register 203 when the control circuit 208 is in the "operating state" described below. The adder circuits 2011 to 201n and the decoder 205 convert the instruction switching overhead when the instruction selecting unit 20 switches from the instruction being processed to another instruction which has not been processed to the block transfer amount and transfer the instruction not selected. It is added to the quantity, and the addition value α may be selected so as to satisfy the following relationship.

α block transfer time≈instruction switching overhead time Therefore, when the instruction switching overhead time is smaller than the one block transfer time, the adder circuits 2011 and 201n and the decoder 205 are not necessary.

The control circuit 208 has two states, "in operation" and "non-operation", and operates as follows.

(I) In the "non-operation state", when it is found that any instruction is in the ready state via the OR gate 206,
Instructing to set the instruction number register 203 via line 2082, issuing a block transfer start command via line 2083, issuing an acceptance report via line 2084, and issuing an "in operation" state.
Move to.

(Ii) When a block transfer end report is received from the instruction processing unit 30 in the "operating state" and any instruction is in the ready state, a set instruction of the instruction number register 203, a block transfer start command, and an acceptance report are issued. Issued and stay in "active" state. In this state, the control circuit 208 is line 208
The addition instruction is given to the decoder 205 via 1.

(Iii) When a block transfer completion report is received from the instruction processing unit 30 in the "operating state" and none of the instructions is in the ready state, the "non-operating state" is entered.

Next, an operation example of the instruction selection unit 20 will be shown. In the following operation example, it is assumed that the added value α is all 1.

(A) Operation example 1 In the case where an instruction with a transfer amount of 2 arrives at the instruction receiving unit 11 in the “non-operating state”.

When line 1151 reports the ready state, control circuit 208 directs to set instruction number register 203, but only instruction 1 is in the ready state, so instruction number 1 is set and selector 204 places line 1111. select. Subsequently, the control circuit 208 activates the block transfer processing of the instruction processing unit 30 via the line 2083, while making an acceptance report to the instruction receiving unit 11 via the line 2084, the demultiplexer 207, and the line 2071, and the “operating state”. "Transition to". Order acceptance section 11 that received the acceptance report
Causes the address registers 112 and 113 to increase by one block, and the transfer amount register 114 to decrease by 1 to be 1. When a block transfer completion report comes from the instruction processing unit 30 in this state, 1 is reset in the instruction number register 203 in the same manner as above,
A block transfer start command is issued to the instruction processing unit 30 via the line 2083, and an acceptance report is sent to the instruction receiving unit 11. The instruction receiving unit 11 subtracts 1 from the transfer amount register 114 to 0, and the line 115
The ready state on 1 is released and the instruction processing end is reported to the processor 1. In this state, when a block transfer end report is received from the instruction processing unit 30 via the line 3041, none of the instructions is in the ready state, so the control circuit 208 is in the “non-operating state”.

(B) Operation example 2 In the "non-operating state", a command of transfer amount 2 arrives at the command receiving unit 11 and a command of transfer amount 3 simultaneously arrives at the command receiving unit 12. Since it is in the "non-operation state", the decoder 205
Does not issue an addition instruction to any of the addition circuits. Therefore, the comparison circuit 202 compares the transfer amounts 2 and 3 and outputs the instruction number 1 having a smaller transfer amount 2. As a result, under the control of the control circuit 208, the instruction 1 is selected, processed, accepted and reported, and the values in the transfer amount registers 114 and 124 of the instructions 1 and 2 change to 1 and 3, respectively. When the block transfer completion report comes in this state, since it is in the “operating state” this time, an addition instruction is issued to an addition circuit other than the addition circuit 2011 of the instruction 1,
The comparison circuit 202 compares the transfer amounts 1 and 4 (= 3 + 1). As a result, the instruction 1 is again selected, processed, accepted and reported, and the processing of the instruction 1 ends. After that, the instruction 2 is independently processed, and the operation is the same as the operation example 1.

(C) Operation example 3 When an instruction with a transfer amount of 1 arrives at the instruction receiving unit 12 during processing of the instruction 1 (remaining transfer amount of 3).

When the block transfer completion report is received, since it is in the "operating state", the addition instruction is issued to the addition circuits other than the instruction 1, and the comparison circuit 202 compares the transfer amounts 3 and 2 (= 1 + 1). It will be. As a result, command 2 is selected this time,
After the processing, the acceptance is reported, and the instruction 2 ends. After that, the single processing of the instruction 1 is performed again, and the same operation as the operation example 1 is performed.

If three or more instructions compete at the same time,
The operation is similar to the above. Further, when the transfer amounts of two or more instructions are the same, the comparison circuit 202 selects the instruction with the smallest instruction number.

As described above, according to this embodiment, the instruction having a small transfer amount can be preferentially processed, so that the waiting time of the processing device can be minimized. Further, according to this embodiment, it is possible to deal with the case where there is a processing command switching overhead.

In the above embodiment, the case where the data transfer amount is compared on a block-by-block basis has been described, but a plurality of ranks from small transfer to large transfer are provided by providing a certain amount of data transfer amount.
It is also possible to easily control the processing by giving priority to the small transfer between the ranks. For example, in the comparison circuit 202 shown in FIG. 3, if the lower 3 bits of the data transfer amount are ignored and the comparison is performed in units of 8 blocks,
Small transfer can be prioritized among ranks of every 8 blocks.

〔The invention's effect〕

According to the present invention, when a plurality of instructions compete with each other, the processing can be performed in the order of the instruction having the smallest data transfer amount, so that the waiting time of the processing device can be minimized.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an overall configuration of an embodiment of the present invention, FIG. 2 (a) is a processing time chart by a shuffle system,
FIG. 2 (b) is a processing time chart according to the present invention, and FIG.
The figure is a detailed block diagram of one embodiment of the present invention. 11,1n …… Instruction receiving section, 20 …… Instruction selection section, 30 …… Instruction processing section, 114,1n4 …… Transfer amount register, 2011,201n …… Adding circuit, 202 …… Comparison circuit, 203 …… Instruction Number register,
204 …… Selector.

Claims (2)

[Claims] 1. A data transfer control device that controls data transfer between two semiconductor memory devices shared by a plurality of processing devices based on commands from the plurality of processing devices, and receives a synchronization command from the plurality of processing devices. A plurality of instruction receiving means held by each of them and a data transfer amount designated for each instruction are input from the plurality of instruction receiving means, and an instruction with a small data transfer amount is preferentially selected and then processed. A data transfer control device comprising: an instruction selecting unit that is designated as an instruction; and an instruction processing unit that executes data transfer between the two semiconductor memory devices based on the instruction designated by the instruction selecting unit. 2. The instruction processing means transfers data in units of a predetermined transfer processing unit, and the instruction selecting means sets a data transfer amount from an instruction receiving means for holding an instruction being executed in the predetermined transfer processing unit. The data transfer control device according to claim 1, wherein the data transfer control device is decreased each time the transfer of data is completed.