JPH0683764A - Interface system between cpu and bus control circuit - Google Patents

Abstract

PURPOSE:To reduce the load of a CPU about data transfer among a CPU card and plural hardware cards. CONSTITUTION:A data storing area 21 in a memory 2 stores plural card data to be transferred among the CPU card 10 and plural hardware cards 4. A pointer area 22 in the memory 2 stores respective pointers having information indicating the storing positions of respective card data stored in the area 21 and information for linking plural card data stored in the area 21. A bus control circuit 3 controls data transfer (data transfer relating to all the card data stored in the area 21) among the CPU card 10 and the hardware ards 4 by referring to the area 22 based upon a data transfer command outputted from the CPU 1, and at the end of data transfer, issues a transfer end interruption to the CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU (Central Processing Unit) for executing a program.
it. CPU card including a central processing unit, a plurality of hardware cards (cards that configure hardware or cards that control hardware), and high-speed hardware control bus (high-speed data transfer between the CPU card and the hardware card) CPU-bus control circuit interface system in a control device having a control bus for connecting both cards to each other.

[0002]

2. Description of the Related Art A bus control circuit for controlling a high-speed hardware control bus is provided in a CPU card of a control device as described above. In order to transfer data between the CPU card and a plurality of hardware cards, a CPU-bus control circuit interface method for controlling an interface for data transfer between the CPU and the bus control circuit is required. It has become.

Conventionally, in this type of CPU-bus control circuit interface system, the interface for data transfer between the CPU and the bus control circuit has been closed to hardware card-based data transfer. That is, the CPU issues a data transfer instruction to the bus control circuit every time data relating to one hardware card (including a data transmission request for prompting the hardware card to transmit data to the CPU card is transmitted). , Data about one hardware card (the hardware card is CP
Every time a reception is made (including a data reception response indicating that data from the U card is received) (every time data transfer for one hardware card is completed), an interrupt (indicates the end of data transfer) An interrupt (hereinafter referred to as a transfer end interrupt) was issued from the bus control circuit to the CPU.

Therefore, the CPU needs to perform the transmission processing when issuing the above-mentioned data transfer instruction, and the reception processing when receiving the above-mentioned transfer end interrupt, for each hardware card. . That is, the processing (the above-described transmission processing and reception processing, etc.) related to the control of the interface for data transfer regarding another hardware card has been performed again after the processing regarding the one hardware card is completed.

[0005]

SUMMARY OF THE INVENTION The conventional CPU described above.
In the inter-bus control circuit interface method, since the interface for data transfer between the CPU and the bus control circuit is closed for data transfer in hardware card units, data transfer between the CPU card and the hardware card is performed. In the case where the load on the CPU with respect to the hardware becomes large and data of several bytes is transferred to each of the plurality of hardware cards, the CPU only performs the processing related to the control of the interface for data transfer. There is a drawback that the processing efficiency of the CPU is reduced.

In recent years, as the performance of the high-speed hardware control bus has been improved (higher speed), the above-mentioned drawbacks have become more prominent, and the processing efficiency of the CPU has significantly decreased.

In view of the above points, an object of the present invention is to provide a CPU
By connecting a memory having a data storage area and a pointer storage area between the bus control circuit and the bus control circuit,
CPU while reducing the load on the CPU related to data transfer between the U card and the hardware card and ensuring high-speed data transfer between the CPU card and the hardware card
An object of the present invention is to provide a CPU-bus control circuit interface method capable of improving the processing efficiency of the above.

[0008]

A CPU-bus control circuit interface system according to the present invention is a CPU having a CPU.
Card, a plurality of hardware cards controlled by the CPU card, a high-speed hardware control bus for connecting the CPU card and the hardware card, and the CP for performing control related to the high-speed hardware control bus
In a CPU-bus control circuit interface system in a control device including a bus control circuit in a U card and a memory in the CPU card connected between the CPU and the bus control circuit, the CPU A data storage area in the memory for storing a plurality of card data to be data-transferred between the card and the plurality of hardware cards, and information indicating a storage location of each card data in the data storage area By referring to the pointer area in the memory for storing each pointer having information for linking a plurality of card data in the data storage area and the pointer area based on a data transfer instruction from the CPU All cards in the data storage area between the CPU card and the hardware card Controls data transfer for over data having said bus controller that issues a transfer end interrupt to the CPU at the end of the data transfer.

[0009]

In the CPU-bus control circuit interface system of the present invention, the data storage area in the memory stores a plurality of card data to be data transferred between the CPU card and the plurality of hardware cards, A pointer area stores therein each pointer having information indicating a storage location of each card data in the data storage area and information for linking a plurality of card data in the data storage area, and a bus control circuit from the CPU By referring to the pointer area based on the data transfer instruction, the data transfer for all card data in the data storage area between the CPU card and the hardware card is controlled and transferred to the CPU at the end of the data transfer. Issues an end interrupt.

[0010]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a CPU-bus control circuit interface system according to the present invention. The CPU-bus control circuit interface method according to the present embodiment includes a CPU 1, a memory 2 having a data storage area 21 and a pointer area 22, and a bus control circuit 3.
, A plurality of hardware cards 4, a CPU bus 5,
A high-speed hardware control bus 6 is included. Here, the CPU 1, the memory 2, the bus control circuit 3, and the CPU bus 5 are provided in the CPU card 10. Access to the memory 2 by the CPU 1 and the bus control circuit 3 is performed via the CPU bus 5 (the reference to the CPU bus 5 is omitted in the following description).

FIG. 2 is a block diagram showing the structure (data structure) of the memory 2 connected between the CPU 1 and the bus control circuit 3. In the memory 2, the CPU card 10
Storage for storing a plurality of data (data to be processed in the hardware card 4 and data for controlling the hardware card 4, etc .; hereinafter referred to as card data) transferred between the hardware card 4 and the plurality of hardware cards 4. There are an area 21 (a plurality of data storage areas 21 can exist in the memory 2) and a pointer area 22 for storing each pointer corresponding to each card data in the data storage area 21. As shown in FIG. 2, the memory 2 is accessed by the CPU 1 and the bus control circuit 3, and the pointer area 22 in the memory 2 is referenced by the bus control circuit 3.

The pointer in the pointer area 22 is information for linking the information indicating the storage location of the corresponding card data (here, the head address of each card data) and a plurality of card data in the data storage area 21. (Has information (here, the start address of the pointer) indicating the storage location of the pointer corresponding to the card data next to the corresponding card data. In order to indicate the end of the link of a plurality of card data. Is provided with a pointer (NULL pointer) for storing "NULL (0)", and the pointer corresponding to the last card data in the link stores the leading address of the NULL pointer.

FIG. 3A is a diagram showing an example of a control sequence of data transfer by the conventional CPU-bus control circuit interface method. 3B is a diagram showing an example of a control sequence of data transfer by the CPU-bus control circuit interface method of the present embodiment (a control sequence corresponding to the control sequence shown in FIG. 3A). .

Next, C of this embodiment having the above-mentioned configuration
The operation of the PU-bus control circuit interface method will be described.

The CPU 1 in the CPU card 10 is a CPU
When it becomes necessary to transfer data between the card 10 and the plurality of hardware cards 4, the card data (C
A data storage area 21 for storing card data (including a data transmission request) transmitted from the PU card 10 to the hardware card 4 and card data to be received (transmitted from the hardware card 4 to the CPU card 10). A data storage area 21 for storing card data (including a data reception response) is secured in the memory 2. The number of card data in one data storage area 21 can be set arbitrarily, and the data length of each card data may be variable.

Next, the CPU 1 transfers data regarding a plurality of card data stored in the data storage area 21 secured as described above to each card data in the data storage area 21 in order to continuously perform data transfer. A pointer area 22 (corresponding data storage area 2 in which the corresponding pointer is stored
The pointer area 22) corresponding to 1 is secured in the memory 2. Each pointer in this pointer area 22 stores the start address of the corresponding card data and the start address of the next pointer (the next pointer in the link of a plurality of card data). In the pointer area 22,
A NULL pointer is provided to indicate the end of linking of a plurality of card data in the corresponding data storage area 21.

When the setting in the memory 2 as described above is completed, the CPU 1 issues a data transfer instruction to the bus control circuit 3. This data transfer instruction includes the start address of the pointer area 22 corresponding to the data storage area 21 related to the card data to be transmitted and the card data to be received. In addition to issuing the data transfer instruction, the CP
U1 is a data storage area 2 related to card data to be transmitted
A plurality of pieces of card data to be transmitted (including a data transmission request) are set in 1.

Based on the data transfer instruction, the bus control circuit 3 traces each pointer from the first pointer to the NULL pointer in the pointer area 22 corresponding to the data storage area 21 relating to the card data to be transmitted, The head address of each card data is sequentially acquired (when the transmission of one card data is completed, the information in the pointer corresponding to the next card data (the head address of the corresponding card data) is acquired). Then, the card data specified by such a start address is acquired from the data storage area 21, and the card data is transferred to the predetermined hardware card 4 (the destination hardware card 4 is transmitted via the high-speed hardware control bus 6). The information shown is present in the card data).

The bus control circuit 3 repeats the above processing until there is no card data to be transmitted. Here, the end of all the transmission of the card data to be transmitted is judged by the presence of the NULL pointer in the pointer area 22.

Each hardware card 4 that has received the card data transmitted from the bus control circuit 3 performs a process based on the card data and sends the card data (including a data reception response) based on the process to the high-speed hardware. It is transmitted to the CPU card 10 via the control bus 6.

The bus control circuit 3 in the CPU card 10 is
The card data received from each hardware card 4 is stored in the data storage area 21 related to the card data to be received. Here, the bus control circuit 3 stores the storage location of each card data in the data storage area 21 in the pointer area 22 corresponding to the data storage area 21 related to the card data to be received which is acquired by the above-mentioned data transfer instruction. It is recognized by the head address and the information in each pointer in the pointer area 22.

When the bus control circuit 3 finishes receiving all the card data to be received (when all the data transfer relating to the above-mentioned data transfer instruction is finished), the CPU 1
To the CPU 1 to notify the CPU 1 of the end of the data transfer.

When the CPU 1 receives the transfer end interrupt, the CPU 1 acquires each card data in the data storage area 21 related to the card data to be received in the memory 2 and performs the receiving process for each card data.

It should be noted that the CPU 1 operates from the issuance of the above data transfer instruction until the receipt of the above transfer end interrupt.
Processing (other processing) other than transmission processing and reception processing can be performed. That is, the processing efficiency of the CPU 1 is improved.

Next, referring to FIGS. 3A and 3B, a data transfer control sequence in the conventional CPU-bus control circuit interface method and the CPU-bus control circuit interface method of the present embodiment. The difference will be explained.

In the conventional CPU-bus control circuit interface system, the bus control circuit 3 sends the CPU 1 to the CPU 1 each time data transfer for one hardware card 4 is completed.
A transfer end interrupt was issued to the device (see FIG. 3 (a)). Therefore, the CPU 1 needs to perform a transmission process related to the data transfer for each data transfer related to one hardware card 4, and needs to perform a reception process related to the data transfer for each data transfer related to the one hardware card 4. It was Therefore, the time for performing other processing (processing other than the transmission processing and the reception processing) between the transmission processing and the reception processing has been limited.

On the other hand, in the present embodiment, and further in the CPU-bus control circuit interface method of the present invention, a plurality of continuous card data (a plurality of hardware cards 4
Data transfer of a plurality of card data) is performed by one data transfer instruction and a transfer end interrupt (see FIG. 3B). Therefore, until the data transfer (data transfer regarding a plurality of consecutive card data) performed under the control of the bus control circuit 3 is completed, the CP
U1 can perform other processing. by this,
There is an effect that the processing efficiency of the CPU 1 is improved. The effect of this embodiment (the present invention) becomes more remarkable as the number of hardware cards 4 subject to continuous data transfer increases and the performance of the high-speed hardware control bus 6 increases.

[0029]

As described above, according to the present invention, a data storage area for storing a plurality of card data in a memory connected between a CPU and a bus control circuit and a plurality of cards in the data storage area. A pointer area for storing pointers for linking data is provided, and the bus control circuit refers to the pointer area to perform control related to data transfer of a plurality of card data. It is possible to reduce the intervention of the CPU when transferring the data of the card data.
It is possible to reduce the load on the CPU related to the data transfer between the PU card and the hardware card, and the C
It becomes possible for the CPU to perform the processing (the above-mentioned “other processing”) that should be performed by the PU for a long time, and ensure the high-speed data transfer between the CPU card and the hardware card while improving the processing efficiency of the CPU. There is an effect that it can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a structure and the like of a memory in FIG.

3A is a diagram showing an example of a control sequence of data transfer according to a conventional CPU-bus control circuit interface system, and FIG. 3B is a diagram showing data according to the CPU-bus control circuit interface system shown in FIG. It is a figure which shows an example of the control sequence of transfer.

[Explanation of symbols]

 1 CPU 2 Memory 3 Bus Control Circuit 4 Hardware Card 5 CPU Bus 6 High Speed Hardware Control Bus 10 CPU Card 21 Data Storage Area 22 Pointer Area

Claims (1)

[Claims] 1. A CPU card having a CPU and the CPU card
A plurality of hardware cards controlled by a PU card, a high-speed hardware control bus connecting the CPU card and the hardware card, and a bus control circuit in the CPU card for controlling the high-speed hardware control bus And a CPU-bus control circuit interface method in a control device including a memory in the CPU card connected between the CPU and the bus control circuit, wherein the CPU card and a plurality of the hardware are provided. A data storage area in the memory for storing a plurality of card data to be transferred to and from a wear card, information indicating a storage location of each card data in the data storage area, and a data storage area in the data storage area. Stores each pointer with information for linking multiple card data A pointer area in the memory, and all card data in the data storage area between the CPU card and the hardware card by referring to the pointer area based on a data transfer instruction from the CPU. A CPU-bus control circuit interface method comprising: a bus control circuit which controls data transfer and issues a transfer end interrupt to the CPU at the end of the data transfer.