JPH07122648A - Routing method for wiring - Google Patents

Abstract

PURPOSE:To achieve high speed routing of wiring without sacrifice of the features of maze-running method by employing a matrix setting step in which information for deciding whether wiring to an adjacent grid can be made or not is set for each grid and then developing the basic point with reference to that information. CONSTITUTION:A matrix map 101 is entirely initialized such that the routing can be made in all directions for each grid and then the routing is disabled in the outward direction from the matrix map 101 for the grids 10-33 on the located on the outer fringe part. Consequently, no routing is conducted outward from the grids 10-33 and searching of outward route becomes meaningless. Furthermore, the routing is prohibited for corresponding grids with reference to the routing prohibition information, etc., and the routing toward the prohibited grid is also prohibited for adjacent grids. The routing is effected for each grid with reference to the matrix map 101 set with information for deciding whether the routing can be made to an adjacent grid. This method realizes high speed developing of basic points.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic placement and routing technology, for example, using a gate array type or standard cell type semiconductor integrated circuit, and further CAD (Computer Aided Design) or DA (Design Automation). The present invention relates to a technique effectively applied to automatic placement and routing of a custom LSI.

[0002]

2. Description of the Related Art In an automatic layout of a semiconductor integrated circuit (hereinafter also simply referred to as an LSI), that is, automatic placement / wiring, cells having a layout design are used to arrange the cells on a semiconductor substrate and between terminals of the cells. Wiring is performed. The cell layout is generated manually or through an automatic program based on a circuit diagram designed in advance. For example, the cell layout automatic generation program is
The actual pattern of the cell is generated based on the circuit diagram information, the layout rule in the processing process of the LSI, and the designation information such as the width and length (W / L) of the transistor. In order to automatically lay out an LSI using cells defined as such a physical pattern, information such as the cell shape, terminal position, and wiring prohibited area that can be recognized from the physical pattern is required.

By the way, a maze method (Lee algorithm) can be cited as a typical method of automatic placement and routing processing in an LSI or a board (printed circuit board). In this maze method, the wiring area is divided into a grid shape, the wiring prohibited area is set in that grid, and the writable grid is expanded in a wavy manner from the start point. It follows the route to determine the route. That is, information on the starting point, the target point, and the wiring prohibited area is set in the matrix map 100 as shown in FIG. 5 (step 1), and wiring from this starting point to each adjacent grid is possible with the starting point as the starting point. The base point cost is incremented in the grid and set in the base point waiting table (step 2). If the target point is not reached, the minimum cost is taken out from the base point waiting table, and the above process is repeated again using that as the base point ( Step 3). Here, since the processing of steps 2 and 3 is repeated several hundred thousand times when one path is determined, the processing time is inevitably lengthened.

An example of a document describing the automatic placement and routing technology is "CMOS Device Handbook (P159 to P164)" issued by Nikkan Kogyo Shimbun on September 29, 1987.

[0005]

As a method for shortening the wiring route processing time, a trial range is limited and only the limited range is searched, or a direction approaching a target point is prioritized. A method of controlling the base point expansion as described above can be considered. However, when the present inventor examined it, it is attempted to speed up by narrowing down the number of expansions of the base point and reducing unnecessary searches, and thus reducing the number of expansions of the base point is required if there is a route. It has been found that the search ability, which is also a feature of the maze method, that can always find it is sacrificed to some extent.

An object of the present invention is to speed up wiring route processing without impairing the features of the maze method.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, in the wiring path processing method, as a matrix map setting step, wiring permission / prohibition information for adjacent lattices is set for each lattice, and base point expansion is performed with reference to the set wiring permission / prohibition information.

[0010]

According to the above-mentioned means, as the matrix map setting step, the wiring availability information for the adjacent grids is set for each grid, and the base point expansion is performed with reference to the set wiring availability information. In the base point expansion, it is not necessary to refer to other base points, which achieves high speed of the base point expansion processing.

[0011]

FIG. 6 shows an overall processing flow of a layout including automatic placement and routing, which is a method according to an embodiment of the present invention. Although not particularly limited, in the present embodiment, automatic placement and routing is performed by a CAD (Computer Aided Design) system.

When designing an LSI, in order to reduce the time and labor required for the design, elements (for example, transistors) are not laid out one by one on a chip, but a unit having a certain logical function. It is usual to complete the layout for each block (functional cell) in advance, and to complete the layout and wiring in the entire chip while laying out the basic cells in these layouts.

The information in the cell layout library 24 is
It is used in each processing of automatic block placement, in-block placement wiring, and inter-block wiring, and when the overall layout is finally determined, it is converted into mask data and stored as mask drawing data.

Incidentally, FIG. 6 also shows, as a reference, the flow of processing for generating the cell layout library exclusively by hand. In this case, the designer creates a cell layout library specification by picking out values while looking at the actual pattern of the cell, then coding while looking at this, further checking it, and checking if necessary. The cell layout library 80 is completed only after the correction.

When the LSI is laid out according to the procedure shown in FIG. 6, when it becomes necessary to vertically or horizontally arrange the cells of the same logic according to the cell arrangement location, In addition, when the cell pattern must be changed and used according to the placement location in order to correct the unevenness of signal propagation delay or the difference from the design value, a cell that satisfies those requirements is prepared in advance. If not, the cell automatic design program is started in the middle of the layout, and a predetermined performance pattern is specified to create the required cell substance pattern. In this way, when a new cell whose pattern or logic has been added and changed is needed during layout, in other words,
When it is necessary to properly use cells having different patterns and different performances during layout, the layout library can be easily obtained through the above procedure.

In this embodiment, the wiring path for connecting the terminals is obtained by the maze method. Although there is no particular limitation in the wiring route processing that adopts the maze method,
A first step of setting a matrix map, a second step of setting a starting point and a destination point in this matrix map, a third step of searching a route while referring to the matrix map, and a first step of determining a route by backtrace. 4 steps and a 5th step of updating the matrix map to prohibit the determined route.

The above-mentioned first step includes a step of setting, for each grid, wiring availability information from the grid to an adjacent grid. That is, information on whether or not wiring is possible from one grid to an adjacent grid is set.

FIG. 1 shows a matrix map 101 thus set. Although not particularly limited,
Such a matrix map 101 is formed by using an appropriate storage device such as a RAM (random access memory) included in the CAD system.

Specifically, first, the entire matrix map is initialized so that it can be omnidirectionally wired for each grid, and thereafter, the wiring toward the outside of the matrix map cannot be wired with respect to the grid at the outer edge portion. In FIG. 1, the lattices 10 to 33 belong to the outer edge portion, and the lattices 10 to 3 concerned.
In 3, the outward arrow is deleted. This is because the wiring route is not formed from the lattices 10 to 33 to the outside, and such outward route search is meaningless. Furthermore, referring to information such as wiring prohibition,
Wiring is prohibited for the corresponding grid (portion indicated by hatching in FIG. 1), and wiring in a grid adjacent to the grid is prohibited in the direction toward the wiring prohibition grid.
In FIG. 1, in the lattice around the wiring prohibited area, the arrow pointing to the prohibited area is deleted. This is because the route search to the prohibited area is meaningless. In this way, the matrix map is initialized.

The reference point expansion processing can be speeded up by processing by referring to a matrix map in which wiring availability information for adjacent grids from each grid is set. The base point expansion processing in this embodiment will be described below in comparison with the conventional method.

For example, FIGS. 3 and 4 show the flow of the base point expansion processing by the conventional method. In FIGS. 3 and 4, A and A indicate that the processing is continued.
In the conventional method, one base point (X, Y, Z) is taken out from the base point waiting table (step 301), and it is determined whether or not the trial point (X + 1, Y, Z) incremented by 1 in the X direction can be wired. It is performed (step 302). If it is determined that wiring is not possible in this determination, in the X direction −
It is determined whether or not the 1-trial point (X-1, Y, Z) can be wired (step 304). If it is determined that wiring is possible in the determination in step 302, the trial point (X + 1, Y, Z) is set in the base point waiting table (step 303), and then the determination in step 304 is performed. . Then, the above step 304
If it is determined that the trial points (X-1, Y, Z) cannot be wired in the above determination, the next determination (step 3
06), and if it is determined that wiring is possible in the determination in step 304, the trial point (X
After (-1, Y, Z) is set in the base point waiting table (step 305), the process proceeds to the determination of step 306.

Thereafter, it is determined whether or not the trial point (X, Y + 1, Z) incremented by 1 in the Y direction can be wired, and the base point waiting table is set according to the determination result (steps 306 and 307). , −1 in the Y direction (X, Y−1, Z) is determined whether or not wiring is possible, and a base point waiting table is set according to the determination result (steps 308 and 309), Z It is determined whether or not the trial point (X, Y, Z + 1) that has been incremented by 1 in the direction can be wired, and the base point waiting table is set according to the determination result (steps 310 and 311), and is decremented by 1 in the Z direction. Whether or not the trial point (X, Y, Z-1) can be wired is determined, and the base point waiting table is set according to the determination result (steps 312 and 313).

On the other hand, in the present embodiment, as shown in the flow of processing in FIG. 2, from the base point waiting table formed using the storage device such as the RAM of the CAD system, the base point (X, Y, Z ) Is taken out (step 201), it is judged whether or not the base point (X, Y, Z) can be expanded (step 202), and if it is judged in this judgment that it can be expanded, that is, If it is determined that wiring can be performed from the base point to the adjacent grid, the expandable point is set in the base point waiting table (step 203), and the process for the base point (X, Y, Z) is performed. Is ended. The points set in the base point wait table are subject to subsequent processing. In addition, the above step 202
Even when it is determined that the expansion is impossible in the determination of, the processing for the base point is ended. As described above, the base point expansion processing in this embodiment is significantly simplified as compared with the conventional method shown in FIGS. 3 and 4, in the case of this embodiment.
Since the processing is performed by referring to the matrix map 101 in which the wiring availability information from each grid to the adjacent grid is set, if only one of the base points extracted from the base point table is referred to, the grid adjacent to it will be displayed. This is because it is possible to determine whether or not wiring is possible, and unlike the case shown in FIG. 3, it is not necessary to individually check each of the trialable X, Y, and Z directions. In other words, by performing the base point expansion with reference to the matrix map 101, it is possible to determine whether or not the wiring to the adjacent grid is possible without referring to the information of other base points. Can be significantly shortened.

According to the above embodiment, the following operational effects can be obtained.

(1) As a setting step of the matrix map 101, wiring permission / prohibition information for adjacent lattices is set for each lattice, and the reference point expansion is performed by referring to the set wiring permission / prohibition information. In, the possibility of wiring from the base point to the adjacent point can be immediately determined, and it is not necessary to refer to another base point, so that the wiring route search process can be speeded up.

(2) In addition, as in the method of limiting the trial range to search only the range or the method of preferentially searching in the direction of the target point, the processing speed is increased by narrowing down the number of developed base points. Since it is not intended to be realized, it does not have to sacrifice the search ability that is a feature of the maze method.

(3) Initially set so that wiring in all directions is possible,
Of the lattices adjacent to it for each lattice, the outward direction is erased, and the wiring prohibited area and the lattice that is adjacent to the wiring prohibited area and goes from the lattice to the wiring prohibited area are erased by the procedure. The wiring availability information can be easily set in the matrix map 101.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above-described embodiment, another speed-up technique, for example, a method of limiting the trial range to search only the trial range or a method of controlling the base point expansion so that the direction approaching the target point is prioritized is used together. You may do it.

In the automatic placement and routing process employing the maze method, a route search process is performed on an unrouted net, and if a route cannot be found by this process, the obstacle line is removed and then the route is again searched. There is a function that performs wiring processing for unwired and removed faulty wiring, then calculates the evaluation value before and after rewiring and adopts the effective one. The invention is effective.

In the above description, the invention that was mainly made by the present inventor is the field of use that is the background of CAD.
Although the automatic placement and routing by (Computer Aided Design) has been described, the present invention is not limited thereto and DA (Design Automation) is used.
It can be widely applied to automatic placement and routing of semiconductor integrated circuits using the.

The present invention can be applied on the condition that the wiring route for connecting at least the terminals is formed by the route search.

[0033]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, as the setting step of the matrix map, the wiring availability information for the adjacent grids is set for each lattice, and the base point expansion is performed with reference to the set wiring availability information. Since it is not necessary to refer to another base point, it is possible to speed up the wiring route search processing. Further, it is not intended to speed up the process by narrowing down the number of expansions of the base points, unlike the method of limiting the trial range and searching only the range or the method of preferentially searching in the direction of the target point. Therefore, the search ability that is a feature of the maze method is not sacrificed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a matrix map in automatic placement and routing processing to which a method according to an embodiment of the present invention is applied.

FIG. 2 is a flowchart of base point expansion in the automatic placement and routing process.

FIG. 3 is a flowchart of base point expansion processing by a conventional method for comparison with base point expansion in the automatic placement and routing processing.

FIG. 4 is a flowchart of base point expansion processing by a conventional method for comparison with base point expansion in the automatic placement and routing processing.

FIG. 5 is an explanatory diagram of a conventional matrix map for comparison with the matrix map in the automatic placement and routing process.

FIG. 6 is a flow chart of an overall layout process including the automatic placement and routing process.

[Explanation of symbols]

 10 to 33 Lattice belonging to outer edge of matrix map 80 Cell layout library 101 Matrix map

Claims (3)

[Claims] 1. A step of setting a matrix map, a step of searching a wiring route with reference to this matrix map, a step of determining a wiring route by performing a back trace based on the result of the route search, In the wiring route processing method including the step of reflecting the determined wiring route in the matrix map as a wiring prohibited area, the matrix map setting step includes a step of setting wiring permission / prohibition information for adjacent lattices for each lattice. A wiring path processing method characterized by the above. 2. The step of setting the wiring permission / prohibition information includes a step of initializing that wiring is possible in all directions, a step of erasing an outward direction of lattices adjacent to each lattice, a wiring prohibited area, 2. The wiring route processing method according to claim 1, further comprising: a step of erasing a grid adjacent to the wiring prohibited area and extending from the grid toward the wiring prohibited area. 3. A step of performing a wiring route search with reference to a matrix map, a step of determining a wiring route by performing a back trace based on the route search result, and the determined wiring route as a wiring prohibited area. In the wiring route processing method including the step of reflecting in the matrix map, the matrix map includes wiring availability information for adjacent lattices for each lattice.