JPH07122557A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent short circuit or open circuit of wiring by covering the wiring layer on a substrate with an insulation film thicker than the wiring layer, mirror polishing the rear of the substrate and polishing the surface of the insulation film. CONSTITUTION:An Al film is vacuum deposited by about 800nm, as a first wiring layer 3, on the surface of a substrate. Subsequently, a wiring pattern is formed and a photoresist pattern is removed by conventional photoresist pattern forming step and dry etching step. Furthermore, a plasma oxide 4 is deposited by about 1mum on the Al film. The plasma oxide has surface level difference of about 600nm. Finally, the single crystal silicon substrate 1 is polished on the rear side thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device by flattening and polishing the surface of an insulating film.

[0002]

2. Description of the Related Art Conventionally, Proceeding, 8th International I.E.E.E., 1991 V.M.I.C. Conference, pp. 20-26
Page (Proceedings of the 8th International IEEE VMIC
As described in Conference, pp.20-26), a first wiring layer 3 is formed on a thermal oxide film 2 on a substrate 1 (FIG. 1A), and the first wiring layer 3 is formed. Plasma CVD-SiO
_{2 a} film 4 is formed (b), the insulating film is flattened and polished (c), and then a connection hole 5 is provided in the insulating film 4.
Then, the second wiring layer is formed on the insulating film 4 (d) to manufacture the semiconductor device.

[0003]

However, in the case of the multi-layer wiring structure as described above, it is difficult to process the connection hole, so that a short circuit or disconnection of the wiring may occur and a good yield cannot be obtained. Was occurring.

It is an object of the present invention to provide a highly reliable method of manufacturing a semiconductor device in which the short circuit or the disconnection of the wiring does not occur.

[0005]

After forming a patterned wiring layer on the surface of a substrate, an insulating film thicker than the thickness of the wiring layer is formed on the substrate so as to cover the wiring layer. This is accomplished by polishing the back surface of the substrate to a mirror surface and then polishing the surface of the insulating film. Alternatively, the order of the step of forming the insulating film and the step of polishing the back surface of the substrate to a mirror surface may be exchanged.

[0006]

The thickness of the wiring formed on the substrate is about 0.9 μm. When the insulating film is formed on this substrate, the step difference on the surface of the insulating film becomes 0.3 to 0.4 μm. When the back surface of this substrate is mounted on a flat sample stage and a load is applied to polish the surface of the insulating film, the waviness and roughness of the back surface of the substrate affect the surface of the substrate. This is because there are undulations (about 0.4 μm) and roughness (about 0.5 μm) larger than the steps generated on the substrate surface. Due to the influence of undulations and roughness on the back surface of this substrate,
Even if the substrate surface is polished, it is not sufficiently flattened, so it is difficult to form a connection hole at a desired portion of the insulating film.
As a result, the wiring was short-circuited or broken.

However, it has been found that by polishing the back surface of the substrate to a mirror surface, the insulating film on the front surface of the substrate can be polished to a good flatness. This experiment is shown in FIGS. First, a plasma oxide film 22 having a thickness of about 0.5 μm was formed on the single crystal silicon substrate 21. Next, the back surface of the single crystal silicon substrate 21 was polished using a polishing liquid mixed in a potassium hydroxide aqueous solution (FIG. 2A). Next, the surface of the plasma oxide film 22 was polished (FIG. 2B). At this time, the polishing distribution on the surface of the plasma oxide film was evaluated by changing the polishing time on the back surface of the substrate. The polishing distribution was evaluated by comparing the deviation of the polishing amount variation at a specific position on the sample surface by the average polishing amount. FIG. 3 shows the results of examining the polishing time dependence of the polishing distribution on the back surface of the substrate. From the figure, it can be seen that the polishing distribution of the plasma oxide film 22 on the sample surface improves as the back surface polishing time increases.

In fact, when a wiring pattern is formed on a substrate and an insulating film is formed on the wiring pattern, the insulating film surface has a slight step as described above, but the surface has a small undulation, so that the sample stand Can be installed evenly. At this time, by polishing the back surface of the substrate, of course, the roughness can significantly reduce the waviness, so that the subsequent polishing of the insulating film can provide a polished surface with good flatness. .

[0009]

EXAMPLE 1 Example 1 is shown in FIG. The single crystal silicon substrate 1 was processed in an oxygen atmosphere at 1000 ° C. to form a thermal oxide film 2 having a thickness of about 500 nm. The thermal oxide film 2 is formed as a substitute for the interlayer insulating film on the element formed on the surface of the substrate 1. Next, the first wiring layer 3 of about 800 n is formed on the surface of the substrate by vacuum evaporation.
An m-thick Al film was deposited. A wiring pattern was formed on the Al film by the usual photoresist pattern formation and dry etching steps, and then the photoresist pattern was removed (FIG. 4A). Further, a 1 μm thick plasma oxide film 4 was formed on the Al film. The surface step of this plasma oxide film was about 600 nm (FIG. 4B). Further, the back surface of the single crystal silicon substrate 1 was polished. Next, as shown in FIG. 5, the substrate was held using the backing pad 8 on the stage 7 of the polishing machine, and colloidal silica (particle size: 20 nm) was mixed on the polishing cloth 9 in the aqueous ammonia solution. The surface of the plasma oxide film was polished while dropping the polishing liquid 10 (FIG. 4C).

Next, a contact hole 5 is formed in the plasma oxide film by using a normal contact hole forming process, and an Al wiring is formed as a second wiring layer 6 on the connection hole and the plasma oxide film (see FIG. 4 ( d)). Since the second Al wiring layer is formed by patterning the Al film deposited on the flat sample surface after the polishing step of the plasma oxide film 4,
Good results can be obtained even in the yield of short-circuiting or disconnection of fine Al wiring.

In this embodiment, the back surface of the single crystal silicon substrate 1 is polished after the plasma oxide film 4 is formed. However, the manufacturing process is changed to polish the back surface of the single crystal silicon substrate 1, and then the plasma is removed. The oxide film 4 may be formed.

<Embodiment 2> Embodiment 2 is shown in FIG. The single crystal silicon substrate 11 was processed in an oxygen atmosphere at 1000 ° C. to form a thermal oxide film 12 of about 500 nm. Next, an Al film 13 having a thickness of about 800 nm was deposited on the surface of the substrate by vacuum evaporation. A wiring pattern was formed on the Al film by the usual photoresist pattern formation and dry etching steps, and then the photoresist pattern was removed (FIG. 6A).

Next, a plasma oxide film 14 having a thickness of 300 nm is formed on the surface of this sample, and the coated glass is spin coated.
Heat treatment (450 ° C., 30 min) was performed. The coated glass film 15 was formed so as to have a thickness of about 800 nm in the flat portion, and the surface step between the Al pattern and the portion between the Al patterns at this time was about 300 nm (FIG. 6).
(B)).

Then, the back surface of the single crystal silicon substrate 11 was polished, and the surface of the coated glass film was further polished.
The convex portion of the coated glass film is polished by this polishing treatment,
The plasma oxide film 14 appeared (FIG. 6C). At this time, A
The 1 wiring 13 was covered with the plasma oxide film, and the coated glass film 15 was embedded in the groove between the wiring patterns, and the surface became flat.

Next, a plasma oxide film 16 having a thickness of about 200 nm is deposited on this surface, a contact hole 17 is formed by using a normal contact hole forming process, and a second hole is formed on the contact hole and the plasma oxide film. An Al wiring layer 18 was deposited and formed into a predetermined shape by the usual photoresist pattern formation and dry etching process (FIG. 6D). Similar to the first embodiment, since the second Al wiring layer is formed by patterning the Al film deposited on the flat sample surface after the step of polishing the coated glass film, short-circuiting of fine Al wiring and Good results are also obtained in the yield of disconnection.

In this embodiment, a plasma oxide film / an oxide film is formed on the interlayer insulating film between the first Al wiring layer and the second Al wiring layer.
A three-layer film of coated glass / plasma oxide film was used. Since the coated glass has a large effect of reducing the surface step, the surface becomes flatter. As a result, the back surface of the substrate is polished to improve the flatness of the back surface, and thus the flatness of the surface is improved also in the subsequent steps. effective.

<Embodiment 3> Embodiment 3 is shown in FIGS. A thermal oxide film 32 having a thickness of about 0.5 μm is formed on a single crystal silicon substrate 31, and a first Al wiring layer 33 is further formed thereon.
Was formed. Next, a plasma oxide film 34 was deposited by high frequency plasma, coating glass 35 was coated, and heat treatment was performed. After that, the back surface and the front surface were sequentially flattened by polishing.
(Figure 7).

Next, a plasma oxide film 36 having a thickness of about 200 nm is deposited on the surface of the sample by high frequency plasma, and the plasma oxide film 36 is formed by using a normal contact hole forming process.
The connection hole 37 was formed in the. In addition, the first Al wiring layer 33
To the third Al wiring layer to be connected with the connection hole 3
8 were provided (FIG. 8).

Further, an Al film is deposited, a second photoresist pattern is formed, and a second etching process is performed.
The Al wiring layer 39 was formed (FIG. 9). In addition, the second Al
The contact Al pattern 40 for connection to the third Al wiring layer to be connected to the wiring layer was also formed at the same time.
Similar to the first and second embodiments, the second Al wiring layer can be formed on the flat sample surface after the step of polishing the coated glass 35, so that the reliability of the short circuit or disconnection of the fine Al wiring can be obtained. It is highly likely.

After that, the plasma oxide film 41 was deposited, the coating glass 42 was formed, the sample surface was flattened by flattening polishing, the plasma oxide film 43 was deposited, and the interlayer wiring connection hole 44 was formed (FIG. 10). ).

Next, a third Al wiring layer 45 was formed.
(Figure 11). When the third Al wiring layer is directly connected to the first Al wiring layer 33, the second Al wiring 40 is formed,
Connect via this (AA '). By forming the plasma oxide films 34 and 36 when forming the multilayer wiring as described above, it is possible to prevent the coated glass from coming into contact with the wiring. Further, since the processing of the connection holes 38 and 44 by dry etching can be performed at the same depth, the processing is easy.

In this embodiment, when the plasma oxide film was formed, high frequency plasma was used.
It may be formed by R (Electron Cycrotron Resonance) plasma. Further, even if the double-sided mirror substrate is used to form the multilayer wiring from the beginning without polishing the back surface of the substrate, a semiconductor device having good surface flatness can be obtained. Furthermore, although the example of the manufacturing process of the multilayer wiring is shown in the present embodiment, the back surface of the substrate may be polished in order to flatten the stepped portion on the surface of the substrate without forming the multilayer wiring.

The semiconductor device thus formed can be applied to highly integrated memories such as CMOS, DRAM, SRAM and the like and integrated semiconductor devices.

[0024]

According to the present invention, it is possible to obtain a semiconductor device which is free from short circuit and disconnection of wiring.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a conventional semiconductor device.

FIG. 2 is a cross-sectional view of an apparatus used in an experiment of the present invention.

FIG. 3 is a diagram showing the back surface polishing time dependence of the sample front surface polishing distribution.

FIG. 4 is a sectional view of a semiconductor device manufacturing process showing the first embodiment of the present invention.

FIG. 5 is a diagram showing a method for polishing the sample surface of Example 1 of the present invention.

FIG. 6 is a sectional view of a semiconductor device manufacturing process showing a second embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device manufacturing process showing a third embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor device manufacturing process showing the third embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor device manufacturing process showing the third embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor device manufacturing process showing the third embodiment of the present invention.

FIG. 11 is a sectional view of a semiconductor device manufacturing process showing the third embodiment of the present invention.

[Explanation of symbols]

1, 11, 21, 31 ... Single crystal silicon substrate, 2, 1
2, 32 ... Thermal oxide film, 3 ... First wiring layer, 4, 22 ... Plasma oxide film, 5, 17, 37, 38, 44 ... Connection hole, 6 ... Second wiring layer, 7 ... Polishing machine Stage, 8 ... backing pad, 9 ... polishing cloth, 10 ... polishing liquid, 1
3, 33 ... First Al wiring layer, 14, 16, 34, 3
6, 41, 43 ... Plasma oxide film, 15, 35, 42 ...
Coated glass, 18, 39 ... Second Al wiring layer, 40 ... Al pattern for interlayer connection, 45 ... Third Al wiring layer.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masayuki Nagasawa 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (5)

[Claims] 1. A step of forming a first wiring layer having a desired shape on a substrate, and a thickness at a portion where the wiring layer is not formed so as to cover the first wiring layer on the substrate. Forming an insulating film thicker than the thickness of the first wiring layer, polishing the surface of the substrate opposite to the surface on which the first wiring layer is formed, and polishing the surface of the insulating film. A method of manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a plasma oxide film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the insulating film includes a step of forming a first plasma oxide film, and a coating glass film on the first plasma oxide film. And a step of forming a second plasma oxide film on the coated glass film. 4. The method for manufacturing a semiconductor device according to claim 1, wherein after the step of polishing the surface of the insulating film, a step of forming a connection hole in the insulating film on the first wiring layer is performed.
A method of manufacturing a semiconductor device, comprising the step of forming a second wiring layer on the connection hole and the insulating film. 5. A method comprising: forming an insulating film on a substrate; polishing a surface of the substrate opposite to the surface on which the insulating film is formed; and polishing a surface of the insulating film. A method for planarizing a characteristic insulating film.