JP2783263B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having three or more layers of wiring. [0002] With the recent remarkable progress of LSI technology,
2. Description of the Related Art As integrated circuits have become denser, device dimensions have been correspondingly reduced. However, since these integrated circuits also occupy 30 to 50% of the area required for wiring,
Unless the miniaturization of the wiring area is also advanced, it is difficult to increase the density. For this reason, attempts have been made to increase the number of wiring layers, and in particular, double-layer aluminum wiring has come into practical use. [0003] However, the conventional double-layer aluminum wiring is composed of a silicon oxide film and a silicon nitride film on a relatively thick first-layer aluminum wiring of about 1 μm in which the second-layer aluminum wiring is already patterned on a surface having many irregularities. Since it is formed on an interlayer insulating film such as a film, the surface step becomes extremely large, and there is a disadvantage that the wiring is liable to be disconnected, which causes a reduction in yield. Therefore, in order to realize the planarization of the surface of the integrated circuit, (1) the method of depositing the insulating film is changed from a normal pressure method to a low pressure method and from the pyrolysis method to a plasma method, and (2) directional etching, that is, a parallel plate. Improvements have been made such as flattening using mold reactive sputter etching, and (3) making the second layer aluminum film thinner, but have not yet achieved sufficient effects. FIG. 3 is a schematic sectional view of a MOS field effect transistor in which a part of a conventional MOS integrated circuit is enlarged. 1 is a P-type silicon substrate, 2 is a field oxide film, 3
Is a channel stopper region, 4 is a gate oxide film, 5 is polycrystalline silicon, 6 is a source / drain region, 7 and 9 are interlayer insulating films, for example, a silicon oxide film formed by CVD, 8
In many cases, the first layer aluminum wiring and the second layer aluminum wiring 10 are used. FIG. 1A shows a portion where the thickness of the metal wiring is so thin that a disconnection failure is likely to occur. This is done by a parallel plate type plasma etching method for miniaturization of dimensions. This is due to the fact that a steep edge profile is realized by using directional etching, and that the aluminum film is usually deposited by an electron gun type vacuum evaporation method, so that the steep step coverage on the side wall is poor. [0007] In addition, the unevenness of the surface causes unevenness in the thickness of the resist in the photolithography, which makes it difficult to miniaturize the wiring. In particular, when the number of wirings is three, four,..., Three or more, the higher the layer, the more uneven the surface becomes, and it becomes impossible to form fine wirings. For this reason, with the miniaturization of elements due to the improvement of the element formation technique of the substrate 1, the technique of forming wiring for interconnecting these elements has not been established, and the improvement of the integration density has been hindered. Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which three or more wiring layers can be provided. According to a method of manufacturing a semiconductor device according to the present invention, there is provided a method of manufacturing a semiconductor device in which three or more layers of wiring are formed on a semiconductor substrate. It is characterized in that each film is subjected to mechanochemical polishing to flatten the surface of each interlayer insulating film. In mechanochemical polishing, for example, silica (Si) having a diameter of about 0.01 μm is
Polishing is performed using a polishing cloth in which abrasive grains of O2) are suspended in a weak alkaline solution and a polyurethane-based cloth. The physical polishing action and the rubbing between the abrasive grains (SiO2) and the silicon wafer are performed. This is polishing in which the action of chemical dissolution of silicon into a weakly alkaline polishing liquid due to a rise in temperature due to heat generation is mixed. In addition, mechanochemical polishing is used in a final step of polishing a substrate such as a silicon wafer, and the surface of the polished substrate is a flat distortion-free mirror surface. When such mechanochemical polishing is applied to polishing of a silicon wafer, there is no strict restriction on the polishing amount, but the amount of irregularities of the insulating film deposited as used in the present invention is several thousand angstroms. However, since the film thickness to be polished is very thin, 2 μm or less, the polishing method is considerably limited. Under such restrictions, it is not easy to reduce irregularities of about several thousand angstroms as compared with conventional polishing such as processing of a silicon wafer. The planarization of an insulating film by mechanochemical polishing has not yet been performed. As a result of various experiments, the present inventor has found that the use of mechanochemical polishing, which has a very low polishing rate of, for example, 100 angstroms / minute and has good controllability, significantly reduces the unevenness of the insulating film. It has been newly found that a flat substrate surface can be obtained without reducing the device characteristics of the semiconductor device. Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a MOS according to an embodiment of the present invention.
FIG. 4 is a process cross-sectional view in which a wiring portion of the integrated circuit is enlarged. However, although the drawing shows only the second layer, it is formed in the same manner thereafter. After a field oxide film 12 and a channel stopper region 13 are formed on a P-type silicon substrate 11 by using a normal selective oxidation method (LOCOS), a gate oxide film 14 is formed.
Is formed by the thermal oxidation method, and FIG. 1A is obtained. Next, phosphorus-doped polycrystalline silicon 15 used for the gate electrode and wiring is deposited by vapor phase epitaxy, patterned by photolithography, and n-type impurities such as arsenic are introduced by ion implantation or the like. Then, when a source / drain region 16 serving as a lower wiring layer is formed,
Figure 1b is obtained. A silicon oxide film 17 is deposited by a vapor deposition method, a contact hole for connecting the polycrystalline silicon 15 is opened by a photolithography technique, and a first layer of aluminum 18 is deposited to a thickness of about 0.8 μm by a vacuum deposition method. Then, when patterned, FIG. 1c is obtained. Subsequently, similarly, when a silicon oxide film 19 having a thickness of about 1.5 μm, which is about twice the thickness of the aluminum film, is deposited by a vapor phase growth method, the surface irregularities are slightly reduced, and FIG. 3D is obtained. Then, a polishing solution prepared by suspending a fine powder of silica having a diameter of 100 Å or less in a weak alkaline solution is applied under a pressure of 1 μm.
When polishing is performed at 10 g / cm @ 2 at 0.5 to 0.7 .mu.m, the surface of the interlayer insulating film becomes almost flat, and FIG. 1e is obtained. After opening a contact hole for connection with the first-layer aluminum wiring, an aluminum film is further deposited by a vacuum evaporation method and similarly patterned to form a second-layer aluminum wiring 20, and FIG. Is obtained. When alloying is performed by heat treatment, extremely good wiring connection can be obtained. Thereafter, three or more layers of aluminum wiring are formed in the same manner. Failures such as disconnection of wiring do not particularly increase. FIG. 2 is a diagram for explaining the effect of the present invention.
FIG. 3 is a schematic cross-sectional view shown in comparison with FIG. Interlayer insulating film 19
Is almost completely flattened by mechanochemical polishing, so that the aluminum wiring 20 is formed without difficulty.
Significant improvement in yield is achieved. Although the present embodiment has mainly described the aluminum wiring, the effect does not change even if other metal wiring is used. Further, this mechanochemical polishing apparatus can simultaneously process a large number of wafers by using a normal mirror polishing apparatus for a silicon substrate. It doesn't come. As described above, by using the present invention,
There is an advantage that extremely good metal wiring can be realized. In addition, photolithography on a flattened surface has the effect that resist can be applied to a uniform thickness, so that the dimensions can be miniaturized at the same time. is there.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a process sectional view showing one embodiment of the present invention. FIG. 2 is a sectional view of a semiconductor device obtained by a manufacturing method according to one embodiment of the present invention. FIG. 3 is a sectional view of a conventional example. [Description of Reference Numerals] 17 First interlayer insulating film 18 First layer metal wiring 19 Second interlayer insulating film 20 Second layer metal wiring

Claims (1)

(57) [Claims] In a method of manufacturing a semiconductor device in which three or more layers of wiring are formed on a semiconductor substrate, mechanochemical polishing is performed on each of the interlayer insulating films that insulate between the wirings of each layer to flatten the surface of each interlayer insulating film. A method for manufacturing a semiconductor device, comprising: 2. 2. The method according to claim 1, wherein each of the three or more wiring layers is a metal wiring. 3. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a wiring made of a semiconductor is further formed between the first metal wiring and the semiconductor substrate. 4. Each of the interlayer insulating films is formed of a silicon oxide film, and the mechanochemical polishing is performed using silica (SiO 2).
4. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed by using the abrasive grains of 2).