JPH07122060A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize the higher speed of the semiconductor device of a pipeline system by decreasing the load to be connected to a synchronizing signal. CONSTITUTION:A decoding connection switch 29 for connecting a column decoder 1 and a column switch 2 is divided and only the necessary parts are driven. Then, transistors connected to one decoding connection signal are reduced to 1/N the number of the conventional devices and high-speed driving is possible. Since the load to be charged and discharged in one cycle is reduced to 1/N, the current consumption is reduced to 1/N.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, logical LS such as microprocessors has been used.
As for I, the one whose operating frequency exceeds 100 MHz has been put into practical use due to the progress of speeding up. On the other hand, the operation speed of semiconductor memory devices, especially dynamic random access memories, cannot be said to be sufficiently high, and there is an increasing demand for semiconductor memory devices that can be accessed at high speed. Synchronous DRAM, etc.) has been developed. A pipeline method has been proposed as a method of realizing such a semiconductor memory device capable of high-speed sequential access.

FIG. 4 shows the configuration of a conventional pipeline type semiconductor memory device. The operation will be described with reference to the drawings. First, a column address is input to the column decoder 1 from the address buffer or the address counter 8 and decoded by the control signal ICLK1. Next, the decode signal is connected to the selection transistor 6 by the control signal ICLK2 and simultaneously latched by the decode signal latch means, and after being latched, the control signal ICL is supplied.
The column decoder 1 and the column switch 2 are separated by K2. The output of the sense amplifier 3 is connected to the read bus 4 by the selection transistor 6 and amplified by the main amplifier 9. The output of the main amplifier 9 is connected to the data latch 10 by the control signal ICLK3, latched and then disconnected. The data latched in the data latch 10 is output to the output terminal 12 by the output buffer 11. As described above, the read operation is performed by the control signals ICLK1 and ICL.
It is performed in synchronization with K2 and ICLK3.

[0004]

However, in the configuration shown in FIG. 4, the number of transistors connected to one control signal is large, and in particular, the same number of transistors as the number of column switches are connected to the control signal ICLK2. As a result, the load of the control signal ICLK2 increases and the driving speed decreases.
That is, the read operation speed and the operation frequency are lowered. As the storage capacity increases, the number of column switches further increases, which hinders the increase in the storage capacity and the further increase in speed.

The present invention solves the above-mentioned conventional problems, and an object thereof is to provide a large-capacity and high-speed semiconductor memory device by reducing the load of control signals.

[0006]

In order to solve the above problems, a semiconductor memory device of the present invention comprises a memory cell array,
A sense amplifier array including a plurality of sense amplifiers provided in the memory cell array; a multiple selection transistor that connects the output of the sense amplifier to a read bus; a column decoder that generates a decode signal that selects the multiple selection transistor; Decode signal connecting means for connecting the output of the column decoder to the select transistor by the decode connection signal, decode signal latching means for latching the decode signal connected to the select transistor by the decode signal connecting means, and decode signal latching means A decode signal reset means for resetting the latched decode signal by a decode reset signal is provided, and the selected decode signal connection means and the decode signal reset means are divided into N (N is an integer) group, and each group is divided into groups. A decode connection signal and a decode reset signal are provided for each group, and signal control means for activating the decode connection signal of the block including the decode signal selected by the column decoder and the decode reset signal of the block not including the decode signal are provided. It is a thing.

[0007]

According to the present invention, since only the decode connection signal including the selected decode signal is activated by the above structure, the load of the decode connection signal is reduced and high speed driving becomes possible. Moreover, since unnecessary decode connection signals are not activated, current consumption is also reduced.

[0008]

【Example】

(Embodiment 1) A semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention.

In FIG. 1, 1 is a column decoder, 2 is a decode signal latch means 7, and a decode reset means 2
8 is a column switch composed of 8 and a selection transistor 6, 3 is a sense amplifier row composed of SA1 to 8 sense amplifiers, 4 is a read bus, 5 is a clock control circuit, and 21
Is a memory cell array. Decode signal connection means 29
Are controlled by the decode connection signals C1 to C4, and the decode reset means 28 controls the decode reset signals R1 to R1.
Controlled by 4.

The operation of the semiconductor memory device configured as described above will be described below with reference to FIG. In the standby state where no sense amplifier is selected, all the decode connection signals C1 to C4 are not activated,
The decode reset signals R1 to R4 are all activated, and all the signals latched by the decode signal latch means 7 are in the non-selected state.

Next, the column decoder 1 generates a decode signal for selecting the sense amplifier. In this embodiment, a decode signal Y1 that selects the sense amplifier SA1 is generated. The control signal ICLK2 is applied to the clock control circuit 5.
Is inputted, the clock control circuit 5 inactivates the decode reset signal R1 for controlling the group of the decode reset means 28 including the decode signal Y1, and controls the group of the decode signal connecting means 29 including the decode signal Y1. The decode connection signal C1 is activated. As a result, Y1 is connected to the column switch 2 and latched by the decode signal latch means 7. After the decode signal Y1 is latched by the decode signal latch means 7, the decode connection signal C1 becomes inactive and the column switch 2 and the column decoder 1 are disconnected. Since the decode signal Y1 is latched in the column switch 2, the sense amplifier SA1
Is connected to the read bus 4 and read.

When the column decoder 1 is disconnected from the column switch 2, it decodes the address of the next cycle,
Decode signal is output. The case where Y2 is output in the next cycle will be described. Next cycle control signal IC
When LK2 is input to the clock control circuit 5, the clock control circuit 5 activates the inactive decode reset signal R1 and the decode connection signal C corresponding to the group of the decode signal connection means 29 including the decode signal Y2.
Activate 2. After Y2 is latched by the decode signal latch means 7, the decode connection signal C2 is deactivated to disconnect the column decoder 1 and the column switch 2. The data of the sense amplifier SA2 is output to the read bus 4 by the decode signal latched by the column switch 2.

By repeating the above operation, the data of each sense amplifier is read out to the read bus 4 at high speed.

As described above, according to this embodiment, the number of transistors connected to one decode connection signal is 1 / N of that in the conventional case, and it is possible to drive at high speed. Also,
Since the load charged / discharged in one cycle becomes 1 / N, the consumption current is reduced to 1 / N.

(Second Embodiment) A semiconductor memory device according to a second embodiment of the present invention will be described below with reference to the drawings. Second Embodiment FIG. 2 is a block diagram of a semiconductor memory device according to a second embodiment of the present invention.

In FIG. 2, 1 is a column decoder, 2 is a decode signal latch means 7, a decode reset means 28,
Column switch composed of select transistor 6, 3
Is a sense amplifier row consisting of sense amplifiers SA1 to SA4
Is a read bus, and 5 is a clock control circuit. The decode signal connection means 29 is controlled by the decode connection signal CN, and the decode signal setting means 28 is controlled by the decode reset signal RN.

Reference numeral 1R is a spare column decoder, 2R is a spare column switch composed of a spare decode signal latch means 7R, a spare decode reset means 28R and a spare selection transistor 6R, and SAR is a spare sense amplifier. The preliminary decode signal connection means 29R is configured to decode the decode connection signal C.
Controlled by R, the decode signal reset means is controlled by the decode reset signal RR.

The operation of the semiconductor memory device configured as described above will be described below with reference to FIG.

In the standby state where no sense amplifier is selected, the decode connection signals CN and CR are not activated, the decode reset signals RN and RR are all activated, and the decode signal latch means 7 latches them. All the signals that have been selected are in the non-selected state.

Next, the column decoder 1 generates a decode signal for selecting the sense amplifier. Here, the case where the decode signal Y1 for selecting the sense amplifier SA1 is generated will be described. When the control signal ICLK2 is input to the clock control circuit 5, the clock control circuit 5
Deactivates the decode reset signal RN and activates the decode connection signal CN. As a result, Y1 is connected to the column switch 2 and latched by the decode signal latch means 7. After the decode signal Y1 is latched by the decode signal latch means 7, the decode connection signal CN becomes inactive and the column switch 2 and the column decoder 1 are disconnected. Since the decode signal Y1 is latched in the column switch 2, the output of the sense amplifier SA1 is connected to the read bus 4 and read. When the column decoder 1 is disconnected from the column switch 2, the column decoder 1 decodes the address of the next cycle and outputs a decode signal. Here, Y2 is output. Next cycle control signal IC
When LK2 is input to the clock control circuit 5, the clock control circuit 5 activates the decode connection signal CN. Y
After 2 is latched by the decode signal latch means, the decode connection signal CN is deactivated to disconnect the column decoder 1 and the column switch 2. The data of the sense amplifier SA2 is output to the read bus 4 by the decode signal latched by the column switch 2. By repeating the above operation, the data of each sense amplifier is read out to the read bus 4 at high speed.

On the other hand, when the spare circuit is used, the decode connection signal CN and the spare decode reset signal RR are inactive, and the spare decode connection signal CR and the decode reset signal RN are activated. Here, the case where the sense amplifier SA3 is replaced by the spare sense amplifier SAR will be described. When the column decoder 1 outputs the decode signal Y3, the spare decode signal YR is the spare decoder 1R.
Is output from. The control signal ICL is applied to the clock control circuit 5.
When K2 is input, the decode reset signal RN is activated when the spare circuit is used, and the decode signal latch means 7 is activated.
All decode signals latched at are deselected. Further, since the decode connection signal CN is not activated, the output Y3 of the column decoder 1 is not connected to the column switch 2.

On the other hand, when the spare ICLK2 is input to the clock control circuit 5, the spare decode reset signal RR becomes inactive and the spare decode connection signal CR is activated,
The preliminary decode signal YR is connected to the preliminary column switch 2R and latched by the preliminary decode signal latch means 7R. After the preliminary decode signal YR is latched by the preliminary decode signal latch means 7R, the preliminary decode connection signal CR is deactivated and the spare column decoder 1R and the spare column switch 2R are disconnected. Since the preliminary decode signal YR is latched in the preliminary decode signal latch means 7R, the preliminary select transistor 6R allows the preliminary sense amplifier SAR to operate.
Is connected to the read bus 4 and read.

By the above operation, the sense amplifier SA3 selected by Y3 is replaced with the spare sense amplifier SAR.

As described above, according to the present embodiment, the normal circuit and the spare circuit can be switched at a portion after the column decoder, so that the preliminary determination time does not slow down the column decoding speed and the high-speed reading is performed. Is possible.

(Embodiment 3) A semiconductor memory device according to a third embodiment of the present invention will be described below with reference to the drawings. Third Embodiment FIG. 3 is a block diagram of a semiconductor memory device according to a third embodiment of the present invention.

In FIG. 3, 1 is a column decoder, 2 is a decode signal latch means 7, and a decode reset means 2
8, a column switch composed of a selection transistor 6, 3 a sense amplifier row composed of sense amplifiers SA1 to SA, 4 a read bus, 1R a spare column decoder, 2
R is a spare column switch composed of a spare decode signal latch means 7R, a spare decode reset means 28R, and a spare selection transistor 6R, and 3R is a spare sense amplifier S.
A spare sense amplifier string 5 composed of A1R to 4R is a clock control circuit. The decode signal connection means 29 and the spare decode signal connection means 29R are connected to the decode connection signals C1 to
4 and the decode reset means 28 and the preliminary decode reset means 28R are controlled by the decode reset signals R1 to R4.

The operation of the semiconductor memory device configured as described above will be described below with reference to FIG.

In the standby state in which none of the sense amplifiers is selected, all the decode connection signals C1 to C4 are not activated, the decode reset signals R1 to R4 are all activated, and the decode signal latch means 7 is provided. All the signals latched by the preliminary decode signal latch means 7R are in the non-selected state.

Next, the column decoder 1 generates a decode signal for selecting the sense amplifier. Here, it is assumed that the decode signal Y1 that selects the sense amplifier SA1 is generated. Control signal IC for the clock control circuit 5
When LK2 is input, the clock control circuit 5 inactivates the decode reset signal R1 for controlling the group of the decode reset means 28 including the decode signal Y1, and controls the group of the decode signal connecting means 29 including the decode signal Y1. The decode connection signal C1 is activated. As a result, Y1 is connected to the column switch 2 and latched by the decode signal latch means 7. After the decode signal Y1 is latched by the decode signal latch means 7, the decode connection signal C1 becomes inactive and the column switch 2 and the column decoder 1 are disconnected. Since the decode signal Y1 is latched in the column switch 2, the sense amplifier SA
The output of 1 is connected to the read bus 4 and read.
When the column decoder 1 is disconnected from the column switch 2, the column decoder 1 decodes the address of the next cycle and outputs a decode signal. Here, Y2 is output. When the control signal ICLK2 of the next cycle is input to the clock control circuit 5, the clock control circuit 5 activates the inactive decode reset signal R1 and corresponds to the group of decode signal connecting means including the decode signal Y2. The decoded connection signal C2 is activated. After Y2 is latched by the decode signal latch means 7, the decode connection signal C
2 inactive, column decoder 1 and column switch 2
Disconnect. The data of the sense amplifier SA2 is output to the read bus 4 by the decode signal latched by the column switch 2. By repeating the above operation, the data of each sense amplifier is read out to the read bus 4 at high speed.

Next, a case where a defective column is replaced with a spare circuit will be described. When replacing a defect with a spare, it is replaced with a spare in a group other than the group containing the defect to be replaced. For example, when the column corresponding to Y3 is replaced, Y3 is included in the group controlled by C3 and R3, and therefore the spare to be replaced uses a group other than the group controlled by C3 and R3. Here, C1, R1
An example of replacing with the spare Y1R controlled by the above will be described.

When an address for selecting Y3 is input to the column decoder 1, the column decoder 1 outputs the decode signal Y.
3 and a preliminary decode signal Y1R. Next, when the control signal ICLK2 is input to the clock control circuit 5, the decode reset signal R which has been inactive in the previous cycle.
2 is activated and R1 is deactivated. Next, the decode connection signal C1 is activated, and the column decoder 1, the spare column decoder 1R and the column switch 2 are connected. At this time, the column decoder 1 and the spare column decoder 1R
Outputs Y3 and Y1R, the decode signal Y3 is not connected to the column switch 2 and only Y1R is connected to the spare column switch 2R. The following operation is the same as the normal operation.

As described above, according to this embodiment, the number of transistors connected to one decode connection signal is 1 / N of that in the conventional case, and it is possible to drive at high speed. Also,
Since the load charged / discharged in one cycle becomes 1 / N, the consumption current is reduced to 1 / N. Further, since the signal line for controlling the spare circuit for relieving the defect is common to the signal line for controlling the normal circuit, the number of wires is not increased, and the spare circuit and the spare circuit are provided after the column decoder. Since the circuits can be switched, high-speed reading can be performed without delaying the column decoding speed in the preliminary determination time.

[0033]

As described above, according to the present invention, the number of transistors connected to one decode connection signal is 1 / N of that in the conventional case, and it is possible to drive at high speed. Also,
Since the load charged / discharged in one cycle becomes 1 / N, the consumption current is reduced to 1 / N. Further, by performing redundancy switching with the decode connection signal, high-speed reading can be performed without delaying the column decoding speed in the preliminary determination time. Further, since the decode connection signal is commonly used by the normal circuit and the spare circuit, the number of wirings does not increase.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional semiconductor memory device.

[Explanation of symbols]

 1 Column Decoder 2 Column Switch 3 Sense Amplifier 4 Readout Bus 5 Signal Control Circuit 6 Select Transistor 7 Decode Signal Latch Means 28 Decode Reset Means SA1-8 Sense Amplifiers

Claims (3)

[Claims] 1. A memory cell array, a sense amplifier array including a plurality of sense amplifiers provided in the memory cell array, a multi-select transistor for connecting an output of the sense amplifier to a read bus, and a decode for selecting the multi-select transistor. A column decoder for generating a signal, a decode signal connecting means for connecting an output of the column decoder to a select transistor by a decode connecting signal, and a decode signal latch for latching the decode signal connected by the decode signal connecting means to the select transistor Means and a decode signal reset means for resetting the decode signal latched by the decode signal latch means by a decode reset signal, and the selected decode signal connecting means and the decode signal reset means are N (N is (Integer) group, each of the groups is provided with a decode connection signal and a decode reset signal, and a decode connection signal of a block including a decode signal selected by the column decoder and a decode reset of a block not including the decode signal A semiconductor memory device comprising a signal control means for activating a signal. 2. A spare memory cell array, a spare sense amplifier array provided in the spare memory cell array, a spare selection transistor connecting an output of the spare sense amplifier array to the read bus, and the spare selection transistor. A spare column decoder for generating a spare decode signal, a spare decode signal connecting means for connecting an output of the spare column decoder to a spare select transistor by a spare decode connection signal, and a spare decode signal connecting means for connecting the spare decode transistor to the spare select transistor. A preliminary decode signal latching means for latching the preliminary decode signal, a preliminary decode signal reset means for resetting the preliminary decode signal latched by the preliminary decode signal latch means by a preliminary decode reset signal, and a spare decode signal when the spare is not used. Has signal control means for activating the decode connection signal and the preliminary decode reset signal, and activating the preliminary decode connection signal and the decode reset signal when a spare is used. The semiconductor memory device according to claim 1. 3. The preliminary selection decode signal connection means and the preliminary decode signal reset means are divided into N groups (N is an integer), and a decode connection signal and a decode reset signal are provided for each group. 3. The semiconductor memory device according to claim 2, wherein the control means activates the decode connection signal of the block including the decode signal selected by the column decoder and the decode reset signal of the block not including the decode signal.