JPH07120720A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide the liquid crystal display device capable of completely compensating the fluctuation in the voltage applied to a liquid crystal. CONSTITUTION:A compensation voltage VCOM is applied via a terminal 3 to an electrode 9 of the liquid crystal 5. A regulating voltage VCS is applied via a terminal 12 to an electrode 11 of n auxiliary capacitance 6. A TFT 4 attains an on-state and a drain voltage VD is charged to the electrode 8 of the liquid crystal 5 and the electrode 10 of the auxiliary capacitance 6 until the voltage converges to a source voltage VS. The drain voltage VD intrinsically converged to the voltage VS fluctuates by receiving the influence of a coupling capacitance 7 when the TFT 4 attains an off-state but this influence is suppressed and the fluctuation is decreased to '0' by applying the prescribed regulation voltage VCS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a plurality of liquid crystal display pixels in which a gate of a thin film transistor (hereinafter referred to as "TFT") is connected to a scanning electrode line, a source is connected to a signal electrode line, and a drain is connected to a liquid crystal pixel electrode. And a TFT active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art FIG. 4 shows a circuit diagram of a liquid crystal display pixel of a conventional TFT active matrix type liquid crystal display device. The scanning electrode line Lg is arranged in the horizontal direction of the screen and is connected to the gate G of the TFT 4 of each liquid crystal display pixel. Signal electrode line L
s is arranged in the vertical direction of the screen and is the TF of each liquid crystal display pixel.
It is connected to the source S of T4. A gate voltage VG is applied to the terminal 2 from a gate driver (not shown), and this is supplied to the gate G of the TFT 4 through the scanning electrode line Lg.

The gate voltage VG of the TFT4 is "High".
When the voltage value at the h "level becomes VGH, the source S and the drain D
Is turned on and becomes an ON state as an analog switch. At this time, the drain voltage VD at the drain D becomes equal to the source voltage VS given to the terminal 1 from the source driver (not shown), and the electrode 8 of the liquid crystal 5 and the auxiliary capacitance. The electrode 10 of 6 is charged. Electrode 9 and auxiliary capacitance 6 of liquid crystal 5
The compensation voltage VCOM is applied to the electrode 11 via the terminal 3. In addition, 7 is a gate G and a drain D of the TFT 4.
C1, C2, and C3 are coupling capacitances existing between them, and are capacitance values of the liquid crystal 5, the auxiliary capacitance 6, and the coupling capacitance 7, respectively.

On the contrary, the TFT 4 has a gate voltage VG of "Lo".
When the voltage value VGL at the w "level is reached, the transistor is turned off. At this time, the source voltage VD charged as the drain voltage VD.
The phenomenon that the value of S fluctuates under the influence of the coupling capacitance 7 occurs.

Regarding this phenomenon, the liquid crystal 5, the auxiliary capacitance 6,
A circuit diagram equivalent to the circuit diagram of FIG. 4 for the coupling capacitor 7 and an equation for giving the charges Q1, Q2, and Q3 will be described with reference to FIG. In FIG. 5, the same components as those shown and described in FIG. Q1, Q2, and Q3 are electric charges stored in the liquid crystal 5, the auxiliary capacitance 6, and the coupling capacitance 7, respectively. The switch 4'means the TFT 4.

When the switch 4'is in the ON state, the drain voltage VD has completed the convergence of the source voltage VS to the voltage value (VD = VS). In addition, the gate voltage VG applied to the terminal 2 is the "High" level voltage value VGH.
(VG = VGH). At this time, the charges Q1, Q
2, Q3 can be expressed as the formula of FIG.
These sums are given by the following equation (C). Q1 + Q2 + Q3 = (C1 + C2) (VS-VCOM) + C3 (VS-VGH) (C)

The switch 4'is turned off when the gate voltage VG applied to the terminal 2 is "Lo".
This is because the voltage value becomes VGL at the w "level (VG = VG
L). At this moment, the value of the drain voltage VD, which has completely converged to the value of the source voltage VS, is actually fluctuating due to the influence of the coupling capacitance 7 (VD ≠ VS), and therefore the charges Q1 and Q are generated.
2, Q3 can be expressed by the formula of FIG.
These sums are given by the following equation (D). Q1 + Q2 + Q3 = (C1 + C2) (VD-VCOM) + C3 (VD-VGL) (D)

Even if the switch 4'is switched from the ON state to the OFF state, the sum of the charges Q1, Q2 and Q3 remains unchanged. Therefore, if the equations (C) and (D) in FIG. Is obtained. (C1 + C2 + C3) VS-C3 (VGH-VGL) = (C1 + C2 + C3) VD Therefore, .gamma. = C3 / (C1 + C2 + C3), .DELTA.VG = V
Putting it as GH-VGL, the following equation holds. VD = VS-γ · ΔVG (1)

Next, a timing chart of the liquid crystal display device driven as described above is shown in FIG. Figure 6
(A), (b) and (c) respectively have source voltages VS,
Drive waveforms of the gate voltage VG and the drain voltage VD are shown.
The source voltage VS is originally an analog signal or a digital signal having a plurality of gradations.
Or, it has only two values of + VSS.

At time a, the value of the source voltage VS in FIG. 6A rises from -VSS to + VSS, and at the same time, the gate voltage VG in FIG. 6B rises from VGL to VGH. At this time, the TFT4 is turned on and the capacitance C1,
Charging of C2 and C3 is started. Therefore, the drain voltage VD is low at the beginning of charging and increases with charging.
By the time a, the drain voltage VD converges to the voltage value + VSS of the source voltage VS as shown in FIG. 6C.

At time a, the value of the source voltage VS in FIG. 6A falls from + VSS to -VSS, and at the same time, the gate voltage VG in FIG. 6B falls from VGH to VGL. At this time, the TFT4 is turned off and the capacitors C1 and C
2, the charging of C3 is completed. At this moment, as shown in FIG. 6C, the value of the drain voltage VD decreases from the voltage value + VSS by a certain voltage value. Actually, this reduced voltage value becomes equal to γ · ΔVG in the equation (1), so that it is affected by the coupling capacitance 7 at this time a when inductively considered.
It is demonstrated that the value of the drain voltage VD drops by γ · ΔVG from the once converged voltage value + VSS so as to satisfy the expression (1), and the voltage (VSS−γ · ΔVG) is held in the electrode 8.

Even at the instant at time D after time C, the value of the drain voltage VD decreases from the once converged voltage value -VSS by a certain voltage value, as shown in FIG. 6C. Actually, this reduced voltage value is γ · ΔVG in equation (1)
Similarly, at this time d, the value of the drain voltage VD is affected by the coupling capacitance 7 and satisfies the equation (1).
Voltage, and the voltage (-VSS-γ · ΔVG) is applied to electrode 8
Demonstrated to be retained in. That is, at the moment when the TFT 4 is switched to the off state as at times a and d, the value of the drain voltage VD fluctuates from the once converged value of the source voltage VS by (-γ · ΔVG) as shown in the equation (1). (V
S −γ · ΔVG).

As a result, in the liquid crystal 5, the drain voltage VD = (VS-γ.ΔVG) is applied to one electrode 8 and the compensation voltage VCOM is applied to the other electrode 9, so that the difference (VD-VCO
M) = (VS−γ · ΔVG−VCOM) is the liquid crystal applied voltage V
It becomes an LCD, which determines the transmittance of the liquid crystal layer of the liquid crystal 5.

The maximum value of the capacitance C1 is 2 pF and the capacitance C2 is 7
It is assumed that the pF and the capacitance C3 are 1 pF. At this time, the liquid crystal 5
FIG. 7 is a graph showing the relationship between the capacitance C1, the transmittance T, and the liquid crystal applied voltage VLCD. Based on FIG. 7, the capacity ratio γ
FIG. 8 is a graph showing the relationship between the liquid crystal applied voltage VLCD and the liquid crystal.

From the calculation, when the capacitance C1 is 2 pF, the capacitance ratio γ
Is 0.1 because C3 / (C1 + C2 + C3), and the capacitance ratio γ is 0.125 when the capacitance C1 is 0 pF. In other cases, the graph of FIG. 8 can be drawn based on FIG. 7. it can. Maximum gate voltage VGH is 10
Assuming that V is V and the minimum value VGL is -10V, the difference ΔVG is 2
Since it is 0V, the maximum value of γ · ΔVG is 2.5V,
The minimum value is 2V.

The value of the liquid crystal applied voltage VLCD (= VD-VCOM) is (VS-γ.ΔVG-VCOM). If the compensation voltage VCOM is inadvertently grounded and set to 0V, the maximum value that the liquid crystal applied voltage VLCD can take is (VSS−γ · ΔVG) (point X in FIG. 7), and the maximum value of the transmittance T is originally 90% of the maximum value is obtained and the contrast is lowered.

Therefore, in order to widen the selection range of the transmittance T of the liquid crystal layer of the liquid crystal 5, it is necessary to always make the liquid crystal applied voltage VLCD equal to the source voltage VS (maximum value VSS, minimum value −VSS) ( Point Y in FIG. 7). Therefore, the compensation voltage VCO
The value of M is preset as a constant voltage value (-2.0 V in FIG. 8) equal to -γΔVG to prevent the influence of the fluctuation of the drain voltage VD on the image.

[0018]

However, the compensation voltage VCO
The value of M is preset to a constant voltage value (-γ · ΔVG),
Even if the value of the liquid crystal applied voltage VLCD is made equal to the source voltage VS by setting the term of (-γΔVG-VCOM) to "0", the capacitance C1 of the liquid crystal 5 during operation is as shown in FIG. The value of the capacitance ratio γ also fluctuates as shown in FIG. 8 in tandem with the change to, and the value of the liquid crystal applied voltage VLCD does not always become equal to the source voltage VS, so complete compensation is not possible. It will be possible. Furthermore, since the fluctuation of the drain voltage VD (-γ · ΔVG) remains for one field period, in the case of a digital image, "image sticking" may occur in the image.
Development occurs, and the reliability of the image of each display pixel becomes low only by the above measures.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a liquid crystal display device capable of completely compensating for fluctuations in the voltage applied to the liquid crystal.

[0020]

To achieve the above object, in a liquid crystal display device of the present invention, a gate and a source are respectively connected to a scanning electrode line and a signal electrode line, and a drain is connected to a liquid crystal and one electrode of an auxiliary capacitor. A plurality of liquid crystal display pixels having thin film transistors connected to each other are arranged in a matrix, and an adjustment voltage is generated in synchronization with a gate voltage for sequentially selecting and driving scan electrode lines, and the adjustment voltage is generated by the auxiliary capacitor. Is applied to the other electrode of.

Further, the adjustment voltage is changed so as to compensate for a drain voltage variation due to a gate-drain coupling capacitance at the time of selection as compared with that at the time of non-selection. Alternatively, the other electrode of the liquid crystal is grounded, and when the adjustment voltage is selected as compared with the non-selected time, the gate voltage variation and (-1) are added to the ratio of the gate-drain coupling capacitance to the auxiliary capacitance. It is characterized in that it varies only by the multiplied value.

[0022]

By doing so, it is possible to completely compensate the liquid crystal applied voltage which fluctuates under the influence of the coupling capacitance between the gate and drain of the thin film transistor.

[0023]

1 is a circuit diagram of a liquid crystal display pixel of a TFT active matrix type liquid crystal display device embodying the present invention. In FIG. 1, the same parts as those shown in FIG. 4 and described in the conventional example are designated by the same reference numerals, and the description thereof will be omitted.

In the TFT 4, the gate voltage VG has a voltage value VGH.
Will be turned on. At this time, drain voltage VD
Becomes equal to the source voltage VS, and the electrode 8 of the liquid crystal 5 and the electrode 10 of the auxiliary capacitance 6 are charged. At the same time, terminal 1
The adjustment voltage VCS applied from the drive circuit (not shown) to the electrode 11 of the auxiliary capacitance 6 via 2 falls to the voltage value VCSL of "Low" level. In addition, the electrode 9 of the liquid crystal 5 is
The compensation voltage VCOM is applied via the terminal 3.

On the contrary, the TFT 4 is turned off when the gate voltage VG reaches the voltage value VGL, and the adjustment voltage VCS is adjusted so that the value of the drain voltage VD converged to the source voltage VS is not affected by the coupling capacitance 7. Is raised to the "High" level voltage value VCSH. The fluctuation .DELTA.VCS of the adjustment voltage VCS at this time is (VCSH-VCSL).

The reason why the coupling capacitance 7 is not affected if the adjustment voltage VCS is changed is as follows. With respect to the liquid crystal 5, the auxiliary capacitance 6, and the coupling capacitance 7, a circuit diagram equivalent to the circuit diagram of FIG.
And equations for giving the charges Q1, Q2, Q3 are shown in FIG. 2 and will be described. In FIG. 2, the same components as those shown and described in FIGS. 1 and 5 are designated by the same reference numerals and the description thereof will be omitted.

When the switch 4'is in the ON state, the drain voltage VD converges to the value of the source voltage VS (VD =
VS). In addition, the gate voltage VG applied to the terminal 2
Has a voltage value VGH (VG = VGH). The adjustment voltage VCS applied to the terminal 12 has a voltage value VCSL of "Low" level (VCS = VCSL). At this time,
The charges Q1, Q2, and Q3 can be expressed as in the equation of FIG. 2A, and the sum of these is given by the following equation (A). Q1 + Q2 + Q3 = C1 (VS-VCOM) + C2 (VS-VCSL) + C3 (VS-VGH) (A)

The switch 4'is turned off when the gate voltage VG applied to the terminal 2 is "Hi".
This is because the voltage value becomes VGL at the gh "level (VG = VGL). Also, the adjustment voltage VCS applied to the terminal 12
Has a "High" level voltage value VCSH (VCS = VCSH). At this moment, the source voltage VS
Since the value of the drain voltage VD that has completed the convergence to the value of is actually changing due to the influence of the coupling capacitance 7 (VD ≠ VS),
The charges Q1, Q2, and Q3 can be expressed as in the formula of FIG. 2B, and the sum of these is given by the following formula (B). Q1 + Q2 + Q3 = C1 (VD-VCOM) + C2 (VD-VCSH) + C3 (VD-VGL) (B)

When the switch 4'is switched from the ON state to the OFF state, the sum of the charges Q1, Q2 and Q3 is invariable, so that if the equations (A) and (B) are equal, the following equation is obtained. (C1 + C2 + C3) VS-C3 (VGH-VGL) + C2
(VCSH-VCSL) = (C1 + C2 + C3) VD Therefore, γ = C3 / (C1 + C2 + C3), α = C2 /
(C1 + C2 + C3), ΔVG = VGH-VGL, ΔVCS =
Putting it as VCSH-VCSL, the following equation holds. VD = VS-γ-ΔVG + α-ΔVCCS (2)

Next, FIG. 3 shows a timing chart in the liquid crystal display device driven as described above. Figure 3
Drive waveforms of the source voltage VS, the gate voltage VG, the adjustment voltage VCS, and the drain voltage VD are shown in (a), (b), (c), and (d), respectively. In FIG. 3, the source voltage VS
Is originally an analog signal or a digital signal having a plurality of gradations, but for simplicity, it is assumed that it has only two values of -VSS or + VSS.

At time a, the value of the source voltage VS shown in FIG. 3A rises from -VSS to + VSS, and the value shown in FIG.
Also the gate voltage VG of VGL rises from VGL to VGH, and at the same time, the adjustment voltage VCS of FIG. 3C falls from VCSH to VCSL. At this time, the TFT4 is turned on and the capacitance C
1, C2 and C3 start charging, and after a while, the drain voltage VD converges to the value + VSS of the source voltage VS as shown in FIG. 3 (d).

At time a, the value of the source voltage VS in FIG. 3A falls from + VSS to -VSS, and FIG.
Gate voltage VG of VGH falls from VGH to VGL, and at the same time, the adjustment voltage VCS of FIG. 3 (c) rises from VCSL to VCSH. At this time, the TFT4 is turned off and the capacitance C1,
Charging ends for C2 and C3.

At this moment, the value of the drain voltage VD once influenced by the coupling capacitance 7 and converged to the voltage value + VSS is (2)
Varying so as to satisfy the formula (VSS-γ · ΔVG + α · Δ
VCS). Here, (−γ · ΔVG + α · ΔV
ΔCS (= VCSH-VCS) so that the term of CS) becomes “0”
L) is set and the adjusted voltage VCS (maximum value VCS
If H and the minimum value VCSL are generated, even if the value of the drain voltage VD fluctuates, (VSS−γ · ΔVG + α · Δ)
(VCS) can remain equal to + VSS as in Figure 3 (d).

Even at the instant at time D after time C, the value of the drain voltage VD which has once converged to the voltage value -VSS fluctuates so as to satisfy the equation (2) (- VSS-γ · ΔVG + α · ΔVCs).
Similarly, if the adjustment voltage VCS is generated, even if the value of the drain voltage VD fluctuates, (VSS−γ · ΔVG +
.alpha..multidot..DELTA.VCS) can remain equal to -VSS as shown in FIG.

As a result, the drain voltage VD (= VS-γΔVG + αΔVCS) is applied to one electrode 8 of the liquid crystal 5 and the compensation voltage VCOM is applied to the other electrode 9, so that the difference ( VD-VCOM) = (VS-γ ・ ΔVG + α
.DELTA.VCS-VCOM) becomes the liquid crystal applied voltage VLCD, which determines the transmittance of the liquid crystal layer of the liquid crystal 5.

Assuming that the setting of the compensation voltage VCOM is 0V, the value of the liquid crystal applied voltage VLCD is (VS-γΔVG +
α ・ ΔVCS). Further, the value of the capacitance ratio γ changes in a chain when the capacitance C1 of the liquid crystal 5 changes, but (−γ · ΔV
The adjustment voltage VCS (maximum value VCSH, minimum value VCSL) can be easily generated based on ΔVCS that satisfies the following expression (3) in which the term of G + α · ΔVCS is “0”. ΔVCS = (γ / α) · ΔVG = (C3 / C2) · ΔVG (3) This adjustment voltage VCS is synchronized with the gate voltage VG of FIG. 3B as shown in FIG. When the voltage is applied to the electrode 11 of No. 6, the liquid crystal applied voltage VLCD can always be made exactly equal to the source voltage VS.

Therefore, unlike the conventional drain voltage VD shown in FIG. 6C, the fluctuation of γΔVG does not remain for one field period and the "image sticking" phenomenon does not occur. The maximum and minimum values that the liquid crystal applied voltage VLCD can take are VSS and -VSS, respectively (see FIG. 7).
Point Y) and the transmittance T can be set to 100%, which is the maximum. Further, in order to widen the selection range of the transmittance T of the liquid crystal layer of the liquid crystal 5, another compensation voltage VCOM of a certain voltage value applied to the electrode 9 of the liquid crystal 5 is generated and the value is set constant. No ingenuity is required.

Next, a block circuit diagram of a TFT active matrix type liquid crystal display device in which a plurality of liquid crystal display pixels described above are arranged in a matrix is shown in FIG. 9, and a time chart at this time is shown in FIG. The method will be described. As shown in FIG. 9, a plurality of liquid crystal display pixels are arranged on one scanning electrode line Lg in the horizontal direction to form one scanning line, and further, the scanning lines are arranged in the plurality of vertical directions to form one screen. .

In FIG. 9, all the electrodes 11 of the auxiliary capacitors 6 of the plurality of liquid crystal display pixels arranged on the i-th scanning line from the top are connected to the terminal 12 (i). Further, all the electrodes 11 of the auxiliary capacitor 6 of the plurality of liquid crystal display pixels arranged on the (i + 1) th and (i + 2) th scanning lines from the top are also 1
It is connected to 2 (i + 1) and 12 (i + 2), and so on. The compensating voltage VCOM is applied to the electrodes 9 of the liquid crystal 5 of all the liquid crystal display pixels from the driving circuit (not shown) via the terminal 3. The compensation voltage VCOM can be set to 0V for the sake of simplicity. The source driver 13 applies the source voltage VS shown in FIG. 10A to the signal electrode line Ls via the terminal 1.

The gate driver 14 is provided with each scanning electrode line Lg.
Gate voltages VG (i), VG (i + 1) and VG (i + 2) synchronized with the source voltage VS are given to (i), Lg (i + 1) and Lg (i + 2), respectively. As shown in FIGS. 10B, 10C, and 10D, each of the gate voltages VG (i), VG (i + 1), and VG (i + 2) is
The pulse period is sequentially switched every one horizontal scanning period (1H), and each scanning electrode line Lg (i), Lg (i + 1), Lg (i + 2)
Are sequentially driven from above. Similarly, the other scan electrode lines are sequentially driven.

The drive circuit (not shown) is controlled by the gate voltage VG.
In synchronism with (i), as shown in FIG. 10 (e), an adjustment voltage VCS (i) satisfying the equation (3) is generated, and this is generated at the terminal 12
The voltage is applied to the electrodes 11 of the auxiliary capacitors 6 in the plurality of liquid crystal display pixels arranged on the i-th scanning line from the top via (i). Subsequently, the drive circuit (not shown) similarly synchronizes with each of the gate voltages VG (i + 1) and VG (i + 2), as shown in FIG.
As shown in (f) and (g), the adjustment voltages VCS (i + 1) and VCS (i + 2) satisfying the equation (3) are respectively generated, and these are respectively generated at terminals 12 (i + 1) and 12 (i). The voltage is applied to the electrodes 11 of the auxiliary capacitors 6 in the plurality of liquid crystal display pixels arranged on the (i + 1) th and (i + 2) th scanning lines from the top via (i + 2). As a result, FIG. 10 (h), (i), (j)
, The drain voltages VD (i), VD (i + 1), VD (i +
Each of 2) sequentially converges to the source voltage VS every horizontal scanning period. Similarly, in other liquid crystal display pixels, the drain voltage VD converges to the source voltage VS.

[0042]

As described above, according to the present invention, T
Since the drain voltage converged to the source voltage does not change under the influence of the coupling capacitance between the gate and drain of the TFT when the FT is off, the image sticking phenomenon does not occur and the display quality is improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a liquid crystal display pixel of a TFT active matrix type liquid crystal display device embodying the present invention.

FIG. 2 is a circuit diagram of a liquid crystal display pixel of a TFT active matrix type liquid crystal display device embodying the present invention and a charge Q1;
The figure which shows the formula which gives Q2 and Q3.

FIG. 3 is a diagram showing a timing chart in a liquid crystal display pixel of a TFT active matrix type liquid crystal display device embodying the present invention.

FIG. 4 is a circuit diagram of a liquid crystal display pixel of a conventional TFT active matrix type liquid crystal display device.

FIG. 5 is a circuit diagram of a liquid crystal display pixel of a conventional TFT active matrix liquid crystal display device and charges Q1, Q2, Q3.
The figure which shows the formula which gives.

FIG. 6 is a diagram showing a timing chart in a liquid crystal display pixel of a conventional TFT active matrix liquid crystal display device.

FIG. 7 is a graph showing the relationship between the capacitance C1, the transmittance T, and the liquid crystal applied voltage VLCD.

FIG. 8 is a graph showing the relationship between the capacitance ratio γ and the liquid crystal applied voltage VLCD.

FIG. 9 is a block circuit diagram of a TFT active matrix type liquid crystal display device embodying the present invention.

FIG. 10 is a diagram showing a timing chart in a TFT active matrix type liquid crystal display device embodying the present invention.

[Explanation of symbols]

 1 terminal 2 terminal 3 terminal 4 TFT G gate S source D drain 4'switch 5 liquid crystal 6 auxiliary capacitance 7 coupling capacitance 8 electrode 9 electrode 10 electrode 11 electrode 12 terminal 13 source driver 14 gate driver VS source voltage (maximum VSS, minimum) Value -VSS) VG Gate voltage VD Drain voltage VCS Adjustment voltage VCOM Correction voltage VLCD Liquid crystal applied voltage VGH Gate voltage ("High" level) VGL Gate voltage ("Low" level) ΔVG = VGH-VGL VCSH Adjustment voltage ("High") Level) VCSL adjustment voltage (“Low” level) ΔVCS = VCSH-VCSL C1, C2, C3 Capacitance a, a, u, d Time T Transmittance γ Capacitance ratio γΔVG Drain voltage fluctuation

Claims (3)

[Claims] 1. A gate and a source are respectively provided with a scanning electrode line,
In a liquid crystal display device in which a plurality of liquid crystal display pixels each having a thin film transistor connected to a signal electrode line and having a drain connected to one electrode of a liquid crystal and an auxiliary capacitor are arranged in a matrix, a gate voltage for sequentially selecting and driving scanning electrode lines A liquid crystal display device comprising: a circuit that generates an adjustment voltage in synchronization with the control voltage and applies the adjustment voltage to the other electrode of the auxiliary capacitor. 2. The liquid crystal display according to claim 1, wherein the adjustment voltage is changed so as to compensate for a drain voltage variation due to a gate-drain coupling capacitance when the selection voltage is selected, as compared with a non-selection voltage. apparatus. 3. The other electrode of the liquid crystal is grounded, and when the adjustment voltage is selected as compared with the non-selected state, the ratio of the gate voltage fluctuation amount to the ratio of the gate-drain coupling capacitance to the auxiliary capacitance and (- The liquid crystal display device according to claim 1, wherein the liquid crystal display device varies by a value obtained by multiplying 1).