CN107845364A

CN107845364A - Pixel compensation circuit and display device

Info

Publication number: CN107845364A
Application number: CN201610832039.9A
Authority: CN
Inventors: 周兴雨
Original assignee: EverDisplay Optronics Shanghai Co Ltd
Current assignee: EverDisplay Optronics Shanghai Co Ltd
Priority date: 2016-09-19
Filing date: 2016-09-19
Publication date: 2018-03-27
Anticipated expiration: 2036-09-19
Also published as: CN107845364B

Abstract

The invention provides pixel compensation circuit and display device, wherein pixel compensation circuit includes the first transistor, second transistor, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor, the 9th transistor, the tenth transistor, the 11st transistor, the tenth two-transistor, light emitting diode and capacitor.The pixel compensation circuit of the present invention to the voltage of voltage source because the resistance of cabling and caused pressure drop compensates, so that the driving current of OLED display device is not influenceed by the voltage of voltage source in pressure drop caused by display panel, reduce the deviation of the driving current value and the driving current value currently set at the diverse location of display panel as far as possible, the brightness uniformity of display panel is improved, lifts the viewing experience of user.

Description

Pixel compensation circuit and display device

Technical field

The present invention relates to display control circuit field, particularly a kind of voltage of compensating voltage source exists because of the resistance of cabling The pixel compensation circuit and display device of caused pressure drop in display panel.

Background technology

Recently, developed has the various FPD of lower weight and volume compared with cathode-ray tube display Device includes liquid crystal display, Field Emission Display, plasma display and OLED.

In flat-panel monitor, OLED uses the organic light emission that light is produced by the restructuring in electronics and hole Diode (OLED) display image.OLED is had faster response speed and driven with relatively low power consumption.One Transistor electric current to OLED offer according to data-signal of the individual typical OLED by formation within the pixel, from And OLED transmitting light extractions.

OLED makes a distinction according to driving type, can be divided into passive driving types (PMOLED) and active drive Ejector half (AMOLED), wherein passive driving types do not use thin film transistor base plate, and active-drive then uses thin film transistor (TFT) base Plate.

It is brilliant that each pixel of the OLED of active matrix driving is equipped with the low-temperature polysilicon film with switching function Body pipe, and each pixel is equipped with a charge storage capacitance, and peripheral drive circuit and display module are integrated in same glass base On plate.Each data-signal of pixel basis one produces a driving current, by adjust the driving current of Organic Light Emitting Diode come Control the brightness of Organic Light Emitting Diode.

In the drive circuit of existing AMOLED display modules, because AMOLED relies on electric current driving, so providing voltage The voltage in source can produce pressure drop because of the resistance of cabling in display panel, so as to cause AMOLED display panel in upper Under voltage it is different.Again because the brightness of Organic Light Emitting Diode is directly proportional to its amount of drive current, AMOLED display panel Voltage it is uneven, the brightness irregularities of display panel can be caused.With cabling chronological aging in display panel, cabling portion The resistance divided can be raised further, and the uneven situation of voltage will become more apparent in display panel, so as to cause display panel Brightness irregularities degree is further deepened, and also just reduces the service life of AMOLED display panels, influences the viewing body of user Test.

The above- mentioned information disclosed in the background section is merely to promote the understanding to background of invention, therefore It is possibly comprised in this country's information that is unknown to those skilled in the art, not forming prior art.

The content of the invention

For in the prior art the defects of, it is an object of the invention to provide a kind of pixel compensation circuit and display dress Put, the shortcomings that overcoming prior art, the voltage to voltage source because the resistance of cabling and caused pressure drop compensates, improve Brightness uniformity.

According to an aspect of the present invention, there is provided a kind of pixel compensation circuit, including：

One the first transistor, the first pole of the first transistor couple a data-signal, and the second pole couples a first segment Point, grid couple one second scanning signal；

One second transistor, the first pole of the second transistor couple the first node, the second pole coupling one second Node, grid couple a fourth node；

One first switch component, the first end of the first switch component couple the section point, the second end coupling institute Fourth node is stated, control terminal couples second scanning signal；

One the 5th transistor, the first pole of the 5th transistor couple the section point, the second pole coupling one the 3rd Node, grid couple an enable signal；

One the 6th transistor, the first pole of the 6th transistor couple the first node, and the second pole couples a voltage Source positive pole, grid couple the enable signal；

The tenth transistor, the first pole of the tenth transistor couple the voltage source positive pole, the second pole coupling 1 the Five nodes, grid couple the enable signal；

The 11st transistor, the first pole of the 11st transistor couple the 5th node, the second pole coupling one Reference voltage, grid couple one first scanning signal；

One capacitor, the first end of the capacitor couple the 5th node, and the second end couples the fourth node；

One light emitting diode, the positive pole of the light emitting diode couple the 3rd node, and negative pole couples a voltage source and born Pole.

Preferably, the first transistor, second transistor, the 5th transistor, the 6th transistor, the tenth transistor and 11 transistors are PMOS transistor.

Preferably, the first switch component includes a third transistor and one the 4th transistor, wherein：

First pole of the third transistor couples the section point, described in the second pole coupling of the third transistor First pole of the 4th transistor, the second pole of the 4th transistor couple the fourth node, the third transistor and the The grid of four transistors couples second scanning signal.

Preferably, the third transistor and the 4th transistor are PMOS.

Preferably, in addition to a second switch component, the first end of the second switch component couple an initializing signal, Second end couples the fourth node, and control terminal couples first scanning signal.

Preferably, the second switch component includes one the 7th transistor and one the 8th transistor, wherein：

First pole of the 7th transistor couples the initializing signal, the second pole coupling institute of the 7th transistor State the first pole of the 8th transistor, the second pole of the 8th transistor couples the fourth node, the 7th transistor and The grid of 8th transistor couples first scanning signal.

Preferably, in addition to one the 9th transistor, the first pole of the 9th transistor couples the 3rd node, and second Pole couples the initializing signal, and grid couples first scanning signal.

Preferably, the 7th transistor, the 8th transistor and the 9th transistor are PMOS.

Preferably, in addition to 1 the tenth two-transistor, the first pole of the tenth two-transistor couple the 5th node, Second pole couples the reference voltage, and grid couples second scanning signal.

Preferably, the tenth two-transistor is PMOS.

According to another aspect of the present invention, a kind of display device, including above-mentioned pixel compensation circuit are also provided.

Compared with prior art, due to having used above technology, pixel compensation circuit and display device in the present invention, To the voltage of voltage source because the resistance of cabling and caused pressure drop compensates so that the driving current of OLED display device is not Influenceed by the voltage of voltage source in pressure drop caused by display panel, reduce the driving at the diverse location of display panel as far as possible The deviation of current value and the driving current value currently set, the brightness uniformity of display panel is improved, lift the viewing body of user Test.

Brief description of the drawings

The detailed description made by reading with reference to the following drawings to non-limiting example, further feature of the invention, Objects and advantages will become more apparent upon：

Fig. 1 is the circuit diagram of the pixel compensation circuit of the present invention；

Fig. 2 is the drive waveforms figure of the pixel compensation circuit of the present invention；

Fig. 3 is the conducting state schematic diagram of the pixel compensation circuit in A stages in Fig. 2；

Fig. 4 is the conducting state schematic diagram of the pixel compensation circuit of B-stage in Fig. 2；

Fig. 5 is the conducting state schematic diagram of the pixel compensation circuit of C-stage in Fig. 2；

Fig. 6 is the conducting state schematic diagram of the pixel compensation circuit in D stages in Fig. 2；

Fig. 7 is the conducting state schematic diagram of the pixel compensation circuit of E-stage in Fig. 2；

In the schematic diagram of different voltage, currents change when Fig. 8 is the pixel compensation circuit not using the present invention；

Fig. 9 is using the schematic diagram changed after pixel compensation circuit of the invention in different voltage, currents.

Reference

M1 the first transistors

M2 second transistors

M3 third transistor

The transistors of M4 the 4th

The transistors of M5 the 5th

The transistors of M6 the 6th

The transistors of M7 the 7th

The transistors of M8 the 8th

The transistors of M9 the 9th

The transistors of M10 the tenth

The transistors of M11 the 11st

The two-transistors of M12 the tenth

C capacitors

XD light emitting diodes

N1 first nodes

N2 section points

The nodes of N3 the 3rd

N4 fourth nodes

The nodes of N5 the 5th

The nodes of N6 the 6th

Dl5 data-signals

ELVDD voltage source positive poles

ELVSS voltage source negative poles

Vin initialization voltages

Ref reference voltages

En enable signals

The scanning signals of Sn-1 first

The scanning signals of Sn second

Embodiment

Example embodiment is described more fully with referring now to accompanying drawing.However, example embodiment can be with a variety of shapes Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, these embodiments are provided so that the present invention will Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Identical is attached in figure Icon note represents same or similar structure, thus will omit repetition thereof.

Described feature, structure or characteristic can be incorporated in one or more embodiments in any suitable manner In.In the following description, there is provided many details fully understand so as to provide to embodiments of the present invention.However, One of ordinary skill in the art would recognize that without one or more in specific detail, or using other methods, constituent element, material Material etc., can also put into practice technical scheme.In some cases, be not shown in detail or describe known features, material or Person's operation is fuzzy of the invention to avoid.

As shown in figure 1, the pixel compensation circuit of the present invention includes the first transistor M1, second transistor M2, the 3rd crystal Pipe M3, the 4th transistor M4, the 5th transistor M6, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the tenth crystalline substance Body pipe M11, the tenth two-transistor M12, capacitor C and diode XD.

Wherein, the connected mode of each transistor is：The first pole of the first transistor M1 couples a data-signal DI5, the second pole couple a first node N1, and grid couples one second scanning signal Sn；Second transistor M2 the first pole coupling The first node N1, the second pole couple a section point N2, and grid couples a fourth node N4；The first of third transistor M3 Pole couples the section point N2, and the second pole couples the first pole of the 4th transistor M4, grid coupling second scanning Signal Sn；4th transistor M4 the first pole coupling third transistor M3 the second pole, the second pole couple the fourth node N4, Grid couples the second scanning signal Sn；5th transistor M5 the first pole couples the section point N2, the coupling of the second pole One the 3rd node N3, grid couple an enable signal En；The first pole of the 6th transistor M6 couples the first node N1, Second pole couples a voltage source positive pole ELVDD, and grid couples the enable signal En；

The first pole of the 7th transistor M7 couples an initialization voltage Vin, and the second pole couples the 8th transistor M8's First pole, grid couple one first scanning signal Sn-1；The first pole of the 8th transistor M8 couples the 7th transistor M7's Second pole, the second pole couple the fourth node N4, and grid couples the first scanning signal Sn-1；The of the 9th transistor M9 One pole couples the 3rd node N3, and the second pole couples the initialization voltage Vin, and grid couples first scanning signal Sn-1；The first pole of the tenth transistor M10 couples the voltage source positive pole ELVDD, and the second pole couples one the 5th node N5, Grid couples the enable signal En；The first pole of the 11st transistor M11 couples the 5th node N5, the second pole coupling One the 6th node N6 is met, grid couples the first scanning signal Sn-1；The first pole coupling institute of the tenth two-transistor M12 The 5th node N5 is stated, the second pole couples the 6th node N6, and grid couples the second scanning signal Sn.

Capacitor C and light emitting diode XD connected mode is：The first end of the capacitor C couples the 5th node N5, the second end couple the fourth node N4；The positive pole of the diode XD couples the 3rd node N3, the light-emitting diodes Pipe XD negative pole couples a voltage source negative pole ELVSS.

Wherein the 6th node N6 inputs a reference voltage (ref).

Each transistor is selected as PMOS transistor in Fig. 1, the first extremely source electrode, i.e. s poles of each transistor, each The second of transistor extremely drains, i.e. d poles.The breadth length ratio parameter selection of wherein each transistor is as follows：

The breadth length ratio of the second transistor M2 is：Length 3.5um, length 40um；In addition to the second transistor M2 Other transistors, i.e., it is described the first transistor M1, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th brilliant Body pipe M6, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the tenth transistor M10, the 11st transistor M11 and Tenth two-transistor M12 breadth length ratio is：Length 3.3um, width 3.6um.

Wherein, third transistor M3 and the 4th transistor M4 is as the first double-gated transistor, the 7th transistor M7 and the 8th Transistor M8 is as the second double-gated transistor.Double gate transistor compared with single gridistor have threshold voltage (Vth) compared with Greatly, the characteristics of leakage current is relatively low.

In actual applications, each transistor can also select other kinds of transistor, the breadth length ratio of each transistor Parameter is also not necessarily limited to numerical value listed above；In addition, first double-gated transistor and the second double-gated transistor can also divide Do not select to make on the same substrate has the structure of two grids, accordingly adjust each double-gated transistor conducting voltage and The parameter of saturation voltage；The purpose of the present invention can be realized, i.e., the voltage of compensating voltage source is being shown because of the resistance of cabling Caused pressure drop in panel, it is belonged within protection scope of the present invention.

Data-signal dl5, enable signal En, the first scanning signal Sn-1 and second are employed in technical scheme Scanning signal Sn, wherein enable signal En, the first scanning signal Sn-1 and the second scanning signal Sn oscillogram are as shown in Figure 2. The voltage status of other signal input parts is：Voltage source positive pole ELVDD is positive voltage, and voltage source negative pole ELVSS is negative voltage, just Beginningization voltage Vin is negative voltage, and reference voltage ref is positive voltage.Wherein, voltage source positive pole ELVDD is to provide the voltage of electric current Source, when AMOLED lights, continual and steady voltage is produced, therefore ELVDD has lasting electric current and flowed through；Voltage source negative pole ELVSS is the cathode potential of OLED display modules.

Fig. 3~Fig. 7 is combined herein, is introduced respectively in Fig. 1 by five stages of A, B, C, D, E of oscillogram in Fig. 2 The conducting state of pixel compensation circuit.Transistor corresponding to cross expression is drawn in Fig. 3~Fig. 7 is currently not turned on.

As shown in figure 3, when i.e. oscillogram is in A condition in corresponding diagram 2, enable signal En is high level, and the first scanning is believed Number Sn-1 is low level, and the second scanning signal Sn is high level.The transistor that cross is drawn in figure is currently not turned on, i.e. first crystal Pipe M1, third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the tenth transistor M10 and the tenth Two-transistor M12 is not turned on.

Now, initialization voltage Vin voltage write-in fourth node N4 and OLED anode, reference voltage ref voltage are write Enter to the 5th node N5.

As shown in figure 4, when i.e. oscillogram is in B state in corresponding diagram 2, enable signal En is high level, and the first scanning is believed Number Sn-1 is high level, and the second scanning signal Sn is high level.The transistor that cross is drawn in figure is currently not turned on, i.e., except second Transistor M2 is turned on, and other 11 transistors are not turned on.

Now, fourth node N4 keeps initialization voltage Vin voltage, and the 5th node keeps reference voltage ref.

As shown in figure 5, when i.e. oscillogram is in C-state in corresponding diagram 2, enable signal En is high level, and the first scanning is believed Number Sn-1 is high level, and the second scanning signal Sn is low level.The transistor that cross is drawn in figure is currently not turned on, i.e. the 5th crystal Pipe M5, the 6th transistor M6, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the tenth transistor M10 and the tenth One transistor M11 is not turned on.

Now, voltage data signal passes through the first transistor M1, second transistor M2, third transistor M3 and the 4th crystal Pipe M4 is written to fourth node N4, and until second transistor M2 enters cut-off region, the 5th node N5 keeps reference voltage ref. Now, fourth node N4 and the 5th node N5 voltage meet equation below：

Vn4=Vdata+Vth

Vn5=Vref

Wherein, Vn4 is fourth node N4 voltage, and Vn5 is the 5th node N5 voltage, and Vdata is data-signal dl5's Voltage, Vth are second transistor M2 threshold voltage, and Vref is reference voltage ref.

As shown in fig. 6, when i.e. oscillogram is in D-state in corresponding diagram 2, enable signal En is high level, and the first scanning is believed Number Sn-1 is high level, and the second scanning signal Sn is high level.The transistor that cross is drawn in figure is currently not turned on, i.e., brilliant from first Body pipe M1 to the tenth two-transistor M12 12 transistors are all not turned on.

Now, fourth node N4 remains Vdata+Vth, and the 5th node N5 remains Vref.

As shown in fig. 7, when i.e. oscillogram is in E-state in corresponding diagram 2, enable signal En is low level, and the first scanning is believed Number Sn-1 is high level, and the second scanning signal Sn is high level.The transistor that cross is drawn in figure is currently not turned on, i.e. first crystal Pipe M1, third transistor M3, the 4th transistor M4, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the 11st Transistor M11 and the tenth two-transistor M12 are not turned on.

Now, voltage source positive pole ELVDD voltages are written to the 5th node N5, now because electric capacity C coupling, the 4th Node N4 voltage can also change.Fourth node N4 and the 5th node N5 voltage meet equation below：

Vn5=Velvdd=Vs

Vn4=Vdata+Vth+Velvdd-Vref=Vg

Wherein, Vs is second transistor M2 source voltage, and Vg is second transistor M2 grid voltage, and Velvdd is electricity The voltage of potential source positive pole.From second transistor M2 to the 5th transistor M5 electric current Id, that is, flow through light emitting diode XD electric current Value meets equation below：

Id=μ CW/L (Vsg+Vth) ^2

=μ CW/L (Vref-Vdata) ^2

This current value is unrelated with ELVDD voltage sources it can be seen from above-mentioned current formula.

Fig. 8 and 9, which is respectively illustrated, not to be used the pixel compensation circuit of the present invention and is employing the compensation circuit of the present invention When, the situation of change of electric current.

As shown in figure 8, for do not use the present invention pixel compensation circuit when, in voltage source positive pole

When ELVDD voltage is respectively 5.1V and 4.6V, above-mentioned electric current Id situation of change, it can be seen that ELVDD electricity During buckling 0.5V, current variation value reaches 70nA.As shown in figure 9, after to employ the pixel compensation circuit of the present invention, When voltage source positive pole ELVDD voltage is respectively 5.1V and 4.6V, above-mentioned electric current Id situation of change, it can be seen that ELVDD's During voltage change 0.5V, current variation value only has 3nA.

After the pixel compensation circuit for employing the present invention is can be seen that with reference to Fig. 8 and Fig. 9, by current variation value from 70nA 3nA is reduced to, the situation of curent change is greatly improved.

Present invention also offers a kind of display device, including above-mentioned pixel compensation circuit.Employ above-mentioned pixel compensation The display device of circuit, the brightness uniformity of display panel can be effectively improved, its operation principle is i.e. such as above-mentioned pixel compensation electricity The principle on road, will not be repeated here.

Pixel compensation circuit and display device in the present invention produce to the voltage of voltage source because of the resistance of cabling Pressure drop compensate so that the driving current of OLED display device not by voltage source voltage in pressure drop caused by display panel Influence, reduce the inclined of driving current value at the diverse location of display panel and the driving current value that currently sets as far as possible Difference, the brightness uniformity of display panel is improved, lift the viewing experience of user.

The specific embodiment of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned Particular implementation, those skilled in the art can make various deformations or amendments within the scope of the claims, this not shadow Ring the substantive content of the present invention.

Claims

A kind of 1. pixel compensation circuit, it is characterised in that including：

One the first transistor (M1), the first pole of the first transistor (M1) couple a data-signal (dI5), the coupling of the second pole One first node (N1), grid couple one second scanning signal (Sn)；

One second transistor (M2), the first pole of the second transistor (M2) couple the first node (N1), the second pole coupling A section point (N2) is connect, grid couples a fourth node (N4)；

One first switch component, the first end of the first switch component couple the section point (N2), the second end coupling institute Fourth node (N4) is stated, control terminal couples second scanning signal (Sn)；

One the 5th transistor (M5), the first pole of the 5th transistor (M5) couple the section point (N2), the second pole coupling One the 3rd node (N3) is connect, grid couples an enable signal (En)；

One the 6th transistor (M6), the first pole of the 6th transistor (M6) couple the first node (N1), the second pole coupling A voltage source positive pole (ELVDD) is connect, grid couples the enable signal (En)；

The tenth transistor (M10), the first pole of the tenth transistor (M10) couple the voltage source positive pole (ELVDD), the Two poles couple one the 5th node (N5), and grid couples the enable signal (En)；

The 11st transistor (M11), the first pole of the 11st transistor (M11) couple the 5th node (N5), the Two poles couple a reference voltage (ref), and grid couples one first scanning signal (Sn-1)；

One capacitor (C), the first end of the capacitor (C) couple the 5th node (N5), the second end coupling the described 4th Node (N4)；

One light emitting diode (XD), the positive pole of the light emitting diode (XD) couple the 3rd node (N3), negative pole coupling one Voltage source negative pole (ELVSS).
2. pixel compensation circuit according to claim 1, it is characterised in that the first transistor (M1), the second crystal Pipe (M2), the 5th transistor (M5), the 6th transistor (M6), the tenth transistor (M10) and the 11st transistor (M11) are PMOS transistor.
3. pixel compensation circuit according to claim 1, it is characterised in that it is brilliant that the first switch component includes one the 3rd Body pipe (M3) and one the 4th transistor (M4), wherein：

First pole of the third transistor (M3) couples the section point (N2), the second pole of the third transistor (M3) The first pole of the 4th transistor (M4) is coupled, the second pole of the 4th transistor (M4) couples the fourth node, institute The grid for stating third transistor (M3) and the 4th transistor (M4) couples second scanning signal (Sn).
4. pixel compensation circuit according to claim 3, it is characterised in that the third transistor (M3) and the 4th crystal It is PMOS to manage (M4).
5. pixel compensation circuit according to claim 1, it is characterised in that also including a second switch component, described The first end of two switch modules couples an initializing signal (Vin), and the second end couples the fourth node (N4), control terminal coupling First scanning signal (Sn-1).
6. pixel compensation circuit according to claim 5, it is characterised in that it is brilliant that the second switch component includes one the 7th Body pipe (M7) and one the 8th transistor (M8), wherein：

First pole of the 7th transistor (M7) couples the initializing signal (Vin), and the of the 7th transistor (M7) Two poles couple the first pole of the 8th transistor (M8), described Section four of the second pole coupling of the 8th transistor (M8) The grid of point, the 7th transistor (M7) and the 8th transistor (M8) couples first scanning signal (Sn-1).
7. pixel compensation circuit according to claim 6, it is characterised in that described also including one the 9th transistor (M9) First pole of the 9th transistor (M9) couples the 3rd node (N3), and the second pole couples the initializing signal (Vin), grid Couple first scanning signal (Sn-1).
8. pixel compensation circuit according to claim 7, it is characterised in that the 7th transistor (M7), the 8th crystal It is PMOS to manage (M8) and the 9th transistor (M9).
9. pixel compensation circuit according to claim 1, it is characterised in that also including 1 the tenth two-transistor (M12), institute The first pole for stating the tenth two-transistor (M12) couples the 5th node, and the second pole couples the reference voltage (ref), grid Couple second scanning signal (Sn).
10. pixel compensation circuit according to claim 9, it is characterised in that the tenth two-transistor (M12) is PMOS Pipe.
11. a kind of display device, it is characterised in that including the pixel compensation circuit any one of claim 1 to 10.