CN101738794A - Liquid crystal panel - Google Patents
Liquid crystal panel Download PDFInfo
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- CN101738794A CN101738794A CN200810174837A CN200810174837A CN101738794A CN 101738794 A CN101738794 A CN 101738794A CN 200810174837 A CN200810174837 A CN 200810174837A CN 200810174837 A CN200810174837 A CN 200810174837A CN 101738794 A CN101738794 A CN 101738794A
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- sweep trace
- sweep
- liquid crystal
- crystal panel
- pixel column
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Abstract
The invention discloses a liquid crystal panel, which is provided with N scanning lines and N pixel columns. The liquid crystal panel comprises the ith scanning line, the (i+1)th scanning line, the (i+3)th scanning line, a first transistor and a first capacitor, wherein the ith scanning line is used for scanning the ith pixel column; the (i+1)th scanning line is used for scanning the (i+1)th pixel column; the (i+3)th scanning line is used for scanning the (i+3)th pixel column; and the ith pixel column is adjacent to the (i+1)th pixel column. The first transistor is coupled between the ith scanning line and the (i+3)th scanning line, and a gate of the first transistor is coupled with the (i+1)th scanning line. The first capacitor is coupled between the ith scanning line and the common end to reduce the feed-through effect on the ith scanning line, wherein N and i are positive integers, and i is less than or equal to N-3.
Description
Technical field
The present invention relates to a kind of Pixel-level multiplexed (Pixel Level Multiplexing, the PLM) liquid crystal panel of framework, and be particularly related to a kind of liquid crystal panel that reduces required gate drivers (gate driver) number.
Background technology
(FPD) is of a great variety for present flat-panel screens, as LCD (LCD), organic electroluminescence optical display unit (OLED) and plasma scope (PDP) etc.Yet, no matter be which kind of flat-panel screens, the framework all similar of its display panel promptly disposes crisscross sweep trace (scan line) and data line (data line) on substrate (substrate), and each bar sweep trace and data line infall dispose a pixel (pixel).Whether pixel receives sweep signal via sweep trace and is enabled or conducting with decision, and receives data-signal with display image via data line when it is switched on.
The resolution of liquid crystal panel is high more, its required grid drive chip will be many more, and each bar sweep trace all needs to be provided with corresponding bonding pad (pad) to be connected to grid drive chip, and this not only needs considerable layout area, also can increase extra manufacturing cost simultaneously.Therefore,, be one of important development direction of present liquid crystal panel Driving technique how at the pin count of keeping the required grid drive chip of minimizing under the situation of equal resolution.
Fig. 1 is the local circuit synoptic diagram according to the liquid crystal panel of known technology.Local circuit 100 in the liquid crystal panel comprises that many data lines are (as DL1, DL2) and N bar sweep trace (as SEi, SOi, i wherein, N is a positive integer, i is the index value of sweep trace, and 0＜i≤N/2), wherein strange sweep trace SOi is corresponding to strange pixel column 110, idol sweep trace SEi is corresponding to dual pixel row 120, wherein dual pixel row 120 comprise respectively that with strange pixel column 110 a plurality of pixel cells are (as 111,112,121 and 122), comprise transistor in each pixel cell, element such as liquid crystal capacitance and storage capacitors, pixel cell can adopt known dot structure, and the pixel cell among Fig. 1 is (as 111,112,121 and 122) only be schematic.
Is example with dual pixel row 120 with strange pixel column 110, dual pixel row 120 are coupled to even sweep trace SEi, strange pixel column 110 is coupled to strange sweep trace SOi, the other end of strange sweep trace SOi is coupled to the end of transistor M1, the other end of transistor M1 is coupled to next bar idol sweep trace SEi+1, and the grid of transistor M1 is coupled to even sweep trace SEi.When even sweep trace SEi and SEi+1 all enable (during logic high potential), strange pixel column 110 all can be opened with dual pixel row 120 so that data line (as DL1, DL2) writes pixel data extremely in the corresponding pixel cell (as 111,112).Then, when having only even sweep trace SEi to enable, then strange pixel column 110 is closed and remaining dual pixel row 120 are opened in case data line (as DL
1, DL
2) write pixel data to the pixel cell (as 121,122) of pixel column 120 to upgrade the pixel voltage in the pixel column 120.All the other strange sweep traces, even sweep trace can be analogized with the circuit structure of corresponding pixel cell, do not add at this and give unnecessary details.In addition, it should be noted that transistor M1, M2 among Fig. 1 can be formed at the fanout area 150 or the non-active zone (non-activearea) of liquid crystal panel.
The waveform of the sweep signal (being the sweep signal that gate drivers institute palpus is exported) that strange sweep trace SOi and even sweep trace SEi+1 receive as shown in Figure 2, Fig. 2 is the sweep signal oscillogram according to Fig. 1, wherein in the preceding semiperiod of second phase T2, idol sweep trace SEi and SEi+1 all enable, at this moment, strange pixel column 110 all can be opened with pixel column 120.Then, interim in the second half of second phase T2, even sweep trace SEi keeps and enables, and even sweep trace SEi+1 is then forbidden, and at this moment, only surplus pixel column 120 is opened, and utilizes above-mentioned sequential, just can noveler in regular turn pixel column 110 with dual pixel row 120 in pixel data.
Then, even sweep trace SE
I+1Between the third phase, enable among the T3 so that upgrade pairing strange pixel column and dual pixel row, and between the first phase among the T1, even sweep trace SE
iThen cooperate an even sweep trace SE
I-1Sweep signal, between the first phase, enable in the preceding semiperiod of T1 so that upgrade corresponding strange sweep trace SO
I-1Strange pixel column (as even sweep trace SE
I+1Cooperate even sweep trace SE in the preceding semiperiod of second phase T2
iAnd enable the same).It should be noted that T1 between the above-mentioned first phase, second phase T2 and between the third phase cycle of T3 identical, the sweep signal of all the other sweep traces can the rest may be inferred to upgrade the pixel of whole front panel.Utilize the panel framework of Fig. 1, only need the sweep signal of half to drive all pixel cells, also just can reduce the use number of grid drive chip.
In the process that drives, pixel cell can be influenced because of the potential change of sweep signal, just so-called feedthrough effect (feed through effect).But in second phase T2, dual pixel row 120 only are subjected to even sweep trace SE
iThe influence of the negative edge 201 feedthrough effect that produces, strange pixel column 110 then can be subjected to even sweep trace SE
iThe negative edge 201 and next bar idol sweep trace SE of sweep signal
I+1The influence of the negative edge 202 feedthrough effect that produces of sweep signal.Therefore, in the driving process, the suffered feedthrough effect of strange pixel column 110 is greater than dual pixel row 120.If whole image gives same grayscale, then because the difference of above-mentioned feedthrough effect will cause the image quality inequality.
Fig. 3 is the local equivalent circuit diagram according to the liquid crystal panel 100 of Fig. 1.Wherein pixel cell 111 comprises transistor M111, liquid crystal capacitance Clc2 and storage capacitors Cst2, and capacitor C gs2 is used for representing the equivalent capacity between the gate-to-source of transistor M111, and capacitor C gsf is used for representing the equivalent capacity between the gate-to-source of transistor M1.The circuit structure of pixel cell 121 is identical with pixel cell 111, does not add tired stating at this.Equivalent capacity among cooperation Fig. 3 and the signal waveforms of Fig. 2 can calculate the influence of the change in voltage (by high voltage Vgh to Vgl) of sweep signal to the pixel voltage (being that liquid crystal capacitance Clc2 and Clc1 go up stored pixel voltage) of pixel cell 111 and 121.
In second phase T2, the pixel voltage on the pixel cell 121 only is subjected to even sweep trace SE
iThe influence of negative edge 201 (please refer to Fig. 2), just descend via the voltage that capacitor C gs1 is caused, its feed-trough voltage (feed through voltage) Δ V1 can be expressed as follows:
Wherein Cgs1, Clc and the Cst1 in the following formula (1) represents corresponding equivalent capacitance value.
Wherein, in the following formula (2), n represents the number of the pixel cell in the dual pixel row 120, and CX represents the value that Cgs2 connects with (Clc2+Cst2).
By above-mentioned formula (1) and (2) as can be known, pixel cell 111 is because the feed-trough voltage Δ V2 that sweep signal caused can be greater than pixel cell 121 because the feed-trough voltage Δ V1 that sweep signal caused.Therefore, in the driving process, pixel cell 111 can have different change in voltage because of sweep signal with pixel voltage on the pixel cell 121, and this can influence quality and stability of demonstration.
In addition, as even sweep trace SE
iDuring forbidding, strange sweep trace SO
iCan be in the state of float (floating), because many circuitry lines or electric capacity etc. are arranged near the grid of transistor M111, the grid voltage that can cause transistor M111 is subjected to these electrical couplings effects and drifts to common voltage Vcom and influence pixel voltage on the liquid crystal capacitance Clc2.
Summary of the invention
The invention provides a kind of liquid crystal panel, utilize two sweep traces at interval, drive pixel cell with required gate drivers (pin) number of minimizing liquid crystal panel in the mode that cooperates, and the drive waveforms of setting up electric capacity or changing its sweep signal on sweep trace reduces the influence of sweep signal to pixel voltage.
The present invention also provides a kind of liquid crystal panel, between sweep trace, set up control line and corresponding transistor (switch), as long as can scan all sweep traces by control line, reduce required gate drivers (pin) number thus, and reduce the feedthrough effect difference of sweep signal thus to each pixel cell, to increase the display quality of liquid crystal panel.
From the above, the present invention proposes a kind of liquid crystal panel, has a N bar sweep trace and N pixel column, N is a positive integer, this liquid crystal panel comprises i sweep trace, i+1 sweep trace, the first transistor and first electric capacity, wherein said i sweep trace is in order to scan the i pixel column, and described i+1 sweep trace is in order to scan the i+1 pixel column, and wherein said i pixel column is adjacent with described i+1 pixel column; The i+3 sweep trace is in order to scan the i+3 pixel column.The drain electrode of described the first transistor and source electrode are respectively coupled to described i sweep trace and described i+3 sweep trace, and the grid of described the first transistor is coupled to described i+1 scanning linear, and described first electric capacity is coupled between described i sweep trace and the common terminal; Wherein, described i pixel column, described i+1 pixel column and described i+3 pixel column comprise a plurality of pixel cells respectively, and wherein i is that positive integer and i are smaller or equal to N-3.
In embodiments of the present invention, this i sweep trace in the described liquid crystal panel is strange sweep trace, and this i+1 sweep trace is even sweep trace.
In embodiments of the present invention, this i sweep trace in the described liquid crystal panel is even sweep trace, and this i+1 sweep trace is strange sweep trace.
In embodiments of the present invention, described common terminal is earth terminal or common voltage end.
In embodiments of the present invention, wherein said first electric capacity can be formed by the first metal layer, insulation course, second metal level, passivating film, transparency electrode and at least one through hole (via).Wherein, described insulation course is formed on the described the first metal layer, described second metal level is formed on the described the first metal layer, passivating film is formed on described second metal level, described transparency electrode be formed on the described passivating film and described through hole in order to connect described the first metal layer and described transparency electrode.
In embodiments of the present invention, wherein said i+1 sweep trace receives first sweep signal, and described i+3 sweep trace receives second sweep signal, and wherein in the preceding semiperiod between the first phase, described first sweep signal enables; During the second, described first sweep signal enables and described second sweep signal enabled in the preceding semiperiod of the described second phase; In between the third phase, described second sweep signal enables.Before the described second phase, the described second phase is before between the described third phase, and the equal in length between described first, second and the third phase between the described first phase.
In embodiments of the present invention, wherein said the first transistor is a thin film transistor (TFT), and is formed on fanout area.
The present invention also proposes a kind of liquid crystal panel, has a N bar sweep trace and N pixel column, and N is a positive integer, and this liquid crystal panel comprises i sweep trace, i+1 sweep trace, i+3 sweep trace and the first transistor.Wherein, described i sweep trace is in order to scan the i pixel column; Described i+1 sweep trace is in order to scan the i+1 pixel column, and wherein said i pixel column is adjacent with described i+1 pixel column; Described i+3 sweep trace is in order to scan the i+3 pixel column; The drain electrode of described the first transistor and source electrode are respectively coupled to described i sweep trace and described i+3 sweep trace, and the grid of described the first transistor is coupled to described i+1 scanning linear; Wherein, described i+1 sweep trace receives first sweep signal, and described i+3 sweep trace receives second sweep signal, and in the preceding semiperiod between the first phase, described first sweep signal enables; During the second, described first sweep signal enables and described second sweep signal enabled in the preceding semiperiod of the described second phase, and in the described second phase, first enable voltage of described first sweep signal is greater than second enable voltage of described second sweep signal, and wherein i is that positive integer and i are smaller or equal to N-3.
In embodiments of the present invention, in between the third phase after the described second phase, described second sweep signal enables, and described second enable voltage of described second sweep signal between the described third phase equals described first enable voltage of described first sweep signal in the described second phase.Before the described second phase, the described second phase is before between the described third phase, and the equal in length between described first, second and the third phase between the described first phase.
In embodiments of the present invention, described i pixel column, described i+1 pixel column and described i+3 pixel column comprise a plurality of pixel cells respectively.
In embodiments of the present invention, this i sweep trace in the described liquid crystal panel is strange sweep trace, and this i+1 sweep trace is even sweep trace.
In embodiments of the present invention, this i sweep trace in the described liquid crystal panel is strange sweep trace, and this i+1 sweep trace is even sweep trace.
The present invention also proposes a kind of liquid crystal panel, has a N bar sweep trace and N pixel column, and N is a positive integer, and this liquid crystal panel comprises first control line, second control line, the 3rd control line, the first transistor and transistor seconds.The wherein said first control line correspondence is in described i sweep trace and described i+1 sweep trace; The described second control line correspondence is in i+2 sweep trace and i+3 sweep trace; Described the 3rd control line correspondence is in i+4 sweep trace and i+5 sweep trace; The drain electrode of described the first transistor and source electrode are respectively coupled to the described i sweep trace and second control line, and the grid of described the first transistor is coupled to described first control line; The drain electrode of described transistor seconds and source electrode are respectively coupled to described i+1 sweep trace and described first control line, and the grid of described transistor seconds is coupled to described the 3rd control line, wherein, described i sweep trace is adjacent with described i+1 sweep trace, described i+2 sweep trace is adjacent with described i+3 sweep trace, described i+4 sweep trace is adjacent with described i+5 sweep trace, and wherein i is that positive integer and i are smaller or equal to N-5.
In embodiments of the present invention, wherein in the scan period of the described first gated sweep line, the described first gated sweep line enables, and described second control line enables in the preceding semiperiod of described scan period, and described the 3rd control strip sweep trace enables in that the second half of described scan period is interim.
In embodiments of the present invention, wherein each bar of these sweep traces corresponds respectively to a pixel column, and described pixel column has a plurality of pixel cells respectively.
In embodiments of the present invention, this i sweep trace in the described liquid crystal panel is strange sweep trace, and this i+1 sweep trace is even sweep trace.
In embodiments of the present invention, this i sweep trace in the described liquid crystal panel is strange sweep trace, and this i+1 sweep trace is even sweep trace.
The present invention is owing to adopting the multi-strip scanning line to arrange in pairs or groups mutually or driving pixel cell with indirect mode, thereby reduce required gate drivers (pin) number of panel, and reduce the feedthrough effect that voltage transitions caused by the drive waveforms of setting up electric capacity or changing its sweep signal, and reduce the influence of sweep signal pixel voltage because of sweep signal.
For feature and advantage of the present invention can become apparent more, preferred embodiment cited below particularly, and in conjunction with the accompanying drawings, be described in detail below.
Description of drawings
Fig. 1 is the liquid crystal panel local circuit synoptic diagram according to known technology;
Fig. 2 is the sweep signal oscillogram according to Fig. 1;
Fig. 3 is the local equivalent circuit diagram according to the liquid crystal panel 100 of Fig. 1;
Fig. 4 is the local circuit synoptic diagram according to the described liquid crystal panel of first embodiment of the invention;
Fig. 5 is the structural drawing according to the capacitor C st of first embodiment of the invention;
Fig. 6 is the sweep signal oscillogram according to second embodiment of the invention;
Fig. 7 is the local circuit synoptic diagram according to the liquid crystal panel of third embodiment of the invention;
Fig. 8 is the sweep signal oscillogram according to Fig. 7;
[primary clustering symbol description]
100,700: the local circuit of liquid crystal panel
110,710: strange pixel column
120,720: the dual pixel row
111,112,121,122: pixel cell
150: fanout area
201: negative edge
202: negative edge
502: through hole
510: insulation course
520: passivating film
610,620: enable voltage
711,712,721,722: pixel cell
810,820: the pulse of sweep signal
DL
1, DL
2: data line
SO
i～SO
I+2: strange sweep trace
SE
i～SE
I+2: even sweep trace
SC
i～SC
I+2: control line
M1, M2, M111, M121: transistor
M701, M702, M703: transistor
T1: between the first phase
T2: the second phase
T3: between the third phase
Clc1, Clc2: liquid crystal capacitance
Cst2, Cst1: storage capacitors
Cgs2: the equivalent capacity between the gate-to-source of transistor M111
Cgs1: the equivalent capacity between the gate-to-source of transistor M121
Cgsf: the equivalent capacity between the gate-to-source of transistor M1
Cst: electric capacity
M1: the first metal layer
M2: second metal level
ITO: transparency electrode
Vgh1, Vgh2: the enable voltage value of sweep signal
Vgl: the magnitude of voltage during the sweep trace forbidding
T
s: scan period
T
S1: scan period T
sThe preceding semiperiod
T
S2: scan period T
sThe later half cycle
Embodiment
First embodiment
Referring to figs. 1 through Fig. 3, in order to reduce the feed-trough voltage Δ V2 of pixel cell 111, present embodiment is at strange sweep trace SO simultaneously
iLast connection capacitor C st, as shown in Figure 4, Fig. 4 is the local circuit synoptic diagram according to the described liquid crystal panel of first embodiment of the invention.Wherein, capacitor C st and strange sweep trace SO
iOn pixel cell 111 parallel connections, to increase the capacitance after its parallel connection.With reference to above-mentioned formula (2), after setting up capacitor C st, in the formula (2) ((Cgs+n * CX+Cst), promptly its numerical value becomes big to Cgs+n * CX) become, so feed-trough voltage Δ V2 will reduce and levels off to feed-trough voltage Δ V1.Because capacitor C st is parallel to strange sweep trace SO
iOn all pixel cells (as 112), so capacitor C st has too and reduces strange sweep trace SO
iOn the effect of feed-trough voltage of other pixel cell (as 112).
At other strange sweep trace (as SO
I+1) on, present embodiment capacitor C st in parallel equally thereon is to reduce the influence of sweep signal to each bar (strange or idol) sweep trace.The other end of capacitor C st can be coupled to common voltage end Vcom or earth terminal, as long as can increase strange sweep trace SO
iOn equivalent capacitance value get final product., be not repeated as the explanation of above-mentioned Fig. 1 and Fig. 2 about the remaining circuit of Fig. 4 and mode of operation thereof at this.In addition, owing to there is the capacitor C st of big capacitance to exist, therefore strange sweep trace more can not be subjected to the influence of other circuit and change its magnitude of voltage.
Because capacitor C st must be enough to influence strange sweep trace SO
iGo up all pixel cells, therefore must have bigger capacitance, but bigger capacitance needs usually large tracts of land just can reach.Therefore, present embodiment designs this capacitor C st in the sandwich construction mode of sandwich, with reference to Fig. 5, Fig. 5 is the structural drawing according to the capacitor C st of present embodiment, wherein the first metal layer M1 and the second metal level M2 are the two ends of capacitor C st, transparency electrode ITO is positioned at the opposite side of the second metal level M2, and is connected to the first metal layer M1 via through hole 502.Because the second metal level M2 between transparency electrode ITO and the first metal layer M1, therefore can form bigger overlapping area to form bigger capacitance.Wherein, have passivating film 520 between the transparency electrode ITO and the second metal level M2, and have dielectric film 510 between the first metal layer M1 and the second metal level M1.Generally speaking, the material of passivating film (passivation film) 520 for example is a silicon dioxide (SiO2), and the material of gate insulating film (gate insulation film) 510 for example is a silicon nitride (SiNx).The structure of the capacitor C st of Fig. 5 can be formed by general liquid crystal panel technology, is not repeated at this.
Second embodiment
Except reducing strange sweep trace SO via setting up capacitor C st
iWith even sweep trace SE
iBetween difference outside, present embodiment also proposes a kind ofly to reduce the method that retracts the difference between voltage Δ V1, the Δ V2 via the drive waveforms of adjusting sweep signal.
With reference to Fig. 6 and Fig. 1, Fig. 6 is the sweep signal oscillogram according to second embodiment of the invention simultaneously, is applicable to the liquid crystal panel that drives as Fig. 1.Wherein, in second phase T2, make even sweep trace SE
iThe magnitude of voltage of enable voltage 620 be Vgh2, and even sweep trace SE
I+1The magnitude of voltage of enable voltage 610 be Vgh1, wherein Vgh2 is greater than Vgh1.Vgl is even sweep trace SE
I+1Or even sweep trace SE
iMagnitude of voltage during forbidding (or being called logic low potential).Because even sweep trace SE
i, SE
I+1The sweep signal waveform change, so in the known technology formula (1) and formula (2) can be revised as formula (3) respectively as follows with formula (4):
.......................(4)
Via above-mentioned formula (4) as can be known, when magnitude of voltage Vgh1 descended, the voltage Δ V2 that retracts that retracts on voltage Δ V1 and the pixel cell 111 on the pixel cell 121 can be comparatively approaching.When the pixel cell of scanning on the whole front panel, its sweep signal is as the even sweep trace SE among Fig. 6
iWith even sweep trace SE
I+1Shown in, its sweep signal has time delay, or is called scan period, in regular turn with identical waveform scanning whole front panel zone.Via of the present invention open, can know pairing sweep signal waveform of all the other sweep traces and sequential thereof easily by inference those skilled in the art, be not repeated at this.
The 3rd embodiment
Fig. 7 is the circuit diagram according to the liquid crystal panel of third embodiment of the invention, and in Fig. 7, the local circuit 700 in the liquid crystal panel comprises that many data lines are (as DL
1, DL
2), control line SC
i, strange sweep trace SO
iAnd even sweep trace SE
i, wherein i is the index value of sweep trace, if liquid crystal panel comprises N bar sweep trace, and 0＜i≤N/2 then, i, N are all positive integer.Wherein, each bar control line is all corresponding to a strange sweep trace and an even sweep trace, with control line SC
iBe example, its correspondence be strange sweep trace SO
iWith even sweep trace SE
i, strange sweep trace SO
iIn order to scanning strange pixel column 710, and even sweep trace SEi is in order to scanning dual pixel row 720, and wherein strange pixel column 710 comprises a plurality of pixel cells (as 711,712,721,722) respectively with dual pixel row 720.Structure in the pixel cell is identical with known technology, promptly has structures such as liquid crystal capacitance, storage capacitors (not shown) and transistor, can adopt different dot structures according to different demands, is not repeated at this.
Transistor M701 is coupled to strange sweep trace SO
iWith gated sweep line SC
I+1Between, and the grid of transistor M701 couples i bar control line SL
iTransistor M703 is coupled to even sweep trace SE
iWith i+2 bar control line SC
I+2Between, and the grid of transistor M703 couples i+1 bar control line SC
I+1, all the other strange, even sweep traces and corresponding gated sweep line annexation can the rest may be inferred, be not repeated.
The scan mode of Fig. 7 can be with reference to Fig. 8, and Fig. 8 is the sweep signal oscillogram according to Fig. 7.Local circuit 700 in the liquid crystal panel comprises control line SC
i, strange sweep trace SO
iAnd even sweep trace SE
iControl line SC
iAt its scan period T
sIn enable, at this moment, transistor M701 conducting, next bar control line SC
I+1At scan period T
sPreceding semiperiod T
S1In enable to open strange sweep trace SO
iNext, next bar control line SC again
I+2At scan period T
sLater half period T
S2Enable with turn-on transistor M703 to open even sweep trace SE
iSo, at scan period T
sIn can finish and write pixel data to corresponding control line SC
i Strange pixel column 710 and dual pixel row 720 on pixel cell (as 711,712,721,722).All the other even sweep traces can be analogized with the scan mode of strange sweep trace on the liquid crystal panel, repeat no more.
In other words, in the present embodiment, gate drivers only need drive all control lines and can all pixel cells be scanned (all strange sweep trace and the even sweep traces of promptly corresponding scanning), and control line SC
iNumber half number of all sweep traces in the liquid crystal panel (comprise even sweep trace with strange sweep trace) is only arranged, can reduce driving the required gate drivers number of panel thus.In addition, it should be noted that strange sweep trace described in the foregoing description and even sweep trace mainly are to be used for distinguishing two adjacent sweep traces, the present invention is not exceeded with its title, and in another embodiment of the present invention, its placement position also can be exchanged.
Because control line SC
iCan directly not go to the on-pixel unit, but with following two control line SC
I+1, SC
I+2Cooperatively interact, enable corresponding strange sweep trace SO with indirect mode
iWith even sweep trace SE
iTherefore, control line SC
iOn sweep signal have two pulses 810,820, wherein pulse 810 is to be used for cooperating preceding two control line SC
I-1, SC
I-2, and pulse 820 is only and is used for opening corresponding to control line SC
i Strange pixel column 710 and dual pixel row 720.
Because in the process that drives, strange pixel column 710 is identical with its circuit structure with the type of drive of dual pixel row 720, so the suffered feedthrough effect of its pixel cell (as 711 and 721) is consistent, just control line SC
i, SC
I+1, SC
I+2On sweep signal identical to pixel cell 711 with 721 influence.Strange pixel column 710 is subjected to scan mode with pixel cell on the dual pixel row 720 and to influence the degree of its pixel voltage more consistent, so the quality that its picture shows is comparatively stable.And compared to known technology, present embodiment only need use the sweep signal of half can drive all pixel columns, does not resemble known technology, and each pixel column all needs a sweep signal to drive.By technological means of the present invention, can reduce the fanout area area of the number, number of scanning lines and the panel that drive the required grid drive chip of panel.
In addition, it should be noted that transistor M701～M703 is the same with transistor M1, M2 among Fig. 1, all can be formed in the fanout area 150.Certainly, if the layout areas of panel still has living space, also can it be arranged at suitable zone according to deviser's demand.
Fig. 7 only illustrates the part of driving circuit, and remaining control line can be listed as corresponding to a strange pixel column and a dual pixel equally, and its structure and type of drive are as described in above-mentioned Fig. 7 and Fig. 8, those skilled in the art, via of the present invention open, should analogize easily, be not repeated at this.
In addition, it should be noted that the strange sweep trace SO described in the foregoing description
iWith even sweep trace SE
iOnly be the position relation that is used for describing between the sweep trace, the present invention is not exceeded with it.If have N bar sweep trace in the liquid crystal panel, then strange sweep trace SO
iWith even sweep trace SE
iCan represent with i sweep trace and i+1 sweep trace respectively that also wherein N, i are that positive integer and i are less than N.Those skilled in the art via disclosing of present embodiment, should know the expression mode of all the other scan line position that are suitable for by inference easily, do not repeat them here.
In sum, the present invention is according to the principle of feedthrough effect, proposes with new increase electric capacity respectively, changes the waveform of its sweep signal and directly adjust mode such as its driving circuit and reduce the influence of sweep signal to the different pixels row.By technological means of the present invention, can improve the problem of image quality inequality and reduce of the influence of the potential change of sweep signal pixel voltage.
Though the present invention discloses aforesaid preferred embodiment; yet it is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can making various modifications and variations, so protection scope of the present invention should be as the criterion with the scope of appended claims.
Claims (15)
1. a liquid crystal panel has a N bar sweep trace and N pixel column, and N is a positive integer, and this liquid crystal panel comprises:
The i sweep trace, in order to scan the i pixel column, wherein i is that positive integer and i are smaller or equal to N-3;
The i+1 sweep trace, in order to scan the i+1 pixel column, wherein said i pixel column is adjacent with described i+1 pixel column;
The i+3 sweep trace is in order to scan the i+3 pixel column;
The first transistor, the drain electrode of described the first transistor and source electrode are respectively coupled to described i sweep trace and described i+3 sweep trace, and the grid of described the first transistor is coupled to described i+1 scanning linear; And
First electric capacity is coupled between described i sweep trace and the common terminal;
Wherein, described i pixel column, described i+1 pixel column and described i+3 pixel column comprise a plurality of pixel cells respectively.
2. liquid crystal panel according to claim 1, wherein, described i sweep trace is strange sweep trace, described i+1 sweep trace is even sweep trace.
3. liquid crystal panel according to claim 2, wherein, described i sweep trace is even sweep trace, described i+1 sweep trace is strange sweep trace.
4. liquid crystal panel according to claim 1, wherein, described common terminal is earth terminal or common voltage end.
5. liquid crystal panel according to claim 1, wherein, described first electric capacity comprises:
The first metal layer;
Insulation course is formed on the described the first metal layer;
Second metal level is formed on the described the first metal layer;
Passivating film is formed on described second metal level;
Transparency electrode is formed on the described passivating film; And
At least one through hole is in order to connect described the first metal layer and described transparency electrode.
6. liquid crystal panel according to claim 1, wherein, described i+1 sweep trace receives first sweep signal, and described i+3 sweep trace receives second sweep signal, and wherein in the preceding semiperiod between the first phase, described first sweep signal enables; During the second, described first sweep signal enables and described second sweep signal enabled in the preceding semiperiod of the described second phase; In between the third phase, described second sweep signal enables.
7. liquid crystal panel according to claim 6, wherein, before the described second phase, the described second phase is before between the described third phase, and the equal in length between described first, second and the third phase between the described first phase.
8. liquid crystal panel according to claim 1, wherein, described the first transistor is formed on fanout area.
9. liquid crystal panel according to claim 1, wherein, described the first transistor is a thin film transistor (TFT).
10. a liquid crystal panel has a N bar sweep trace and N pixel column, and N is a positive integer, and described liquid crystal panel comprises:
The i sweep trace, in order to scan the i pixel column, wherein i is that positive integer and i are smaller or equal to N-3;
The i+1 sweep trace, in order to scan the i+1 pixel column, wherein said i pixel column is adjacent with described i+1 pixel column;
The i+3 sweep trace is in order to scan the i+3 pixel column; And
The first transistor, the drain electrode of described the first transistor and source electrode are respectively coupled to described i sweep trace and described i+3 sweep trace, and the grid of described the first transistor is coupled to described i+1 scanning linear;
Wherein, described i+1 sweep trace receives first sweep signal, and described i+3 sweep trace receives second sweep signal, and in the preceding semiperiod between the first phase, described first sweep signal enables; During the second, described first sweep signal enables and described second sweep signal enabled in the preceding semiperiod of the described second phase, and in the described second phase, first enable voltage of described first sweep signal is greater than second enable voltage of described second sweep signal.
11. liquid crystal panel according to claim 10, wherein, in between the third phase, described second sweep signal enables, and described second enable voltage of described second sweep signal between the described third phase equals described first enable voltage of described first sweep signal in the described second phase.
12. liquid crystal panel according to claim 10, wherein, before the described second phase, the described second phase is before between the described third phase, and the equal in length between described first, second and the third phase between the described first phase.
13. liquid crystal panel according to claim 10, wherein, described i pixel column, described i+1 pixel column and described i+3 pixel column comprise a plurality of pixel cells respectively.
14. a liquid crystal panel has a N bar sweep trace and N pixel column, N is a positive integer, and described liquid crystal panel comprises:
First control line, corresponding to i sweep trace and i+1 sweep trace, wherein i is that positive integer and i are smaller or equal to N-5;
Second control line is corresponding to i+2 sweep trace and i+3 sweep trace;
The 3rd control line is corresponding to i+4 sweep trace and i+5 sweep trace;
The first transistor, the drain electrode of described the first transistor and source electrode are respectively coupled to the described i sweep trace and second control line, and the grid of described the first transistor is coupled to described first control line; And
Transistor seconds, the drain electrode of described transistor seconds and source electrode are respectively coupled to described i+1 sweep trace and described first control line, and the grid of described transistor seconds is coupled to described the 3rd control line,
Wherein, described i sweep trace is adjacent with described i+1 sweep trace, and described i+2 sweep trace is adjacent with described i+3 sweep trace, and described i+4 sweep trace is adjacent with described i+5 sweep trace.
15. liquid crystal panel according to claim 14, wherein, in the scan period of the described first gated sweep line, the described first gated sweep line enables, and described second control line enabled in the preceding semiperiod of described scan period, and described the 3rd gated sweep line enables in that the second half of described scan period is interim.
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| CN 200810174837 CN101738794B (en) | 2008-11-07 | 2008-11-07 | Liquid crystal panel |
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| CN102096256A (en) * | 2010-11-09 | 2011-06-15 | 华映视讯（吴江）有限公司 | Pixel array structure |
| CN103426398A (en) * | 2012-05-17 | 2013-12-04 | 乐金显示有限公司 | Organic light emitting diode display and its driving method |
| CN107845364A (en) * | 2016-09-19 | 2018-03-27 | 上海和辉光电有限公司 | Pixel compensation circuit and display device |
| CN111435200A (en) * | 2019-01-11 | 2020-07-21 | 惠科股份有限公司 | Liquid crystal display device, liquid crystal display panel and driving method thereof |
| CN112673416A (en) * | 2018-07-13 | 2021-04-16 | 堺显示器制品株式会社 | Control device and liquid crystal display device |
| CN112820237A (en) * | 2019-10-31 | 2021-05-18 | 京东方科技集团股份有限公司 | Electronic substrate, driving method thereof and display device |
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| US20030063074A1 (en) * | 2000-04-24 | 2003-04-03 | Katsuhiko Kumagawa | Display unit and drive method therefor |
| US20030098934A1 (en) * | 2001-11-23 | 2003-05-29 | Hsin-Ta Lee | Liquid crystal display panel having reduced flicker |
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| KR100982121B1 (en) * | 2003-12-23 | 2010-09-14 | 엘지디스플레이 주식회사 | Liquid Crysyal Display And Driving Method Thereof |
| CN101261376B (en) * | 2007-03-09 | 2012-01-04 | 中华映管股份有限公司 | Display panel, display apparatus and drive method |
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| US20030063074A1 (en) * | 2000-04-24 | 2003-04-03 | Katsuhiko Kumagawa | Display unit and drive method therefor |
| US20030098934A1 (en) * | 2001-11-23 | 2003-05-29 | Hsin-Ta Lee | Liquid crystal display panel having reduced flicker |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102096256A (en) * | 2010-11-09 | 2011-06-15 | 华映视讯（吴江）有限公司 | Pixel array structure |
| CN103426398A (en) * | 2012-05-17 | 2013-12-04 | 乐金显示有限公司 | Organic light emitting diode display and its driving method |
| US9159268B2 (en) | 2012-05-17 | 2015-10-13 | Lg Display Co., Ltd. | Organic light emitting diode display and its driving method |
| CN103426398B (en) * | 2012-05-17 | 2016-03-30 | 乐金显示有限公司 | Organic light emitting diode display and driving method thereof |
| CN107845364A (en) * | 2016-09-19 | 2018-03-27 | 上海和辉光电有限公司 | Pixel compensation circuit and display device |
| CN112673416A (en) * | 2018-07-13 | 2021-04-16 | 堺显示器制品株式会社 | Control device and liquid crystal display device |
| CN111435200A (en) * | 2019-01-11 | 2020-07-21 | 惠科股份有限公司 | Liquid crystal display device, liquid crystal display panel and driving method thereof |
| CN112820237A (en) * | 2019-10-31 | 2021-05-18 | 京东方科技集团股份有限公司 | Electronic substrate, driving method thereof and display device |
| US11735101B2 (en) | 2019-10-31 | 2023-08-22 | BOE MLED Technology Co., Ltd. | Electronic substrate and driving method thereof, and display device |
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| CN101738794B (en) | 2013-11-06 |
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