JPH07120641B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07120641B2 JPH07120641B2 JP2423589A JP2423589A JPH07120641B2 JP H07120641 B2 JPH07120641 B2 JP H07120641B2 JP 2423589 A JP2423589 A JP 2423589A JP 2423589 A JP2423589 A JP 2423589A JP H07120641 B2 JPH07120641 B2 JP H07120641B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- aluminum
- layer
- semiconductor device
- active element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Dicing (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体ペレット端近傍の配線層にクラックの
発生するのを抑制する保護手段（剛性保護手段）を備え
た半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a protection means (rigidity protection means) for suppressing the occurrence of cracks in a wiring layer near the edge of a semiconductor pellet.
従来の技術 従来、半導体ウエハの分割には第２図，第３図に示すよ
うに、半導体ペレットに分割すべき分断領域８の位置に
ダイヤモンドスクラバー，ダイシングソー，レーザスク
ラバー等の機械を用いて切断溝を設け、ゴムローラ等を
押し当てること（以下ブレークと呼ぶ）により、個々の
ペレットに分離している。なお、第２図は平面図、第３
図はＡ−Ａ′線に沿った断面図であり、各図中、半導体
基板1,フィールド絶縁膜2,配線層3,層間絶縁膜4,ボロ・
シリケートグラス（BPSG）膜6,窒化ケイ素膜７をもち、
その要部は能動素子Ｑからなるものである。2. Description of the Related Art Conventionally, as shown in FIGS. 2 and 3, when dividing a semiconductor wafer, cutting is performed using a machine such as a diamond scrubber, a dicing saw, and a laser scrubber at a position of a dividing region 8 to be divided into semiconductor pellets. By providing a groove and pressing a rubber roller or the like (hereinafter referred to as a break), the pellets are separated. Note that FIG. 2 is a plan view and FIG.
The figure is a cross-sectional view taken along the line AA '. In each figure, the semiconductor substrate 1, the field insulating film 2, the wiring layer 3, the interlayer insulating film 4,
It has a silicate glass (BPSG) film 6 and a silicon nitride film 7,
The main part is composed of an active element Q.
発明が解決しようとする課題 前記ブレーク工程により、第２図および第３図に点線20
で囲まれるペレット端近傍の能動素子Ｑの配線層３に、
ダメージを受ける。詳しくのべると、第３図の点線20で
囲まれる部には、スクライブラインに力（Ｆ）が、加わ
ったとき、第３図に示す距離（ｌ）に逆比例した大きさ
のモーメントが加わる。このモーメントによりアルミニ
ウム配線層３は、左右に引っぱられ、同アルミニウム配
線３にクラックが発生する。Problems to be Solved by the Invention Due to the break process, dotted lines 20 in FIGS.
In the wiring layer 3 of the active element Q near the end of the pellet surrounded by
receive damage. More specifically, when a force (F) is applied to the scribe line, a moment having a magnitude inversely proportional to the distance (l) shown in FIG. 3 is applied to the portion surrounded by the dotted line 20 in FIG. Due to this moment, the aluminum wiring layer 3 is pulled left and right, and a crack is generated in the aluminum wiring layer 3.
課題を解決するための手段 本発明は、上記した課題を解決するためになされるもの
であり、ペレット端近傍の能動素子部配線層上の層間絶
縁膜と表面保護膜の間に電気的に浮遊したアルミニウム
層を配置したものである。Means for Solving the Problems The present invention is made to solve the above problems, and electrically floats between the interlayer insulating film and the surface protective film on the active element wiring layer near the pellet end. The aluminum layer is formed.
作用 本発明によると、能動素子Ｑの上にアルミニウム層を配
置し、このアルミニウム層で前記モーメントの一部を吸
収するので、同モーメントは高さ方向に分散され、下層
のアルミニウム配線へのダメージが低減される。Effect According to the present invention, the aluminum layer is arranged on the active element Q, and this aluminum layer absorbs a part of the moment, so that the moment is dispersed in the height direction, and the aluminum wiring in the lower layer is damaged. Will be reduced.
実施例 以下、本発明の一実施例について、図面を参照しながら
説明する。第１図は、半導体装置のペレット端近傍の断
面図である。同図に示す様に能動素子Ｑのアルミニウム
配線層３の上の層間絶縁膜４′とBPSG膜６からなる表面
保護膜の間に配線層および半導体基板のいずれにも電気
的に接続されない浮遊したアルミニウム層５を配置す
る。このようにアルミニウム層５を設けることで、ブレ
イク工程時に、スクライブに力（Ｆ）が加わったとき、
第３図に示す0のモーメントは、第１図に示す1，
2のモーメントの和に、ほぼ等しくなる。これにより、
第１図中に示す点線10にかかるモーメントは、アルミニ
ウム層５が受けるモーメント分だけ減少されることにな
る。Embodiment One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of the vicinity of a pellet end of a semiconductor device. As shown in the figure, between the interlayer insulating film 4'on the aluminum wiring layer 3 of the active element Q and the surface protection film made of the BPSG film 6, there is a floating state that is not electrically connected to either the wiring layer or the semiconductor substrate. The aluminum layer 5 is arranged. By providing the aluminum layer 5 in this way, when force (F) is applied to the scribe during the breaking process,
The moment of 0 shown in FIG. 3 corresponds to 1 , shown in FIG.
It is almost equal to the sum of the two moments. This allows
The moment applied to the dotted line 10 shown in FIG. 1 is reduced by the moment received by the aluminum layer 5.
発明の効果 以上実施例で述べたように、アルミニウム配線層に受け
るブレイク工程による力を分散でき、アルミニウム配線
層の断線不良をなくすことができ、半導体製品の信頼性
を向上できる効果が得られる。EFFECTS OF THE INVENTION As described in the above embodiments, it is possible to disperse the force applied to the aluminum wiring layer due to the breaking process, eliminate disconnection defects in the aluminum wiring layer, and improve the reliability of semiconductor products.
第１図は、本発明の一実施例を示すものであって、ペレ
ット側近傍の断面図である。 第２図は、従来のペレット端近傍の平面図、第３図は同
じく第２図におけるＡ−Ａ′視断面図である。 １……半導体基板、２……フィールド絶縁膜、３……ア
ルミニウム配線層、4,4′……層間絶縁膜、５……アル
ミニウム層、６……BPSG層、７……窒化ケイ素膜、８…
…分断領域、Ｑ……能動素子。FIG. 1 shows an embodiment of the present invention and is a cross-sectional view near the pellet side. FIG. 2 is a plan view in the vicinity of a conventional pellet end, and FIG. 3 is a sectional view taken along the line AA ′ in FIG. 1 ... Semiconductor substrate, 2 ... Field insulating film, 3 ... Aluminum wiring layer, 4, 4 '... Interlayer insulating film, 5 ... Aluminum layer, 6 ... BPSG layer, 7 ... Silicon nitride film, 8 …
… Division area, Q …… Active element.
Claims (1)
間絶縁膜と表面保護膜との間に配線層および半導体基板
のいずれにも電気的に接続されないアルミニウム層を配
置したことを特徴とする半導体装置。1. An aluminum layer, which is not electrically connected to either a wiring layer or a semiconductor substrate, is arranged between an interlayer insulating film on a wiring layer of an active element near a pellet end and a surface protective film. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2423589A JPH07120641B2 (en) | 1989-02-02 | 1989-02-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2423589A JPH07120641B2 (en) | 1989-02-02 | 1989-02-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02205050A JPH02205050A (en) | 1990-08-14 |
| JPH07120641B2 true JPH07120641B2 (en) | 1995-12-20 |
Family
ID=12132596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2423589A Expired - Lifetime JPH07120641B2 (en) | 1989-02-02 | 1989-02-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120641B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3186266B2 (en) * | 1992-12-03 | 2001-07-11 | セイコーエプソン株式会社 | Semiconductor device |
-
1989
- 1989-02-02 JP JP2423589A patent/JPH07120641B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02205050A (en) | 1990-08-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100276854B1 (en) | Chip crack stop | |
| US7741196B2 (en) | Semiconductor wafer with improved crack protection | |
| JP3455762B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2598328B2 (en) | Semiconductor device and manufacturing method thereof | |
| US5157001A (en) | Method of dicing semiconductor wafer along protective film formed on scribe lines | |
| JPH07120641B2 (en) | Semiconductor device | |
| JPH09306872A (en) | Semiconductor device | |
| KR20020026995A (en) | Method for fabricating semiconductor device | |
| TWI714328B (en) | Manufacturing method of chip package and chip package | |
| JP2005044901A (en) | Semiconductor wafer dividing method | |
| JPH02308551A (en) | Semiconductor wafer | |
| JPS61292947A (en) | Semiconductor device | |
| JPS62112348A (en) | Manufacture of semiconductor device | |
| JPH0456250A (en) | Semiconductor wafer | |
| JPH01196850A (en) | Dicing of semiconductor wafer | |
| JPS5513904A (en) | Semiconductor device and its manufacturing method | |
| JPH053249A (en) | Semiconductor device and its manufacture | |
| CN118231222A (en) | Semiconductor structure, forming method thereof and forming method of chip | |
| JP2022143676A (en) | Semiconductor device | |
| JPH10223571A (en) | Manufacture of semiconductor device | |
| JPS60149151A (en) | Dicing method for semiconductor wafer | |
| CN118231343A (en) | Semiconductor structure, forming method thereof and forming method of chip | |
| JPH03203338A (en) | Semiconductor device | |
| JPH0429223B2 (en) | ||
| JPS63263742A (en) | Dicing scribe line |