JPH07117947B2 - FIFO device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a FIFO device.

2. Description of the Related Art In a multiprocessor system or the like, a FIFO is often used as a communication path for data transfer between processors. In that case, the data to be transferred may have priority, or meaningful data may be transferred at random.

For example, as shown in FIG. 3, when the processor B processes the tasks processed by the processor A in descending order of priority, or as shown in FIG. 4, task 1 in the processor A and task in the processor B 1 may operate while communicating, and task 2 in processor A and task 2 in processor B may operate while communicating.

In the past, in order to perform the above transfer, it was necessary to tag data or arrange FIFOs in parallel.

The tagging method requires encoding and decoding time to add, an increase in the transfer amount, and an extra memory for temporarily pooling low priority data when the data is received. Is not very efficient.

Further, in the method of arranging the FIFOs in parallel, the software is limited by the number of the FIFOs arranged and the hardware increases.

Problems to be Solved by the Invention In a conventional FIFO, it takes a lot of time to encode and decode tags, and by arranging a plurality of tags, hardware is increased and soft air is limited.

In view of such a problem, it is an object of the present invention to provide a FIFO device that can use all memory cells without waste and can emulate a FIFO system in which an arbitrary number of FIFOs are arranged in parallel.

Means for Solving the Problems In order to solve the problems, the present invention provides an input port including an input address port for inputting an address of a record to be written and an input data port for inputting data to be written, and a record to be read. An output port including an output address port for inputting an address and an output data port for outputting the read data, a memory having a plurality of records including a data section and a pointer section, and the data section among the plurality of records. A free-begin pointer for storing the start address of the record whose value is not set to, and a free-end pointer for storing the end address of the record whose value is not set in the data part among the plurality of records, The memory, the free beginner pointer, and the free end point In a FIFO device having a control circuit for reading / writing an interface, a full flag, and an empty flag, the memory is divided into a FIFO control record area and a data area, and reading is started in the FIFO control record area. FIFO consisting of a read begin record having an address in the data section and a write end record having the last written address in the data section
Have multiple control records, and in the initial state,
The control circuit gives the address of the record of the read begin of the FIFO control record to its data part, and further gives the address next to its own address to the pointer part other than the last address of the data area, The start address of the data area is given to the free begin pointer, and the end address of the data area is given to the free end pointer, and the full flag indicates that the contents of the free begin pointer and the free end pointer match. Asserted, otherwise negated, and the empty flag matches the address of the output address port Asserted when the content of the data part of the read begin of the FIFO control record matches its own address, and otherwise When negated, write In this case, after confirming that the full flag is not asserted, the data input from the input data port is written to the address (a address) of the content of the free begin pointer, and the pointer part of the a address is written. Write the contents to the Free Begin pointer section,
The FIFO corresponding to the address of the input address port
The address a is written in the pointer portion of the address (b address) of the write end content of the control record, and the read of the FIFO control record corresponding to the address of the input address port is written in the pointer portion of the address a. When writing a begin address, writing the a address to the data portion of the write end, and reading the data, the address (c address) is given to the output address port, and the empty flag is not asserted. After confirming, the content of the data portion of the read begin of the FIFO control record corresponding to the c address is addressed (d address).
Read the contents of the data part of the memory to the output data port, write the contents of the pointer part of the d address to the data part of the read begin, and write the contents address (e address) of the free end pointer. A FIFO device is characterized in that the d address is written to the pointer portion of the memory, and the d address is also written to the free end pointer.

By using the information of the FIFO control record provided in the working memory, it is possible to use all the memory cells wastefully and emulate any number of FIFO systems arranged in parallel.

Embodiments In view of the above-mentioned conventional drawbacks, the present invention is to emulate an arbitrary number of FIF systems arranged in parallel by using all the memory access without waste by using a FIFO control record provided in the memory. is there.

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of the FIFO device of the present invention, and FIG. 2 is a block diagram of the memory of the present invention.

As shown in FIG. 1, the FIFO device of the present invention includes a full flag 1, an input address port 2, an input data port 3, an empty flag 6, an output address port 7, an output data port 8, a control circuit 4, and a free begin pointer. 9, a free end pointer 10, and a memory 5. The address of the record to be written is input to the input address port 2, and the data to be written is input to the input data port 3. The address of the record to be read is input to the output address port 7, and the read data is output to the output data port 8.

As shown in FIG. 2, the memory 5 is composed of a plurality of records including a data part and a pointer part. A plurality of records in the memory 5 are divided into a FIFO control record area and a data area. The FIFO control record area is composed of a plurality of FIFO record controls including read begin records and write end records.

The operation of the FIFO device having the above configuration will be described with reference to the example of FIG.
There are two types of priority (0 is high and 1 is low).

In the memory, a FIFO control record of FIFO address 0 and FIFO address 1 is created as shown in FIG. The processor A inputs a high-priority task into the FIFO of address 0, and inputs a low-priority task into the FIFO of address 1. Further, the processor B checks whether the high-priority task exists in the FIFO of address 0, and if there is,
Output from the FIFO, otherwise output the low priority task from the FIFO at address 1.

The control circuit 4 refers to the FIFO control record corresponding to the input address. in this case,
The address is shifted to the left by 2 bits, and the address where the reading is started, that is, the read begin is stored in the address where 0 is added, and the address of the last written memory cell, that is, the write end is stored in the address where 2 is added. ing. By using these pieces of information, the full flag 1 and the empty flag 6 are output to control the data read / write.

Next, description will be made with reference to the drawings. FIG. 5 is a memory block diagram in the initial state, FIG. 6 is a block diagram showing a memory change at the time of writing, and FIG. 7 is a block diagram showing a memory change at the time of reading.

In the initial state, a FIFO control record indicating the state of each FIFO is created, and each read begin has its own address as its content. From the address next to the area of the control record of this FIFO, the remaining memory is called the data area, and each pointer portion points to the next address. Free begin refers to the start address of this data area, and free end refers to the end address of the data area.

The control of flags will be described. Full flag
It is asserted when writing while the free begin and free end match, and negated when reading. The empty flag is asserted when the content of the read begin of the FIFO control record corresponding to the address of the output address port matches its own address, and is negated otherwise.

Next, the writing method will be described. First, check the full flag to make sure it is not asserted. The procedure after this is as follows.

(1) Write to the data part of the address (a address) pointed to by the free begin (2) Write the contents of the pointer part of the a address to the free begin (3) Write the a address to the pointer part of the address (b address) pointed to by the write end (4) Write the address of the read begin to the pointer part of the a address (5) Write the a address to the write end Finally, the reading method will be described. First, give the address of the FIFO you want to read to the output address port, read the empty flag, and confirm that it is not asserted. The procedure after this is as follows.

(1) Read the data part of the address (c address) pointed to by the read begin (2) Write the contents of the poitan part of the c address to the read begin (3) c address in the pointer part of the address (d address) pointed to by the free end (4) Writing the c address to the free end Effect of the Invention As described above, according to the present invention, by providing the FIFO control record in the memory and controlling by the control circuit,
With this one FIFO device, it is possible to use memory cells wastefully and emulate any number of FIFO systems arranged in parallel. Therefore, a highly flexible system can be built without a large increase in hardware.

[Brief description of drawings]

FIG. 1 is a block diagram of a FIFO device of the present invention, FIG. 2 is a block diagram of a memory of the present invention, and FIG. 3 shows transfer of tasks having priorities between processors using a FIFO. Configuration diagram, FIG. 4 is a configuration diagram showing transfer between a plurality of tasks between processors, FIG. 5 is a configuration diagram showing a memory in an initial state, and FIG. 6 shows a change in memory contents at the time of writing. Representation diagram,
FIG. 7 is a block diagram showing changes in the memory contents at the time of reading. 1 …… Full flag, 2 …… Input address port, 3 ……
Input data port, 6 ... Empty flag, 7 ... Output address port, 8 ... Output data port, 9 ... Free begin, 10 ... Free end, 11-12 ... Processor, 13 ... FIFO, 14 ... 16 …… Priority tag, 17-18 …… Processor, 19 …… FIFO.

Claims (1)

[Claims] 1. An input port consisting of an input address port for inputting an address of a record to be written and an input data port for inputting data to be written, an output address port for inputting an address of a record to be read and the read data. An output port including an output data port to be output, a memory having a plurality of records including a data part and a pointer part, and a start address of the record in which a value is not set in the data part among the plurality of records are stored. A free-begin pointer, a free-end pointer for storing the final address of the record in which a value is not set in the data part among the plurality of records, and the memory, the free-begin pointer, and the free-end pointer Control circuit,
In a FIFO device having a full flag and an empty flag, the memory is divided into a FIFO control record area and a data area, and the FIFO control record area has a read start address in a data section. FIFO consisting of a begin record and a write end record having the last written address in the data section
Have multiple control records, and in the initial state,
The control circuit gives the address of the record of the read begin of the FIFO control record to its data part, and further gives the address next to its own address to the pointer part other than the last address of the data area, The start address of the data area is given to the free begin pointer, and the end address of the data area is given to the free end pointer, and the full flag indicates that the contents of the free begin pointer and the free end pointer match. Asserted, otherwise negated, and the empty flag matches the address of the output address port Asserted when the content of the data part of the read begin of the FIFO control record matches its own address, and otherwise When negated, write In this case, after confirming that the full flag is not asserted, the data input from the input data port is written to the address (a address) of the content of the free begin pointer, and the pointer part of the a address is written. Write the contents to the Free Begin pointer section,
The FIFO corresponding to the address of the input address port
The address a is written in the pointer portion of the address (b address) of the write end content of the control record, and the read of the FIFO control record corresponding to the address of the input address port is written in the pointer portion of the address a. When writing a begin address, writing the a address to the data portion of the write end, and reading the data, the address (c address) is given to the output address port, and the empty flag is not asserted. After confirming, the content of the data portion of the read begin of the FIFO control record corresponding to the c address is addressed (d address).
Read the contents of the data part of the memory to the output data port, write the contents of the pointer part of the d address to the data part of the read begin, and write the contents address (e address) of the free end pointer. A FIFO device, characterized in that the d address is written to the pointer portion of the memory, and the d address is also written to the free end pointer.