JPH07117941B2 - Clock management system - Google Patents

Description

The present invention relates to a timepiece management system that manages time synchronization between timepiece devices such as information processing devices and information transmission devices.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional timepiece management system disclosed in, for example, Japanese Patent Application Laid-Open No. 64-79855, in which 1 is a microprocessor of a main timepiece device M (hereinafter referred to as CP.
2) CPU of sub clock device S, 3 is main clock device M
The clock device 5 is provided with 5, a reference clock generation circuit for giving a clock reference clock to the clock device 3, 7 is a fixed period pulse output circuit for generating a pulse of a constant period in synchronization with the time of the clock device 3, 13 is a A counter that counts the pulses output by the frequency divider pulse output circuit 7 and generates an interrupt to the CPU 2 when a preset value is reached, 14 is a register for storing clock information, and 15 and 16 are main clock devices M An interface for exchanging data such as clock information between the sub clock device S and the sub clock device S, and 11 and 12 are CPU buses of the CPUs 1 and 2.

Next, the operation will be described.

First, the CPU 2 requests the CPU 1 to read the time data via the interfaces 15 and 16. When the CPU 1 receives this time data read request, it reads the time from the clock device 3 and reports it to the CPU 2 via the interfaces 15 and 16. Therefore, CPU2 registers the reported time data.
Write in 14 and memorize. At the same time, counter 13
Inputs a clock signal in units of seconds sent from the fixed-cycle pulse output circuit 7 of the main clock device M, and automatically counts in synchronization with this clock signal. The count value of counter 13 is "6
When reaching "0", this counter 13 interrupts the CPU2. When CPU2 receives this interrupt, it again interfaces
Request CPU1 to read the time data via 15, 16
Obtain new time data from PU1. Receiving the new time data, the CPU 2 writes and stores the new time data in place of the time data stored in the register 14 and sets the count value of the counter 13 to zero. By repeating the above operation, when CPU2 needs time data,
It is only necessary to read the count value of the time data counter 13 stored in the register 14, and the time data can be immediately obtained at the necessary time.

FIG. 4 is a block diagram showing another conventional timepiece management system in which the main timepiece device M and the subclock device S have a timepiece device. In the figure, 1 is a CPU of the main clock device M, 2
Is a CPU of the sub clock device S, 3 is a clock device provided in the main clock device M, 4 is a clock device provided in the sub clock device S, 5 is a reference clock generation circuit for giving a time reference clock to the clock device 3. Reference numeral 6 is a reference clock generation circuit for supplying a time reference clock to the clock device 4, reference numerals 15 and 16 are interfaces for exchanging data such as clock information between the main clock device M and the sub clock device S, and 11 and 12 are respective interfaces. CPU1,2 CPU
It's a bus.

Next, the operation will be described.

First, it is assumed that the timepiece device 3 and the timepiece device 4 are operating based on the time information that is initially set in advance. The CPU 2 of the sub timepiece device S, through the interfaces 15 and 16 at a constant cycle (for example, one minute cycle) of the main timepiece device C
Request PU1 to read the time data. When the CPU 1 receives the time data read request, it reads the time data from the clock device 3 and reports the time data to the CPU 2.
The CPU 2 sets the reported clock data in the clock device 4. By repeating the above operation, when the CPU 2 needs the time data, it is only necessary to read the time data counted by the timepiece device 4, and the time data can be immediately obtained at the necessary time.

[Problems to be Solved by the Invention]

Since the conventional timepiece device is configured as described above, in the conventional example shown in FIG. 3, when the system of the main timepiece device M goes down, the clock function of the sub timepiece device S is also stopped and the main timepiece device. Since the interfaces 15 and 16 for exchanging data between the device M and the sub clock device S are required, the cost is increased, and particularly when the sub clock devices S are plural, the cost is increased and the circuit becomes complicated. There was such a problem. Further, in the conventional example of FIG. 4, the synchronization of the time data of the main clock device M and the sub clock device S depends on the processing speed of the CPUs 1 and 2, and the time data of the sub clock device S depends on the accuracy difference of the reference clock. In addition to the possibility of reversing, there is a problem that the interfaces 15 and 16 for exchanging data between the main clock device M and the sub clock device S are required, and thus the cost is increased and the circuit is complicated similarly to the above. It was

The present invention has been made to solve the above problems, and the clock function of the sub timepiece device does not stop even if the main timepiece device goes down, and the time data of the main timepiece device and the subclock device are synchronized. However, it is an object of the present invention to obtain a timepiece management system that does not require an interface for exchanging data between the main timepiece device and the subclock device.

[Means for Solving the Problems]

In the timepiece management system according to the present invention, the first constant-cycle pulse output circuit provided in the main timepiece device outputs a pulse having a constant cycle in synchronization with the time data from the first timepiece device, and the subclock. The phase comparison circuit provided in the device is connected to the first fixed-cycle pulse output circuit through a single interface, and the phase of the pulse output from the first fixed-cycle pulse output circuit and the second fixed-cycle pulse output circuit. Compare with the phase of the pulse output from the output circuit, based on the phase comparison output of the phase comparison circuit by the clock correction circuit,
The reference clock for the second time is corrected, and the corrected clock thus corrected is output to the second timepiece device.

[Action]

Since the clock correction circuit according to the present invention corrects the reference clock for the second timepiece on the side of the sub timepiece by the reference clock for the first time on the side of the main timepiece, the main timepiece is temporarily down. Even in this case, the time can be counted by the corrected second reference clock for time, and the timepiece function in the sub timepiece device is prevented from being down. In addition, the interface between the main clock device and the sub clock device is provided with one that outputs a constant period pulse, so that the interface can be simplified.

Example of Invention

 An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a CPU of the main clock device M, 2 is a CPU of the sub clock device S, 3 is a clock device as a first clock device provided in the main clock device M, 4 is a sub clock device S. A clock device as a second clock device provided,
Reference numeral 5 is a reference clock generation circuit that gives a time reference clock to the timepiece device 3, 6 is a reference clock generation circuit that gives a time reference clock to the timepiece device 4, and 7 is a pulse of a constant cycle synchronized with the time of the timepiece device 3. A fixed-cycle pulse output circuit as a first fixed-cycle pulse output circuit to be generated, and a fixed-cycle pulse 8 as a second fixed-cycle pulse output circuit to generate a fixed-cycle pulse in synchronization with the time of the timepiece device 4. Output circuit, 9 is a periodic pulse output circuit 7
Of the output pulse of the fixed period pulse output circuit 8 and the phase comparison circuit which outputs this phase comparison result as a phase advance signal or a phase delay signal, 10 is based on the phase comparison result of the phase comparison circuit 9. Is a clock correction circuit for correcting the reference clock output from the reference clock generation circuit 6.

Next, the operation will be described.

First, it is assumed that the clock device 3 is initialized by the CPU 1 and the clock device 4 is initialized by the CPU 2 at the same time (accuracy within ± 30 seconds). The fixed-cycle pulse output circuit 7 outputs a pulse with a duty ratio of 1: 1 every minute in synchronization with the time of the timepiece device 3. As shown in the timing chart of FIG. 2, the phase comparison circuit 9 outputs the minute pulse output (the rising edge in the figure) of the one-minute pulse output as shown in FIG. hand,
The one-minute pulse output as shown in FIG. 2 (b) output from the fixed-cycle pulse output circuit 8 is sampled and the phases are compared.
If the polarity of the 1-minute pulse output of the constant-cycle pulse output circuit 8 at the time of sampling is insignificant (H level), the phase of the 1-minute pulse output of the constant-cycle pulse output circuit 8 is output by the constant-cycle pulse output circuit 7. It is judged to be “lagging” with respect to the phase of the 1-minute pulse output. That is, in this state, the time of the timepiece device 4 is “delayed” with respect to the time of the timepiece device 3. The clock correction circuit 10 is the phase comparison circuit 9
Based on the phase delay signal output from, the necessary advance correction is performed for the next time period of 1 minute. For example, if the clock accuracy of the reference clock generation circuits 5 and 6 is ± 100PPM, the maximum error between the time of the clock devices 3 and 4 that occurs in 1 minute is 12ms.
Therefore, the amount of advance correction required at this time is 12 ms or more. This correction is performed by raising the frequency of the reference clock source oscillation for a certain period of time, whereby the time becomes a smooth change, that is, a change without skipping or reversing the time. On the contrary, if the polarity of the 1-minute pulse output of the fixed-cycle pulse output circuit 8 at the time of sampling as shown in FIG. 2 (c) is significant (L level) as shown in FIG. 2 (d). It is determined that the phase of the 1-minute pulse output of the fixed-cycle pulse output circuit 8 is “advanced” with respect to the phase of the 1-minute pulse output of the fixed-cycle pulse output circuit 7. That is, in this state, the time of the clock device 4 is the time of the clock device 3
The state is "advancing" with respect to the time. The clock correction circuit 10 performs a necessary delay correction (correction similar to the advance correction) for the next one-minute time period based on the phase advance signal output from the phase comparison circuit 9.

With the above operation, the time of the clock device 4 is synchronized with the time of the clock device 3, and the CPU 2 synchronizes with the time of the clock device 3 from the clock device 4 via the CPU bus 12 when necessary. You can get the time.

In the above embodiment, the case where there is only one sub timepiece device S has been described, but the same effect can be obtained when there are a plurality of sub timepiece devices S. Further, the cycle of the fixed-cycle pulse output circuits 7 and 8, the clock accuracy of the reference clock generation circuits 5 and 6, the clock correction amount, and the like are not fixed and can be set arbitrarily. Note that the clock correction circuit 10 can use any circuit that performs the above operation, such as a voltage controlled oscillator (VCO) or a digital clock correction circuit.

〔The invention's effect〕

As described above, according to the present invention, the first constant-cycle pulse output circuit provided in the main timepiece device outputs a pulse having a constant cycle in synchronization with the time data from the first timepiece device, and The phase comparison circuit provided in the timepiece device is connected to the first constant-cycle pulse output circuit through one interface, and the phase of the pulse output from the first constant-cycle pulse output circuit and the second constant cycle are output. The phase of the pulse output from the pulse output circuit is compared, and the clock correction circuit outputs the second phase based on the phase comparison output of the phase comparison circuit.
Since the reference clock for time is corrected and the corrected clock is output to the second timepiece device, even if the main timepiece device goes down, the subclock device uses the reference clock for its own timepiece. By counting the time by
It is possible to prevent the clock function on the sub clock device side from going down and to prepare an interface for the main clock device and the sub clock device for one system that transmits a fixed-cycle pulse signal. There is an effect that the operation of the main clock device and the operation of the sub clock device can be synchronized with each other without performing a general software process.

[Brief description of drawings]

1 is a block diagram showing a timepiece management system according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of a phase comparison circuit of the present invention, and FIGS. 3 and 4 are conventional timepiece management systems. It is a block diagram showing. M is a main clock device, S is a sub clock device, 3 is a first clock device (clock device), 4 is a second clock device (clock device), and 7 is a first fixed-cycle pulse output circuit (fixed-cycle pulse). Output circuit), 8 is a second constant period pulse output circuit (constant period pulse output circuit), 9 is a phase comparison circuit, and 10 is a clock correction circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A clock management system for managing time so as to synchronize the time of a sub clock device with the time of a main clock device. The clock management system is provided in the main clock device and is output from a reference clock for a first time. A first clock device that counts a clock signal that is output and outputs it as time data; a first fixed-cycle pulse output circuit that outputs a pulse of a constant cycle in synchronization with the time data from the first watch device; A second clock device provided in the sub clock device for counting clock signals output from a second reference clock for time and outputting as time data, and time data from the second clock device. A second fixed-cycle pulse output circuit that outputs a fixed-cycle pulse in synchronization with the first fixed-cycle pulse output circuit through a single interface;
Based on a phase comparison circuit for comparing the phase of the pulse output from the first constant period pulse output circuit with the phase of the pulse output from the second constant period pulse output circuit, and based on the phase comparison output of the phase comparison circuit. And a clock correction circuit that corrects the reference clock for the second time and outputs the corrected clock to the second timepiece device.