JPH07115616A - Recording and reproducing device - Google Patents

Abstract

PURPOSE:To improve resistance against any error in a transmission line by recording address information for each code corresponding to a prescribed picture element and detecting this information at the time of reproduction. CONSTITUTION:At the time of recording, the number of data bytes in an output from a data packing circuit 3 is counted by an address information generation circuit 4 and for each of encoded data for 32 blocks, 96 kinds of address information are outputted for storing the encoded data of the first byte. Then, a synchronizing signal and an ID are added through an error correct code addition circuit 5 by a recorded signal processing circuit 6 and recorded in a medium 8 by a recording head 7. At the time of reproduction, three pieces of address information among the 96 kinds of address information are detected from the inputted and error-corrected data by an address information detection circuit 13 and when two or more pieces of address information are equal, those data are outputted as the address information. When the absence of any decode disabled flag is judged by an error correction circuit 16, those data are outputted as they are but when there is such a flag, decoded data are replaced with the data of a preceding field and a decoded conversion coefficient is outputted from an output terminal 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing apparatus for compressing a video signal of a television or the like and recording it on a VTR or the like.

[0002]

2. Description of the Related Art As a method of efficiently compressing information of a digitized image signal, variable length coding is applied to a prediction error from an adjacent sample or a quantized coefficient after orthogonal transform processing. Is effective. Variable-length coding gives a short code to the data with a high probability of occurrence and a long code to the data with a low probability of occurrence to encode the data before coding, thereby causing distortion due to coding. This is to reduce the average code amount without generating it.

However, when decoding a variable length code, it is necessary to decode the encoded data in order from the beginning, and it is not possible to decode from the middle of the data. That is, when variable length encoded data is transmitted or recorded,
Due to an error in the data that occurs on the transmission path, it becomes impossible to decode the data after that point.

Therefore, when variable length coding is used for transmission or recording, it is necessary to increase the resistance to the occurrence of errors on the transmission path. In the decoding error propagation prevention method disclosed in Japanese Patent Application Laid-Open No. 62-141875, by inserting a specific pattern not included in a codeword into a data string of a variable length code and detecting the pattern at the time of decoding,
The error propagation after that pattern is suppressed.

Further, in the recording / reproducing apparatus disclosed in Japanese Patent Laid-Open No. 4-86181 and the image coding apparatus disclosed in Japanese Patent Laid-Open No. 4-252666, boundary information of variable-length codes in sync blocks is used. Is added to each sync block for transmission, so that error propagation is contained within the range indicated by the boundary information.

[0006]

However, the above-mentioned first problem
In the conventional method, the specific pattern to be inserted into the data string of the variable-length code needs to be one that does not occur even by concatenation of codewords, so the length of the specific pattern is generally the maximum code length of the variable-length code. Will be longer than. This means that not only the redundancy becomes large, but also the error rate of the specific pattern becomes larger than the error rate of the variable length code data. If the specific pattern is erroneously detected, error propagation cannot be suppressed. Therefore, the error rate of the specific pattern needs to be sufficiently smaller than that of variable-length code data.

In the second and third methods, the error rate of the boundary information can be improved by adding the error correction code and the error detection code only to the boundary information, but it is added to each sync block. Because I have to
The redundancy increases accordingly. Also, stop error propagation,
In order to restart the variable length decoding from the location indicated by the boundary information, in addition to the boundary information of the codeword, it is necessary to transmit the information of the position on the screen corresponding to the codeword. Therefore,
The ratio of the additional information in the transmitted data becomes large, resulting in a decrease in coding efficiency.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a recording / reproducing apparatus which improves the resistance to errors in the transmission path without lowering the coding efficiency.

[0009]

In order to achieve this object, a recording / reproducing apparatus of the present invention uses a predetermined error correction for an image signal, with a region consisting of a predetermined number of pixels as a code amount control unit. A means for performing variable length coding so that the code amount can be stored in a code constituent block or less, and an error correction of the variable length coding result for each N sets of pixels obtained by dividing the code amount control unit into N. A means for outputting N sets of variable-length code data by head-filling in units of one symbol length of the code, and storing the variable-length code data string in the error correction code block for each symbol in a predetermined order. Means and said N in said error correction code block
Coded according to the above-mentioned configuration, having means for generating address information indicating an address of the first symbol of the data string of the set and means for storing the address information in a predetermined area of the error correction code block. When decoding a variable-length code, error correction processing is performed, an error correction impossible flag is set for uncorrectable symbols, a means for detecting the address information, and a predetermined timing for each of the N sets. Means for performing variable length decoding for each variable length code data string, and setting a non-decodable flag from the time of decoding a code including a symbol for which an error correction impossible flag is set to the decoding end timing of the set currently being decoded, When decoding a set for which address information cannot be detected, there is provided means for setting an undecodable flag during the entire decoding of the set.

Further, the address information is recorded on the recording medium a plurality of times, and at the time of reproduction, the address information is detected from a plurality of reproduction data by a majority decision.

[0011]

With the above-described structure, the address information representing the head position of the code word corresponding to N sets of pixels is arranged at a predetermined specific position in the error correction code constituent block. Therefore, since the head of the code word corresponding to the predetermined pixel can be determined from the position and the content where the address information is recorded, it is not necessary to add the information indicating the position on the screen. At the time of decoding, when the error correction impossible flag is detected and when the address information cannot be detected, the decoding impossible flag is set to detect the section that cannot be decoded with a simple configuration.

The address information is not required for each sync block, but may be provided for each code amount control unit. Furthermore, by setting the address information to indicate the address of the symbol unit in the error correction code, the redundancy by recording the address information multiple times becomes sufficiently small, and the coding efficiency is increased by the additional information for suppressing the error propagation. The resistance to errors in the transmission path is increased without reducing the error.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the image coding apparatus of the present invention will be described below with reference to the drawings. FIG. 1 is a signal processing block diagram in an embodiment of the present invention, FIG. 2 is a configuration diagram of an error correction code block in an embodiment of the present invention, and FIG. 3 is a recording track pattern diagram in an embodiment of the present invention.

In FIG. 1, 1 is a digital signal input terminal, 2 is a variable length coding circuit, 3 is a data packing circuit, 4 is an address information generating circuit, 5 is an error correction code adding circuit, 6 is a recording signal processing circuit, 7 is a recording head, 8 is a recording medium, 9 is a reproducing head, 10 is a reproduction signal processing circuit, 1
1 is an error correction processing circuit, 12 is a memory, 13 is an address information detection circuit, 14 is a memory read control circuit, 15 is a variable length decoding circuit, 16 is an error correction circuit, and 17 is a digital signal output terminal.

The operation of the recording / reproducing apparatus of this embodiment constructed as shown in FIG. 1 will be described below. In this embodiment, one field is 768 pixels horizontally and 25 pixels vertically.
The sampling amount is 6 pixels, and the code amount is 1 for each field.
It is assumed that the information is compressed to / 3 and the data of one field is recorded on three tracks.

Transform coefficient data obtained by orthogonally transforming a video signal in block units of 8 lines * 8 pixels and quantized with a quantization parameter such that a predetermined code amount is obtained for each field is digital signal input terminal 1. Enter more. In the variable length encoding circuit 2, the conversion data is subjected to a variable length encoding process, and encoded data having a variable code length is output. The data packing circuit 3 head-packs the encoded data in 1-byte units for every 32 blocks and outputs a 1-byte data string. However, dummy data of 1 byte or less is added to the end of the data string so that the code amount of the encoded data corresponding to each 32 blocks is an integral multiple of 1 byte. The structure of the error correction code constituent block is shown in FIG.

In FIG. 2, a1, a2, ..., A8
16 is an inner data block, of which a1
The leading 16 bytes of a12, a385 to a396, and a757 to a768 are address information storage areas. a769 to a816 are outer parity storage areas,
The remaining area is a variable length encoded data storage area,
Is the inner parity. In the error correction code adding circuit 5, the data packed in the byte unit is
The data is sequentially stored in the variable length coded data storage area.

In this embodiment, a1, a2 of FIG.
The variable-length coded data are stored in order of a768. The address information generation circuit 4 counts the number of bytes of the data output from the data packing circuit 3, and for each piece of encoded data corresponding to 32 blocks, determines the address at which the leading 1-byte encoded data is stored. Outputs the indicated address information. Since the video signal of one field consists of 3072 blocks, 3072 /
32 = 96 types of address information are output.

The size of the entire data storage area other than the error correction code in FIG. 2 is 85 * 128 * 6 = 65280 bytes. That is, the address can be represented by 16 bits. Therefore, 16 * 96 = 1536 bits = 192 bytes are the minimum required for the address information. The 192 byte address information is a1 to a12, a385 to a396, and a757 to a757 in the error correction code constituent block shown in FIG.
It stores in each of the three areas indicated by 768. That is, the same address information in one code amount control unit is
It is recorded on the recording medium in triplicate. After the outer and inner error correction codes are added by the error correction code adding circuit 5, the inner code is output every 93 bytes.

The recording signal processing circuit 6 adds the synchronization signal and the ID and performs recording modulation processing, and then records on the recording medium 8 via the recording head 7. The recording track pattern of three fields in one field is as shown in FIG. 3, and the inner data blocks a1 to a256 and a769 in FIG.
272 blocks of 784 are recorded on track 19 and
257-a512, a785-a800 are trucks 20
In addition, a513 to a768 and a801 to a816 are sequentially recorded on the track 21. Therefore, the address information is recorded on the three tracks at different positions in the width direction of the recording tape, as indicated by the shaded areas 22 in the tracks 19, 20, and 21 of FIG.

At the time of reproduction, a reproduction signal processing circuit 10 performs reproduction signal processing such as reproduction equalization and demodulation processing from a signal reproduced through the reproduction head 9, and an error correction processing circuit 11 performs error correction processing. If it cannot be corrected, an error flag is set. The corrected data and the error flag are temporarily stored in the memory 12. The address information detection circuit 13 detects three pieces of each of 96 types of address information from the error-corrected data and makes a majority decision.

That is, if two or more of the three data are the same, that value is output as address information. here,
If all three values are different, an address information undetectable flag indicating that the address could not be detected is set. The variable length decoding circuit 15 decodes the data output from the memory 12 and outputs the decoded data and the error flag. Decoding of the variable-length code is performed in units of 32 blocks, and if the error flag is set, the decoding disabled flag is set and output from that point until the end of the 32 blocks currently being decoded.
If the address information undetectable flag has been set, the undecodable flag is set in all the decoding results of 32 blocks corresponding to the address information.

The memory read control circuit 14 generates a read address of the memory 12 based on the address information for every 32 blocks, and thereafter controls the read of the memory 12 in accordance with the decoding process in the variable length decoding circuit 15. To do. The error correction circuit 16 outputs the decoded data in which the undecodable flag is not set as it is, and the decoded data in which the undecodable flag is set is replaced with the data of the previous field and is output. The decoded transform coefficient is output at the digital signal output terminal 17.

As described above, since the address information indicating the head position of each variable length code data string of N sets is stored in the predetermined position of the error correction code constituent block, the variable length code data string of each set is stored. Even if an uncorrectable error occurs on the transmission line by simply detecting the address information stored at a predetermined position without adding the position information on the screen corresponding to The variable length decoding can be restarted from the position indicated by the information.

When the error correction impossible flag is set, the decoding impossible flag is set from that point until the group currently being decoded ends, and when the address information cannot be detected, the address information is dealt with. By setting the undecodable flag for all the decoding results of the set, it is possible to detect the section that could not be decoded with a simple configuration. The decoding result is not output in the section in which the undecodable flag is set, and the decoded image is interpolated and output from the correctly decoded data to prevent the reproduction image from being broken.

When the error rate per byte in the recording / reproducing system is p, the address information is 16 as shown in this embodiment.
When expressed in bits, the error rate of each address information is about 2p
become. However, by writing the address information three times and performing detection by majority decision, the error rate of each address information is about 12p * p, which is sufficiently smaller than the error rate of the data representing the image information.

Further, by packing the variable length code data for every 32 blocks by head-packing in a unit of one symbol in the error correction code, when one symbol is 1 byte as in this embodiment, the data for every 32 blocks. A maximum of 7 bits of dummy data is added to the end of the column, and an average of 3.5 bits is generated, but the address information can be reduced by 3 bits compared to the case where all the data of the code amount control unit is packed head-to-head. . As a result, if the address information is recorded a plurality of times, the total amount of additional bits becomes small.

Further, in the case of this embodiment, the address information is
When recording is performed at different positions in the width direction of the recording tape on each of the three tracks, foreign matter adheres to the tape posts or the like to scratch the tape in the longitudinal direction, or instantaneous head clogging occurs. Even if the data of one track is lost due to
Since there is a high possibility that two of the three pieces of address information can be correctly reproduced, important address information can be protected during decoding.

Further, as shown in this embodiment, the error correction code is set to 1 for each of N sets of pixels obtained by dividing the code amount control unit into N.
In order to encode and decode data of one code amount control unit by packing so as to be an integral multiple of symbols, the coding side performs variable length coding and packing processing in parallel for each predetermined number of sets. After that, simply perform time division multiplexing, and on the decoding side, after error correction processing,
The decoding process can be performed in parallel for each of a predetermined number of sets on the N sets of encoded data strings whose start position is indicated by the address information. That is, parallel processing of variable length encoding and decoding can be easily realized, and the processing speed can be increased.

In this embodiment, the case where the variable length coding is performed on the quantized orthogonal transform coefficient and the address information is generated every 32 blocks has been described, but the present invention is not limited to this. The same effect can be obtained when variable length coding is performed on pixel-based data such as data after predictive coding, and address information is generated for each pixel obtained by dividing the code amount control unit into N.

[0031]

As described above, according to the present invention, the address information in the error correction code constituent block is recorded for each code corresponding to a predetermined pixel together with the variable length code data, and the address information is detected at the time of reproduction. As a result, it becomes possible to improve the tolerance against errors in the transmission path without reducing the coding efficiency due to the additional information for suppressing the error propagation.

[Brief description of drawings]

FIG. 1 is a signal processing block diagram of a recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an error correction code block according to an embodiment of the present invention.

FIG. 3 is a recording track pattern diagram in one embodiment of the present invention.

[Explanation of symbols]

 2 variable length coding circuit 3 data packing circuit 4 address information generation circuit 5 error correction code addition circuit 11 error correction processing circuit 12 memory 13 address information detection circuit 14 memory read control circuit 15 variable length decoding circuit 16 error correction circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H04N 7/32 H04N 7/137 A

Claims (4)

[Claims] 1. An image signal is subjected to variable length coding such that a region consisting of a predetermined number of pixels is used as a code amount control unit so that the code amount becomes equal to or less than a code amount that can be stored in a predetermined error correction code constituent block. Means, and for each of N sets of pixels obtained by dividing the code amount control unit by N, the variable length coding result is head-filled into a unit of one symbol length of an error correction code,
Means for outputting N sets of variable-length code data; means for storing the variable-length code data string in the error correction code block for each symbol in a predetermined order; and the N in the error correction code block. A recording / reproducing apparatus comprising: means for generating address information indicating an address of one symbol at the head of a set of data strings; and means for storing the address information in a predetermined area of the error correction code block. 2. A variable length coding result for each N sets of pixels obtained by dividing a region consisting of a predetermined number of pixels into N, and a data string of the N sets of variable length coding results in an error correction code constituent block. When decoding a code consisting of address information indicating the head position of an error correction code and an error correction code, means for performing an error correction process and setting an error correction impossible flag for an uncorrectable symbol, and detecting the address information. Means for sequentially performing variable-length decoding for each of the N sets of variable-length code data strings at a predetermined timing, and for a set currently being decoded from the time of decoding of a code including a symbol for which an error correction impossible flag is set. Means for setting an undecodable flag until the decoding end timing, and setting an undecodable flag during all the decoding of the set when the address information cannot be detected. Recording and reproducing apparatus. 3. The recording / reproducing apparatus according to claim 1, wherein the address information is recorded on the recording medium a plurality of times, and the address information is detected from a plurality of reproduction data by a majority decision during reproduction. 4. The recording / reproducing according to claim 3, wherein the address information is recorded one or more times respectively by different recording heads, and the recording areas of the address information on each recording track are different from each other in the recording tape width direction. apparatus.