JPH07114490A - Runaway monitoring device - Google Patents

Abstract

PURPOSE:To provide a runaway monitoring device capable of surely detecting runaway without making the hardware constitution a large scale as the runaway monitoring device which monitors the runaway of a microcomputer. CONSTITUTION:When a watchdog timer 20 counts a clock signal a prescribed number of times, a CPU 10 is reset. The CPU 10 resets the watchdog timer 20 by executing interruption processing at every prescribed time. however, when a task with the lowest priority is not executed while the interruption processing is being performed the prescribed number of times, the watchdog timer 20 is not reset. In this way, the microcomputer 10 can be surely reset when abnormality occurs in the microcomputer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a runaway monitoring device for resetting a microcomputer when it runs out of control.

[0002]

2. Description of the Related Art FIG. 1 shows an outline of an on-vehicle traveling position display device. In FIG. 1, 1 is a direction sensor,
The direction sensor 1 uses a geomagnetic sensor for detecting the absolute traveling direction of the automobile and an optical gyro for detecting the relative traveling direction of the automobile. Reference numeral 2 is a distance sensor that generates a pulse according to the number of rotations of the wheel, and 3 is various sensor signals such as an ON / OFF signal of a brake switch and a parking switch, and a power supply voltage monitoring signal. Reference numeral 4 is a sensor signal processing unit that processes sensor signals from the azimuth sensor 1, the distance sensor 2, and the like, and 5 is a GPS (Global Positioning System) receiver. The GPS receiver 5 receives radio waves transmitted from a plurality of satellites and performs calculation. By doing so, the position (latitude, longitude) of the receiving point can be obtained. Reference numeral 6 denotes a CD-ROM drive, and this CD-ROM drive 6 reads map data from a CD-ROM 7 in which map data is recorded. Reference numeral 8 denotes a display / operation unit installed in the vehicle interior. The display / operation unit 8 is provided on a liquid crystal display 8A for displaying a map and the current traveling position, direction, etc. of the automobile, and is provided in front of the liquid crystal display 8A. The touch panel 8B includes a switch for instructing enlargement or reduction of the display map,
A switch for instructing a route search, a switch for selecting a destination from the place names displayed on the liquid crystal display 8A, and the like are provided. Reference numeral 9 denotes an apparatus main body, and the apparatus main body 9 is installed in a trunk room or the like.

Next, the structure of the apparatus main body 9 will be described.
Reference numeral 10 denotes a CPU (central processing unit) for performing various calculations, 11
Is a ROM (read only memory) in which programs for various calculations performed by the CPU 9 are stored, 12 is data from the direction sensor 1, distance sensor 2, GPS receiver 5, CD-ROM drive 6 and the like, calculation results by the CPU 10, etc. Is a memory (DRAM) for storing data, 13 is a backup memory (SRAM) for holding necessary data even when power supply to the apparatus body 9 is stopped, and 14 is a character displayed on the liquid crystal display 8A. A memory (kanji, font ROM) in which patterns such as symbols are stored, 15 is an image processor for forming a display image based on map data, current position data of the vehicle, and 16 is a CPU 10
Map data, current position data and kanji output from
A memory (VRAM) for memorizing an image to be displayed on the liquid crystal display 8A by synthesizing Chinese characters such as a town name and a road name output from the font ROM 14 and a font, and 17 is a VRA
This is an RGB conversion circuit for converting the output data of M16 into a color signal, and the color signal is output from the RGB conversion circuit 17 to the liquid crystal display 8A. Reference numeral 18 is a communication interface. Reference numeral 19 denotes a runaway monitoring unit, which monitors the runaway of the CPU 10 and resets the CPU 10 when the CPU 10 runs out of control.

In FIG. 1, the output of the azimuth sensor 1 and the output of the distance sensor 2 are sent to the CPU 10 via the sensor processing unit 4.
Sent to. The CPU 10 calculates the current position of the vehicle and obtains the latitude and longitude of the current position. Also GPS
The current position is corrected based on the data from the receiver 5. Based on the present position thus obtained, the map data of the unit corresponding to the present position is read from the CD-ROM 7 by the CD-ROM drive 6, and this map data is stored in the memory (DRAM) 12 via the communication interface 18. Is stored. A part of the map data stored in the DRAM 12 is read by the CPU 10,
It is converted into image data by the image processor 15 and written in the image memory 16. The image data stored in the image memory 16 is converted into a color signal by the RGB conversion circuit 17 and sent to the liquid crystal display 8A, and a map of a predetermined range centering on the current position is displayed. Further, if the map data read from the DRAM 12 includes character codes and symbol codes, patterns corresponding to these character codes and symbol codes are read from the kanji and font ROM 14, and the liquid crystal display 8A displays characters such as place names together with the map. , Symbols such as school are displayed. In addition, the current position displayed on the liquid crystal display 8A is sequentially changed based on the traveling speed and traveling direction that are sequentially obtained as the automobile travels.

FIG. 2 shows the circuit configuration of the runaway monitoring section 19 of FIG. In FIG. 2, 10 is the CPU,
The CPU 10 is controlled by the OS and sequentially activates tasks having different priorities to execute various processes. Reference numeral 20 is a watchdog timer which constitutes the runaway monitoring section 19. The watchdog timer 20 is composed of a plurality of stages of flip-flops, and the output of the final stage flip-flop is connected to the reset terminal 22 of the CPU 10. The reset terminal 23 of the watchdog timer 20 is connected to the port 24 of the CPU 10,
The watchdog timer 20 is reset by a reset signal output from this port. 21
Is a clock generator, and the clock signal output from the clock generator 21 is a watchdog timer 20.
Is input to the first stage flip-flop.

Next, regarding the operation of the conventional runaway monitoring device,
This will be described with reference to FIGS. 9 to 13. FIG. 9 shows an idle task (task with the lowest priority) processing in the conventional example. In FIG. 9, in step S1, the CPU
HIGH is output from the port 24 of 10. Next, in step S2, the CPU 1 waits for a fixed time and in step S3, the CPU 1
LOW is output from the port 24 of 0. Step S above
A reset signal is generated in 1 to S3, and the watchdog timer 20 is reset by this reset signal.
Next, in step S4, the process returns to step S1 after waiting for a fixed time.

FIG. 10 shows the task processing of the conventional runaway monitoring apparatus with the passage of time, and FIG. 11 shows the count value of the watchdog timer 20 in the operation shown in FIG. As shown in FIG. 10, the CPU 10 executes task A, task B, task C, and task D (idle task) under the control of the OS. Among the tasks A to D, the task A has the highest priority, and the tasks B, C,
The task D has a lower priority, and the task D has the lowest priority. The generation of the reset signal shown in FIG. 9 is performed in task D. Task A in the traveling position display device is, for example, a task of drawing a map, task B is a task of reading data from the CD-ROM 7, task C is a task of determining whether the touch panel switch is on or off, and the like. Is.

As shown in FIG. 10, when a reset signal is applied to the watchdog timer 20 at the timing (# 1) (the timing of step S1 in FIG. 9) during the execution of the idle task (task D). The watchdog timer 20 is reset. After that, steps S2, S3 and S4 of FIG. 9 are executed, and when the system call is notified to the OS at the time when a certain time has passed in step S4, the processing of the idle task is interrupted and the task C is started. When the OS is notified of the system call of the task with the higher priority during the execution of the task C, the task A with the higher priority is activated. When task A ends, the processing of task C that was in the middle of execution is restarted. When the processing of the task C is completed, the processing of the idle task D is restarted, and the reset signal is applied to the watchdog timer 20 at the timing (# 2). Thereafter, as shown in FIG. 10, a task with a higher priority is preferentially executed,
Task D is executed during the period when tasks A to C are not processed,
A reset signal is applied to the watchdog timer 20 every time a predetermined time elapses during the execution period of the task D.

FIG. 11 shows the clock count value of the watchdog timer 20. Since the watchdog timer 20 is reset at the timing (# 1) in task D, the clock count value becomes 0 and the next reset signal The clock count value of the watchdog timer 20 increases until is applied. When the idle task is executed at an appropriate frequency as shown in FIGS. 10 and 11, the watchdog timer 20 to C
Since the watchdog timer 20 is reset before the reset signal is output to the PU 10, the CPU 10 is never reset.

FIGS. 12 and 13 show the above-mentioned conventional example.
The operation when a high-priority task is continuously executed and an idle task is not executed at an appropriate frequency is shown. After the reset signal is generated at the timing (# 1) in FIG. 12 and the watchdog timer 20 is reset, the tasks C, B, and A are continuously executed, and the task D is not executed for a predetermined time (t _R ) or more. The case is shown.
After the watchdog timer 20 is reset at the timing (# 1) and the count value of the watchdog timer 20 increases and reaches a predetermined count value (T _R ), the watchdog timer 20 resets the reset terminal 22 of the CPU 10.
A reset signal is output to the CPU 10, the CPU 10 is reset, the initial task is activated, and the initialization process is executed.
After that, task B is executed, and when task B ends, task D is executed and the timing when task D is being executed (# 2)
Then, the reset signal is applied to the watchdog timer 20.

As described above, in the conventional runaway monitoring device,
Watchdog timer 20 for tasks with the lowest priority
Since the reset signal for resetting the CPU is generated, the CPU 10 is frequently reset when the high-priority task is continued, and the initial task is executed each time, so there is a problem that the processing is interrupted. It was For example, in the case of the traveling position display device shown in FIG. 1, task A,
When B and C are continuously executed, the CPU 10 is frequently reset, and the initial task is executed each time the reset is performed. Therefore, a task for drawing a map (task A) and reading data from the CD-ROM 7 are performed. The task to be inserted (task B), the task to determine the on / off of the switch of the touch panel (task C), and the like are interrupted.

In order to solve such a conventional problem, the set time (t _R ) of the watchdog timer 20 may be lengthened, but in order to lengthen the set time (t _R ) of the watchdog timer 20. Must increase the number of flip-flops of the watchdog timer 20 or divide the clock generated by the clock generator 21 and apply the divided clock to the watchdog timer 20, which increases the hardware configuration. The cost was high.

[0013]

As described above, in the above-mentioned conventional example, the watchdog timer is not reset when the high-priority task is continuously executed, so that the CPU 10 is frequently reset. As a result, there is a problem that processing is interrupted each time, and if the set time of the watchdog timer is increased to solve this problem, the hardware configuration becomes large (for example, the number of flip-flop stages of the watchdog timer). Is large, or the hardware configuration is large, such as the need to add a separate divider to divide the clock) was.

The present invention solves the above-mentioned conventional problems, and the processing is not interrupted even when a task with a high priority is continuously executed without increasing the hardware configuration. It is intended to provide a runaway monitoring device.

[0015]

In order to achieve the above object, the present invention provides a processing means for executing a plurality of processings according to priority and executing a highest priority interrupt processing at every predetermined time. A watchdog timer that counts the clock signals output from the clock generator and resets the processing means when the count value reaches a predetermined value; an interrupt counter that counts the number of interrupt processes; Determination means for determining whether or not the process having the lowest priority among the plurality of processes is executed while the interrupt counter counts a predetermined value, and the interrupt process until the interrupt counter reaches a predetermined value. A means for outputting a reset signal to the watchdog timer every time, and the interrupt timer when it is determined that the process with the lowest priority is being executed when the interrupt counter reaches a predetermined value. Resetting the input counter and prohibiting the reset signal from being output to the watchdog timer when it is determined that the process with the lowest priority is not being executed when the interrupt counter reaches a predetermined value. Means and means are provided.

[0016]

According to the present invention, which has the above-mentioned structure, the clock signal output from the clock generator is counted by the watchdog timer, and the processing means is reset when the count value of the watchdog timer reaches a predetermined value. In a runaway monitoring device that prevents runaway by doing so, the interrupt counter counts the number of interrupt processes, and the determining means determines whether or not the process with the lowest priority has been executed. Until the number of interrupt processing reaches a predetermined value, the watchdog timer is reset for each interrupt processing, and when the number of interrupt processing reaches a predetermined value, the determination means executes the process with the lowest priority. Only if it resets the interrupt counter, the watchdog timer is reset.

[0017]

EXAMPLE An example of the present invention will be described below with reference to FIGS.
Will be explained together. The hardware configuration of this embodiment is the same as that of the conventional example, and is as shown in FIGS. FIG. 3 shows the processing of this embodiment. In this embodiment, tasks A, B,
The watchdog timer is reset by generating a reset signal by an interrupt process having a higher priority than C and D at regular time intervals. As shown in FIG. 3, when an interrupt occurs at regular intervals, it is determined in step S1 whether the count value of the interrupt counter is n or more (n is a positive integer). Step S
If YES is determined in step 1, it is determined in step S2 whether "1" is set in the idle flag. Step S2
If YES is determined in step S3, the process proceeds to step S3, and "0" is set in the idle flag. The idle flag is set to "0" in step S3, the interrupt counter is set to "0" in step S4, and the process proceeds to the next step S5. On the other hand, when it is determined in step S1 that the count value of the interrupt counter is not greater than or equal to n, the process proceeds to step S8, the interrupt counter is incremented, and the process proceeds to step S5. Step S5
Then, HIGH is output from the port of the CPU 10, and after waiting for a certain time in the next step 6, the CPU 1 is output in step S7.
Set port 0 to LOW. Steps S5, S6 above
In S7, the reset signal to the watchdog timer 20 is generated.

FIG. 4 shows the processing of the idle task (task D) having the lowest priority. When the task D is executed, the idle flag "1" is set.

Next, the operation of this embodiment will be described with reference to FIGS. As shown in FIG. 5, when an idle request (task D) is being executed and an interrupt request is generated at regular intervals, the processing shown in FIG. 3 is executed.
In step S1, the count value of the interrupt counter is the set value n
It is determined whether it is larger than (set value n = 6). If the interrupt count value is 5 at the stage before the interrupt, the determination in step S1 is NO, and the process proceeds to step S8 to increment the interrupt count value. Therefore, the interrupt count value is 5 + 1 = 6. When step S8 ends, the process proceeds to steps S5, S6, and S7 to output a reset signal to the watchdog timer 20 and reset the watchdog timer 20. When the above interrupt processing is completed, task C is executed as shown in FIG. 5, task A with a high priority is activated in the middle of task C, and the second interrupt processing is executed when task A ends. Be started. Since the interrupt count value was 6 in the first interrupt process, the determination in step S1 of the second interrupt process is YES, and the process proceeds to step S2. In step S2, the idle flag is 1
Whether or not it is determined, but since the idle task was being executed before the first interrupt processing, the determination in step S2 is YES, the process proceeds to steps S3 and S4, the idle flag is changed from 1 to 0, and the interrupt is performed. Change the count value from 6 to 0.
Next, in steps S5, S6 and S7, a reset signal is output to the watchdog timer 20 to reset the watchdog timer 20. Therefore, the count value of the watchdog timer 20 becomes zero. When the second interrupt process is completed, the interrupted process of task C is restarted, and when task C is completed, task B is activated. During the execution of task B, the third interrupt process is performed. In the third interrupt processing, the determination in step S1 is NO, and the interrupt counter is incremented in step S8, and the interrupt count value becomes 0 → 1. When step S8 ends, the process proceeds to steps S5, S6 and S7, the watchdog timer 20 is reset, and the third interrupt processing ends. Similarly, in the fourth interruption, the process proceeds to step S8, the interruption count value is incremented from 1 to 2, and further S5, S6, S
Go to 7 and reset the watchdog timer 20.
In the next fifth interrupt processing, the interrupt count value is incremented from 2 to 3 in step S8, and the subsequent step S5.
The watchdog timer 20 is reset in S6 and S7. In the next sixth interrupt processing, the interrupt count value is incremented from 3 to 4 in step S8,
The watchdog timer 20 is reset in 5, S6 and S7. When the sixth interrupt process is completed, the idle task is executed, so the idle flag is changed from 0 to 1 as shown in FIG. In the subsequent 7th interrupt processing, the interrupt count value is incremented from 4 → 5, and in the 8th interrupt processing, the interrupt count value is incremented from 5 → 6. The determination in step S1 of the next 9th interrupt processing is YES. This is because the interrupt count value was 6 in the eighth interrupt process, so that the answer is YES in step S1 of the ninth interrupt process. In the next step S3, it is determined whether the idle flag is 1, but as described above, the idle task is executed after the sixth interrupt processing and the idle flag is 1, so the determination in step S3 is YES, In the next step S3, the idle flag is changed from 1 to 0.
And the interrupt count value is changed from 6 to 0 in step S4. As described above, when the idle task is being executed while the interrupt processing at fixed time intervals is performed a plurality of times (six times in this embodiment), the count value of the watchdog timer 20 as shown in FIG. Is the set value (T
_{Since R} ) is not reached, the CPU 10 will not be reset.

7 and 8 show the case where the idle task is not executed while the interrupt processing is performed a plurality of times after the interrupt processing is performed at the timing (# 2), and the idle task is not executed. Therefore, 1 does not stand in the idle flag,
In each interrupt process, only steps S1 → S2 in FIG. 3 are repeated. Even if the interrupt process is repeated a plurality of times in this way, steps S5 to S7 are not executed and the reset signal cannot be output to the watchdog timer 20.
Therefore, as shown in FIG.
The count value is increased set value reached (T _R), CPU1
A reset signal is output to 0 and the CPU 10 is reset.

As described above, according to the above-described embodiment, since the reset signal of the watchdog timer 20 is generated in the interrupt processing of the highest priority, the CPU 10 can be executed even if the high priority task is continuously executed. It will not be reset frequently. Further, in the above embodiment, since the CPU 10 is reset when the idle task is not executed while the interrupt processing is performed a predetermined number of times,
There is no need to increase the hardware configuration such as increasing the number of stages of the watchdog timer or providing a frequency divider separately.

[0022]

The present invention has the above-described structure. According to the present invention, the CP can be used without increasing the hardware structure.
This has the advantage that the CPU can be reliably reset when U becomes abnormal.

[Brief description of drawings]

FIG. 1 is a block diagram of a traveling position display device including a runaway monitoring device of the present invention.

FIG. 2 is an electric circuit diagram of a runaway monitoring device according to an embodiment of the present invention.

FIG. 3 is a flow chart of the same embodiment.

FIG. 4 is a flowchart of the embodiment.

FIG. 5 is an operation explanatory diagram of the embodiment.

FIG. 6 is a diagram showing a count value of the watchdog timer of the embodiment.

FIG. 7 is an operation explanatory diagram of the embodiment.

FIG. 8 is a diagram showing a count value of the watchdog timer of the embodiment.

FIG. 9 is a flowchart of a conventional runaway monitoring device.

FIG. 10 is an operation explanatory diagram of a conventional example.

FIG. 11 is a diagram showing a count value of the watchdog timer of the conventional example.

FIG. 12 is an operation explanatory diagram of the conventional example.

FIG. 13 is a diagram showing a count value of the watchdog timer of the conventional example.

[Explanation of symbols]

 10 central processing unit 19 runaway monitoring circuit 20 watchdog timer 21 clock generator

Claims (1)

[Claims] 1. A processing means for executing a plurality of processes according to a priority and executing a highest priority interrupt process at every predetermined time, and a clock signal output from a clock generator. A watchdog timer that resets the processing means when reaching a predetermined value, an interrupt counter that counts the number of times of the interrupt processing, and among the plurality of processing while the interrupt counter counts a predetermined value. Determining means for determining whether or not the processing with the lowest priority has been executed, means for outputting a reset signal to the watchdog timer for each interrupt processing until the interrupt counter reaches a predetermined value, and A means for resetting the interrupt counter when it is determined that the process with the lowest priority is being executed when the interrupt counter reaches a predetermined value, and the interrupt counter are provided. A runaway monitoring apparatus comprising: means for prohibiting output of a reset signal to the watchdog timer when it is determined that the process with the lowest priority is not executed when the fixed value is reached. .