JP2007264856A - Cpu monitoring system, device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CPU monitoring system, device and method that can implement circuit simplification and cost reduction and facilitate the investigation of the cause of failures. <P>SOLUTION: An interrupt routine R is executed at constant time intervals to increment a counter and to clear a watchdog timer implemented in a CPU 20 if the count value is within a predetermined threshold. A reset task TS3 is executed at time intervals longer than the time intervals of execution of the interrupt routine R to clear the counter. The interrupt routine R can be executed irrespective of the priority of tasks executed by the CPU 20, and the reset task TS3 is set to the lowest priority of all the tasks executed by the CPU 20. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a CPU monitoring system, apparatus, and method for monitoring the execution status of a CPU (central processing unit).

  Conventionally, a watchdog timer is used to monitor the execution status of the CPU. Here, the watchdog timer has a function of resetting a counter for counting at regular intervals, and resets the CPU when the counter is not reset within a predetermined period. By constantly monitoring the CPU using such a watchdog timer, it is possible to restore the CPU in a runaway state.

  FIG. 3 is a timing chart showing an example of a conventional CPU monitoring method using a watchdog timer. As shown in FIG. 3, conventionally, an external watchdog timer (hereinafter referred to as WDT) 101 is provided outside the CPU 100 to be monitored, and the execution status of the CPU 100 is monitored using this external WDT 101. Consider a case where the CPU 100 executes two tasks, an A task TS11 and a B task TS12, and a task (WDT task TS13) for periodically clearing the external WDT 101. Of these tasks, the A task TS11 has the highest priority, the B task TS12 has the next highest priority, and the WDT task TS13 has the lowest priority.

  As shown in FIG. 3, the CPU 100 executes the A task TS11, the B task TS12, and the WDT task TS13 in a time division manner. Here, since the A task TS11 and the B task TS12 have a higher priority than the WDT task TS13, they are executed with priority over the WDT task TS13. The WDT task TS13 is executed at regular intervals, and the counter of the external WDT 101 is cleared by executing the WDT task TS13. The WDT task TS13 is executed at a time interval of about 3 seconds, for example. Therefore, the time intervals T11 and T12 for clearing the counter of the external WDT 101 are about 3 seconds.

  Assume that the A task TS11 is executed after the counter of the external WDT 101 is cleared, and the A task TS11 runs away for some reason. As described above, since the A task TS11 has the highest priority, if the A task TS11 runs away, the A task TS11 occupies the CPU 100. For this reason, the WDT task TS13 is not executed, the counter of the external WDT 101 is not cleared, and the counter of the external WDT 101 is continuously incremented. When a predetermined period T13 (for example, about 10 seconds) elapses after the counter of the external WDT 101 is cleared, the external WDT 101 times out and outputs a reset signal to the CPU 100. As a result, the CPU 100 is reset.

Patent Document 1 below saves the runaway detection timer count value and information in addition to the context information of each task that was saved / saved and restored / set when switching the task to be executed. A method and apparatus for detecting task runaway by returning is proposed.
JP-A-2005-107757

  Incidentally, in the conventional CPU monitoring method described with reference to FIG. 3, the CPU 100 is monitored using the external WDT 101. Here, some CPUs have a built-in WDT, but the built-in WDT has a short time interval of reset (counter reset) of about 1.5 seconds, even if it does not lead to a runaway. The reset may not be performed due to a temporary load. For this reason, in the example shown in FIG. 3, an external WDT having a longer reset time interval is provided. However, when the external WDT is provided, there is a problem that the circuit becomes complicated and the cost increases.

  Conventionally, the CPU 100 is reset due to the time-out of the external WDT 101, but there is almost no information regarding tasks saved and saved when the CPU 100 is reset. For this reason, it takes time to pursue the cause of the reset after the CPU 100 is reset, and it is difficult to perform debugging.

  The present invention has been made in view of the above circumstances, and provides a CPU monitoring system, apparatus, and method capable of simplifying the circuit and reducing the cost and easily pursuing the cause of the failure. Objective.

In order to solve the above-described problem, a CPU monitoring system according to the present invention is a CPU monitoring system that monitors the execution status of a CPU having a watchdog timer. Means for counting and interrupting means for clearing the watchdog timer when the count value of the counting means is within a predetermined value, and for each second predetermined time longer than the first predetermined period, the count And reset means for clearing the count value of the means.
In order to solve the above problems, a CPU monitoring system according to the present invention is a CPU monitoring system that monitors the execution status of a CPU including a watchdog timer. When the count value is within a predetermined value, an interrupt routine for clearing the watchdog timer is executed every first predetermined time, and a reset task for clearing the count value of the counting means is executed in the first predetermined value. And a task control unit that is executed every second predetermined time longer than the period.
Here, in the CPU monitoring system of the present invention, the interrupt routine can be executed regardless of the priority of the task executed by the CPU, and the reset task is the most of the tasks executed by the CPU. It is characterized by a low priority.
In the CPU monitoring system of the present invention, when the task control means causes a task other than the reset task to be executed, a control is performed to set a flag at the start of execution and clear the flag set at the end of execution. It is characterized by.
Furthermore, the CPU monitoring system of the present invention is characterized in that, when the count value of the counting means is larger than the predetermined value, the interrupt routine saves information on a task for which the flag is set. It is said.
In order to solve the above-described problem, a CPU monitoring device according to the present invention is a CPU monitoring device that monitors the execution status of a CPU including a watchdog timer. The CPU monitoring device counts the counting unit for each first predetermined time. Means for counting and interrupting means for clearing the watchdog timer when the count value of the counting means is within a predetermined value, and for each second predetermined time longer than the first predetermined period, the count And reset means for clearing the count value of the means.
The CPU monitoring device of the present invention is a CPU monitoring device that monitors the execution status of a CPU having a watchdog timer. The CPU monitoring device counts the counting means, and the counting means counts the count value of the counting means. If not, an interrupt routine for clearing the watchdog timer is executed every first predetermined time, and a reset task for clearing the count value of the counting means is set to a second time longer than the first predetermined period. And a task control unit that is executed every predetermined time.
Furthermore, in the CPU monitoring device of the present invention, the interrupt routine can be executed regardless of the priority of the task executed by the CPU, and the reset task is the lowest of the tasks executed by the CPU. It is characterized in that priority is set.
In order to solve the above-mentioned problem, a CPU monitoring method of the present invention is a CPU monitoring method for monitoring an execution status of a CPU including a watchdog timer, wherein a first step of performing counting by a counting means every first predetermined time; A second step of clearing the count value of the counting means every second predetermined time longer than the first predetermined period, and the watchdog timer if the count value of the counting means is within a predetermined value And a third step of clearing.
In the CPU monitoring method of the present invention, the first step is executed regardless of the priority of the task executed by the CPU, and the second step is the lowest task among the tasks executed by the CPU. It is characterized in that the priority is set and executed.
The CPU monitoring method of the present invention includes a step of setting a flag at the start of execution when the CPU executes a task, and a step of clearing the flag set at the end of execution of the task. .
Furthermore, the CPU monitoring method of the present invention includes a fourth step of evacuating information relating to the task for which the flag is set when the count value of the counting means is larger than the predetermined value. It is said.

According to the present invention, the counting means counts every first predetermined time, the count value of the counting means is cleared every second predetermined time longer than the first predetermined period, and the count value of the counting means is The watchdog timer is cleared when it is within the predetermined value, and the watchdog timer is not cleared when the count value is larger than the predetermined value, so the CPU is monitored even without an external watchdog timer. be able to. As a result, the circuit can be simplified and the cost can be reduced.
In addition, when a task is executed by the CPU, a flag is set at the start of execution, and the flag set at the end of execution of the task is cleared. Therefore, it is easy to identify a task whose flag is set due to runaway or the like. Can do. In addition, the cause of the failure can be easily pursued by saving the information on the task with the flag set.

  Hereinafter, a CPU monitoring system, apparatus, and method according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of a PHS base station including a CPU monitoring system according to the present invention. In this embodiment, a case where the CPU monitoring system of the present invention is applied to a PHS base station will be described as an example. However, the CPU monitoring system of the present invention performs monitoring of a CPU provided in a PHS base station. However, the present invention can be applied to monitoring of any CPU.

  As shown in FIG. 1, the PHS base station 10 includes first and second transmission / reception devices 11 and 12, a modem unit 13, a control unit 14, and a DSU (Digital Service Unit) 15. The first and second transmission / reception devices 11 and 12 are high-frequency circuits (including antennas) that perform wireless communication with a PHS terminal (communication terminal device), and output a reception signal received from the PHS terminal to the modem unit 13. The transmission signal input from the modem unit 13 is transmitted to the PHS terminal.

  The modem unit 13 decodes the reception signal or generates (encodes) the transmission signal, and controls a signal (decoded audio signal or decoded image signal) obtained by demodulating the reception signal. 14 for output. Also, the audio signal and image signal for transmission output from the control unit 14 are encoded to generate an encoded audio signal and an encoded image signal, which are output to the first transmission / reception device 11 or the second transmission / reception device 12.

  The control unit 14 includes a CPU 20, an audio / image conversion unit 21, an SDRAM (Synchronous DRAM (Dynamic Random Access Memory)) 22, an SRAM (Static Random Access Memory) 23, a Flash ROM (Flash Read Only Memory) 24, a BOOTROM (Boot Read Only Memory). ) 25, an FPGA (Field Programmable Gate Array) 26, and a USB unit 27.

  As shown in FIG. 1, the control unit 14 includes a CPU 20, an audio / image conversion unit 21, an SDRAM 22, an SRAM 23, a FlashROM 24, a BOOTROM 25, an FPGA 26, and a USB unit 27 connected by a bus line B, and is stored in the SDRAM 22. Data transmission / reception between the modem unit 13 and the DSU 15 is controlled based on the control program.

  The CPU 20 includes a task control unit 20a and a watch dog timer (WDT) 20b. Here, for the sake of convenience of explanation, the description will be made assuming that the CPU 20 includes the task control unit 20a. However, the task control unit 20a is realized by software by the CPU 20 executing a control program stored in the SDRAM 22. It may be a thing. The task control unit 20a controls the execution of various tasks executed by the CPU 20. Although details will be described later, in this embodiment, the CPU 20 executes an interrupt routine. The task control unit 20a also controls the execution of this interrupt routine.

  Furthermore, when the task is executed by the CPU 20, the task control unit 20a sets a flag at the start of execution and performs control to clear the flag set at the end of execution (including when the task is temporarily stopped). This control is performed for each task executed by the CPU 20. In other words, a different flag is set for each task, and when the execution of a certain task is started, the flag of that task is set, and when the task ends and execution of a different task starts, the end The flag of the task to be executed is cleared, and the flag of the task to be executed is set.

  The WDT 20b is provided with a counter for measuring time, and resets the CPU 20 when the counter counts a certain value without being reset. The WDT 20b is built in the CPU 20. Although details will be described later, the WDT 20b is reset at predetermined time intervals by an interrupt routine executed by the CPU 20.

  Under the control of the CPU 20, the audio / image conversion unit 21 converts the above-described decoded audio signal and decoded image signal into an audio signal and an image signal suitable for transmission to the network, and outputs them to the CPU 20. Also, the audio signal and image signal from the line network input from the CPU 20 are converted into an audio signal and image signal for the PHS terminal and output to the modem unit 13.

  The SDRAM 22 stores a control program executed by the CPU 20. The SDRAM 22 is provided with storage areas 22a and 22b. The storage area 22a stores a count value that is incremented by execution of the interrupt routine in the CPU 20 and cleared by execution of a reset task (details will be described later). Although details will be described later, the storage area 22a is used as a counter. The storage area 22b stores a flag that is set when the CPU 20 starts executing the task and is cleared when the execution is completed.

  The SRAM 23 temporarily stores processing results of the CPU 20 and the like. The flash ROM 24 stores, for example, a control program before deployment downloaded from the host control system via the DSU 15. The BOOTROM 25 stores a boot program (startup program) executed by the CPU 20 when the PHS base station 10 is started. The FPGA 26 is a programmable logic circuit provided for controlling hardware such as the modem unit 13 and the DSU 15. The USB unit 27 is an interface circuit for exchanging data with an external device such as a maintenance computer.

  Next, the operation of the CPU monitoring system of the present invention applied to the PHS base station 10 described above will be described. FIG. 2 is a timing chart showing a CPU monitoring method according to an embodiment of the present invention. As shown in FIG. 2, in the present embodiment, the CPU 20 executes the interrupt routine R and the reset task TS3, and the execution status of the CPU 20 is monitored by these. Here, let us consider a case where the CPU 20 executes two tasks, the A task TS1 and the B task TS2, in addition to the interrupt routine R and the reset task TS3.

  The task control unit 20a of the CPU 20 controls the start / end of execution of the A task TS1, the B task TS2, and the reset task TS3 as shown in FIG. Specifically, the task control unit 20a causes the tasks TS1, TS2 and the reset task TS3 to be executed in a time division manner. Of these tasks, the A task TS1 has the highest priority, and the B task TS2 has the next highest priority. The reset task TS3 is set to the lowest priority among the tasks executed by the CPU 20. That is, the A task TS1 and the B task TS2 have higher priority than the reset task TS3, and therefore are executed with priority over the reset task TS3. The interrupt routine R can be executed regardless of the priority of the task executed by the CPU 20.

  The task control unit 20 causes the interrupt routine R to be executed at regular intervals (for example, every 100 milliseconds), and the reset task TS3 is performed at regular intervals (for example, every 3 seconds) longer than the time interval of the interrupt routine R. Control to be executed. When a task other than the reset task TS3 is to be executed, a flag indicating that the execution of the task is started is stored in the storage area 22b of the SDRAM 22 at the start of execution, and the flag is set at the end of execution. Control to clear. This flag is prepared for each task.

  Each time the interrupt routine R is executed, the interrupt routine R performs a process of incrementing a value (count value) stored in the storage area 22a of the SDRAM 22 used as a counter, and the count value is within a predetermined threshold value set in advance. Judge whether there is. For example, the threshold is set to the number of times the interrupt routine R is executed in 10 seconds. In the following description, for convenience, the process in which the interrupt routine R increments the count value stored in the storage area 22a is referred to as “counter increment”.

  Further, the interrupt routine R performs a process of clearing the WDT 20b provided in the CPU 20 when the count value stored in the storage area 22a is within a predetermined threshold based on the above determination. Thereby, when the count value is within a predetermined threshold, the WDT 20b is cleared, for example, every 100 milliseconds. On the other hand, when the count value stored in the storage area 22a is larger than a predetermined threshold, information related to the task for which the flag is set in the storage area 22b is saved in the SDRAM 22, for example.

  Now, assuming that the operation is started by turning on the power of the base station 10 or the like, the control program stored in the SDRAM 22 is read out and executed by the CPU 20. The task control unit 20a of the CPU 20 causes the interrupt routine R to be executed when a predetermined time (for example, 100 milliseconds) elapses after the operation of the CPU 20 is started. When the interrupt routine R is executed, the counter is incremented (step S1), and it is determined whether the count value is within a threshold value (step S2).

  Here, in the initial state, since the count value of the counter is set to “0”, the determination result of the determination process in step S2 is “YES”. As a result, a reset signal is output from the interrupt routine R to the WDT 20b (step S3), and the WDT 20b is cleared (step S4).

  Next, it is assumed that the task control unit 20a starts executing the A task TS1. When the execution of the A task TS1 is started, the task control unit 20a stores a flag indicating that the execution of the A task TS1 has started in the storage area 22b of the SDRAM 22 so that the flag for the A task TS1 (hereinafter, referred to as the A task TS1). A flag) is set (step S5).

  Next, it is assumed that there is a request to start execution of the B task TS2 while the A task TS1 is being executed. At this time, the task control unit 20a first ends the A task TS1 and clears the A flag (step S6). Next, the execution of the B task TS2 is started, and a flag indicating that the execution of the B task TS2 is started is stored in the storage area 22b of the SDRAM 22 to thereby set a flag for the B task TS2 (hereinafter referred to as B flag). Set (step S5).

  Next, when a predetermined time (for example, 3 seconds) elapses after the operation of the CPU 20 is started, the task control unit 20a causes the reset task TS3 to be executed. At this time, the task control unit 20a ends the B task TS2 and clears the B flag before starting the execution of the reset task TS3 (step S8). When the reset task TS3 is executed, a process of clearing the value (count value) stored in the storage area 22a of the SDRAM 22 used as a counter is performed (step S9). With this process, the count value of the counter is set to “0”. In the following description, for the sake of convenience, the process in which the reset task TS3 clears the count value stored in the storage area 22a is referred to as “counter clear”.

  If the A task TS1 is executed after the reset task TS3 is completed, the task control unit 20a sets the A flag (step S10). Similarly, when a plurality of tasks are normally executed by the CPU 20, the task control unit 20b controls the execution and termination of the task, and sets and clears a flag for the task. In addition, the interrupt routine R is executed at a constant time interval (for example, 100 milliseconds), the counter is incremented and the WDT 20b is cleared, and the reset task TS3 is executed at a predetermined time interval (for example, 3 seconds). The counter is cleared.

  Consider the case where the execution of the B task TS2 is started, the B flag is set (step S11), and then the B task TS2 runs away for some reason. Even when the B task TS2 runs away, the interrupt routine R can be executed regardless of the priority of the task executed by the CPU 20. Therefore, even when the B task TS2 runs out of control, the counter is incremented at regular time intervals, and if the count value is within the threshold value, a reset signal is output from the interrupt routine R to the WDT 20b (step S1). S12), the WDT 20b is cleared (step S13).

  On the other hand, the reset task TS3 has a lower priority than the B task TS2, and therefore cannot be executed if the B task TS2 runs away. For this reason, the counter is not cleared while the B task TS2 runs out of control. As a result, the increment of the counter by the interrupt routine R is continued, and the count value gradually increases. When the interrupt routine R is executed after a predetermined time has elapsed since the B task TS2 has runaway (specifically, after about 20 seconds have elapsed since the counter was last cleared by the reset task TS3), the counter Is incremented (step S14), and it is determined whether the count value is within a threshold value (step S15). If the count value exceeds the threshold value, the determination result in step S15 is “NO”.

  When the determination result of the determination process performed in the interrupt routine R is “NO”, the interrupt routine R first searches the storage area 22b of the SDRAM 22 for a set flag (an uncleared flag) and is cleared. If there is a non-existing flag, information regarding the task regarding this flag is saved in the SDRAM 22 (step S16). In the example shown in FIG. 2, since the B flag is set in step S <b> 11 and clearing is not performed, information regarding the B task TS <b> 2 is saved in the SDRAM 22.

  If the determination result in step S15 is “NO”, no reset signal is transmitted from the interrupt routine R to the WDT 20b. For this reason, the WDT 20b is not cleared and the count in the WDT 20b is continued. When a predetermined time elapses after the WDT 20b is not cleared, the WDT 20b times out and the CPU 20 is reset.

  As described above, in this embodiment, the interrupt routine R is executed at regular time intervals to increment the counter, and the reset task TS3 is executed at a time interval longer than the time interval at which the interrupt routine R is executed. The counter is cleared. Here, the interrupt routine R can be executed regardless of the priority of the task executed by the CPU 20, but the reset task TS3 is set to the lowest priority among the tasks executed by the CPU 20, so It becomes impossible to run if runaway. If the count value of the counter is within a predetermined threshold, the WDT 20b is cleared by the interrupt routine R. However, if the count value of the counter is larger than the predetermined threshold, the WDT 20b is not cleared and the CPU 20 is reset by the WDT 20b. As described above, even without the external WDT 101 shown in FIG. 3, the execution status of the CPU 20 can be monitored, and the circuit can be simplified and the cost can be reduced.

  In the present embodiment, when a task other than the reset task TS3 is executed, a flag is set at the start of execution, and the flag set at the end of execution is cleared. When the count value of the counter is larger than a predetermined threshold value, the interrupt routine R saves information related to the task for which the flag remains set (the flag is not cleared). For this reason, it is possible to easily identify a task in which a failure such as a runaway has occurred, thereby easily pursuing the cause of the failure.

  Although the CPU monitoring system, apparatus, and method according to the embodiment of the present invention have been described above, the present invention is not limited to the above-described embodiment, and can be freely changed within the scope of the present invention. For example, in the embodiment described above, the case where the count value is stored in the storage area 22a of the SDRAM 22 and the interrupt routine R increments the count value has been described as an example, but the counter that increments according to the instruction of the interrupt routine R has been described. The structure which provided this may be sufficient.

It is a block diagram which shows the principal part structure of a PHS base station provided with the CPU monitoring system of this invention. 6 is a timing chart illustrating a CPU monitoring method according to an embodiment of the present invention. It is a timing chart which shows an example of the conventional CPU monitoring method using a watchdog timer.

Explanation of symbols

20 CPU
20a Task control unit 20b Watchdog timer 22a, 22b Storage area R Interrupt routine TS3 Reset task

Claims (12)

In a CPU monitoring system for monitoring the execution status of a CPU having a watchdog timer,
A counting means for counting,
Interrupt means for causing the counting means to count at each first predetermined time and clearing the watchdog timer when the count value of the counting means is within a predetermined value;
A CPU monitoring system comprising: a reset unit that clears a count value of the count unit every second predetermined time longer than the first predetermined period. In a CPU monitoring system for monitoring the execution status of a CPU having a watchdog timer,
A counting means for counting,
When the count value of the count means is within a predetermined value, an interrupt routine for clearing the watchdog timer is executed every first predetermined time, and the count value of the count means is set. And a task control unit that executes a reset task to be cleared every second predetermined time longer than the first predetermined period. The interrupt routine can be executed regardless of the priority of the task executed by the CPU,
The CPU monitoring system according to claim 2, wherein the reset task has a lowest priority among tasks executed by the CPU.   The said task control means performs the control which sets a flag at the time of execution start, and clears the flag set at the time of execution completion, when performing tasks other than the said reset task. 3. The CPU monitoring system according to 3.   5. The CPU monitoring system according to claim 4, wherein when the count value of the counting means is larger than the predetermined value, the interrupt routine saves information on a task for which the flag is set. . In a CPU monitoring device that monitors the execution status of a CPU having a watchdog timer,
A counting means for counting,
Interrupt means for causing the counting means to count at each first predetermined time and clearing the watchdog timer when the count value of the counting means is within a predetermined value;
A CPU monitoring device comprising: a reset unit that clears a count value of the count unit every second predetermined time longer than the first predetermined period. In a CPU monitoring device that monitors the execution status of a CPU having a watchdog timer,
A counting means for counting,
When the count value of the count means is within a predetermined value, an interrupt routine for clearing the watchdog timer is executed every first predetermined time, and the count value of the count means is set. A CPU monitoring device comprising: task control means for executing a reset task to be cleared every second predetermined time longer than the first predetermined period. The interrupt routine can be executed regardless of the priority of the task executed by the CPU,
The CPU monitoring device according to claim 7, wherein the reset task has a lowest priority among tasks executed by the CPU. In a CPU monitoring method for monitoring the execution status of a CPU having a watchdog timer,
A first step of counting by a counting means every first predetermined time;
A second step of clearing the count value of the counting means every second predetermined time longer than the first predetermined period;
And a third step of clearing the watchdog timer when the count value of the counting means is within a predetermined value. The first step is executed regardless of the priority of the task executed by the CPU,
The CPU monitoring method according to claim 9, wherein the second step is executed by setting a lowest priority among tasks executed by the CPU. Setting a flag at the start of execution when the CPU executes a task;
The CPU monitoring method according to claim 9, further comprising: clearing a flag set at the end of execution of the task. 12. The method according to claim 9, further comprising a fourth step of saving information related to a task for which the flag is set when the count value of the counting means is larger than the predetermined value. The CPU monitoring method according to any one of the above.

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