JPH07114343B2 - Integrated circuit for signal processing - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal processing integrated circuit, and more particularly to a signal processing integrated circuit for forming a digital filter by digital signal processing.

[Conventional technology]

Conventionally, this kind of signal processing integrated circuit is provided with a data storage unit, an arithmetic unit, a control unit, a coefficient storage unit for storing coefficients necessary for arithmetic processing, and the like, so that the data storage unit is accessed each time the arithmetic processing is performed. Is configured.

FIG. 4 is a signal processing integrated circuit diagram showing an example of such a conventional technique.

As shown in FIG. 4, in this conventional example, a data storage unit 1 that stores data necessary for processing, a coefficient storage unit 3 that stores coefficients necessary for processing, and a data pointer that determines an address of the data storage unit 1 (DP) 10, coefficient pointer (CP) 11 for determining the address of coefficient storage unit 3, external interface 4 for exchanging instructions with the outside, arithmetic unit 5 for performing arithmetic operations, and exchange of signals with the outside. It is composed of a peripheral section 6 for performing the control and a control section 2 for controlling the whole.

FIG. 5 is a block diagram of a digital filter configured by using the integrated circuit in FIG.

As shown in FIG. 5, in such an IIR digital filter, the signals input from the input terminal IN are added by the adder 13 via the delay circuits Z ₀ , Z ₁ and the coefficient circuits c, a ₀ , a ₁ to output terminals. OUT
Meanwhile, the output is fed back to the adder 13 via the delay circuits Z ₂ and Z ₃ and the coefficient circuits b ₀ and b ₁ . That is, a ₀ , a ₁ , b ₀ , b ₁ and c respectively represent the coefficients required for processing and are stored in the coefficient storage unit 3. Further, Z _{0 to} Z ₃ represent delayed data and are stored in the data storage unit 1 each time they are calculated.

FIG. 6 is a sequence diagram for explaining the flow of calculation between the data storage section and the calculation section in FIG.

As shown in FIG. 6, here, Z _{0 to} Z ₃ respectively correspond to addresses _{0 to 3} of the data storage unit 1. Further, ACC in the calculation unit 5 represents an accumulator, reads out data and coefficients from the data storage unit 1 and the coefficient storage unit 3, and stores the formula (IN × c + a ₀ × Z _{0) in the} ammulator ACC.
+ A ₁ × Z ₁ + b ₀ × Z ₂ + b ₁ × Z ₃ )
The operation of the IIR digital filter shown in the figure is performed.

[Problems to be Solved by the Invention]

In the above-described conventional signal processing integrated circuit, when attention is paid to the data storage unit, the data is read out in the order of Z ₁ and Z ₀ and is operated, and the Z ₀ data is transferred to the address 1 for the next operation. It must be written to (Z ₁ of the entered have the address). Further, the data Z ₃ and Z ₂ are also read out in order and the operation is performed, and the Z ₂ data is sent to the address 3
Must be written to (the address where Z ₃ was).

In this way, Z ₀ , Z ₂ data must be rewritten to the next advanced address for the next calculation each time one calculation is completed, so that the number of calculation steps increases and at the same time, There is a drawback that the calculation time becomes long.

It is an object of the present invention to provide a signal processing integrated circuit that reduces the number of calculation steps and the calculation time.

[Means for Solving the Problems]

The signal processing integrated circuit of the present invention is, in an IIR digital filter, an arithmetic unit that performs arithmetic operations, a coefficient storage unit that stores coefficients necessary for processing, a coefficient pointer that determines the address thereof, and a data storage unit that stores data. A data pointer for determining its address, a peripheral section for exchanging data with peripheral devices, an external interface section for exchanging instructions with the outside, a control section for overall control, and a signal from the control section. And a inverting circuit connected between the data pointer and the data storage unit and inverting a value such as LSB of the data pointer based on the output of the binary counting means. , The control unit via the binary count means, the data pointer, and the inversion circuit Configured to determine an address to the data storage unit by al signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a signal processing integrated circuit diagram showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment is the same as the above-mentioned conventional example (fourth embodiment).
The difference from FIG. 2 is that the binary counter 7 operated by the signal from the control unit 2, the AND gate 8 that takes the logical product of the output of the binary counter 7 and the signal from the control unit 2, and the AND gate 8 The inversion circuit 9 inverts the value of the data pointer (DP) 10 according to the output signal. The gate 8 and the inverting circuit 9 change the access method to the address of the data storage unit 1 every time the calculation is performed. As a result, the rewriting work of data, which is a drawback of the conventional example, becomes unnecessary and the number of calculation steps can be reduced.

Next, in order to make the above contents easy to understand, when the inverting circuit 9 is a circuit which inverts only the LSB of the data pointer 10,
Calculations similar to those in FIG. 6 will be described with reference to FIG.

FIG. 2 is a sequence diagram for explaining the flow of calculation between the data storage unit and the calculation unit in FIG.

As shown in FIG. 2, the data storage unit 1 in this embodiment.
The calculation between and the calculation unit 5 was required in FIG.
The step of rewriting Z ₀ and D ₂ data to addresses 1 and 3 respectively is omitted. That is, since the data Z ₀ is contained in the address 0 and the data Z ₁ is contained in the address 1 in the _first operation, the address 0 is contained in the second operation.
If access to Z ₁ is in the Z ₀ to which and the address 1 contains, Z ₀ data need not rewritten. In short, the binary counter 7 controlled by the control unit 2 is provided, and the value of the binary counter 7 is changed every time the operation is completed to change the access to the data storage unit 1. Therefore, the value shown as the address in the data storage unit 1 in FIG. 2 with parentheses indicates the access method in the second operation, that is, the next operation when there is no parenthesis. is there.

Here, the AND gate 8 connected to the binary counter 7 is a logic circuit that can be controlled by the control unit 2 whether to invert or not. That is, when the data storage unit 1 contains not only the IIR filter but also various data, the above-mentioned access is not necessary except for the IIR filter operation, and thus the gate 8 is required. Has become.

In short, in the present embodiment, by changing the addressing method of the data storage unit 1 to the arithmetic processing unit, the data storage unit 1
It is possible to reduce the number of times of writing to.

FIG. 3 is a signal processing integrated circuit diagram showing a second embodiment of the present invention.

As shown in FIG. 3, this embodiment is different from the above-mentioned first embodiment in that the AND gate 8 is omitted and the binary counter 8 is replaced with a binary F / F 12. As described above, the AND gate 8 is the data storage unit 1.
This is a gate for controlling the irregular access of, and is unnecessary if all the operations are only IIR digital filters.

〔The invention's effect〕

As described above, the signal processing integrated circuit of the present invention is
By providing the binary counting means, the data pointer and the inverting circuit and changing the address control to the data storage section by the signal from the control section, it is possible to reduce the number of operation steps and shorten the time required for the operation. There is an effect.

[Brief description of drawings]

FIG. 1 is an integrated circuit diagram for signal processing showing a first embodiment of the present invention, FIG. 2 is a sequence diagram for explaining a flow of calculation between a data storage unit and a calculation unit in FIG. 1, and FIG. FIG. 4 is a signal processing integrated circuit diagram showing a second embodiment of the present invention, FIG. 4 is a conventional signal processing integrated circuit diagram, and FIG. 5 is a configuration using the integrated circuit shown in FIG. FIG. 6 is a configuration diagram of the digital filter, and FIG. 6 is a sequence diagram for explaining the flow of calculation between the data storage unit and the calculation unit in FIG. 1 ... Data storage unit, 2 ... Control unit, 3 ... Coefficient storage unit, 4 ... External interface, 5 ... Calculation unit, 6 ...
... Peripheral part, 7 ... Binary counter, 8 ... AND circuit, 9 ... Inversion circuit, 10 ... Data pointer (DP),
11 …… Coefficient pointer (CP), 12 …… Binary F / F.

Claims (1)

[Claims] 1. An IIR digital filter comprising: an arithmetic unit for performing arithmetic operations; a coefficient storage unit for storing coefficients necessary for processing; a coefficient pointer for determining its address; a data storage unit for storing data; and its address. A data pointer to be decided, a peripheral part for exchanging data with the peripheral device, an external interface part for exchanging instructions with the outside, a control part for controlling the whole, and a binary count by a signal from the control part. Binary counting means, and an inverting circuit connected between the data pointer and the data storage section and inverting a value such as LSB of the data pointer based on the output of the binary counting means. And a signal from the control unit via the data pointer and the inversion circuit. Signal processing integrated circuit, characterized in that to determine the address of the data storage unit.