JPH07114287B2 - Semiconductor resistance element - Google Patents

Semiconductor resistance element

Info

Publication number
JPH07114287B2
JPH07114287B2 JP63089209A JP8920988A JPH07114287B2 JP H07114287 B2 JPH07114287 B2 JP H07114287B2 JP 63089209 A JP63089209 A JP 63089209A JP 8920988 A JP8920988 A JP 8920988A JP H07114287 B2 JPH07114287 B2 JP H07114287B2
Authority
JP
Japan
Prior art keywords
diffusion layer
resistance element
silicon substrate
semiconductor resistance
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63089209A
Other languages
Japanese (ja)
Other versions
JPH01261878A (en
Inventor
志郎 唐澤
誠志郎 大屋
幸男 栗原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kanagawa Prefecture
Original Assignee
Kanagawa Prefecture
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Filing date
Publication date
Application filed by Kanagawa Prefecture filed Critical Kanagawa Prefecture
Priority to JP63089209A priority Critical patent/JPH07114287B2/en
Publication of JPH01261878A publication Critical patent/JPH01261878A/en
Publication of JPH07114287B2 publication Critical patent/JPH07114287B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体歪ゲージ、圧力センサ、加速度センサ
等に用いられる半導体抵抗素子に関する。
Description: TECHNICAL FIELD The present invention relates to a semiconductor resistance element used for a semiconductor strain gauge, a pressure sensor, an acceleration sensor, and the like.

(従来の技術) 従来の半導体抵抗素子は、シリコン基板に熱拡散法によ
りp形またはn形拡散層を形成して成るものであった。
(Prior Art) A conventional semiconductor resistance element is formed by forming a p-type or n-type diffusion layer on a silicon substrate by a thermal diffusion method.

(発明が解決しようとする課題) 熱拡散法が用いられる上記従来の半導体抵抗素子におい
ては、不純物分布が補誤差関数で代表される関数で表わ
され、拡散層のピエゾ抵抗係数が不純物濃度分布、換言
すれば導電率分布に依存して変化する。このため拡散層
のピエゾ抵抗係数並びにゲージ率の実測値は拡散層の導
電率分布σ(X)について行なった平均値π並びにで
与えられ、次式のように表現できる。
(Problems to be Solved by the Invention) In the above-described conventional semiconductor resistance element using the thermal diffusion method, the impurity distribution is represented by a function represented by a complementary error function, and the piezoresistance coefficient of the diffusion layer is the impurity concentration distribution. In other words, it changes depending on the conductivity distribution. Therefore, the measured values of the piezoresistive coefficient and the gauge factor of the diffusion layer are given by the average value π of the conductivity distribution σ (X) of the diffusion layer and can be expressed by the following equation.

=1+γ+πE≒E …(2) ここでXは表面から拡散層中への距離Xoは拡散層の深
さ、π(X)は拡散層中のピエゾ抵抗係数、sは応力、
γはポアソン比、Eはヤング率である。
= 1 + γ + πE≈E (2) where X is the distance from the surface to the diffusion layer, X o is the depth of the diffusion layer, π (X) is the piezoresistance coefficient in the diffusion layer, and s is the stress.
γ is the Poisson's ratio and E is the Young's modulus.

(1)式はπ(X){1−π(X)s}により非線形性
となる。したがって、熱拡散性で拡散層を形成した半導
体抵抗素子のゲージ率はピエゾ抵抗係数の増加とともに
減少し、また応力の増加とともに減少する不都合があっ
た。さらに、ピエゾ抵抗係数は温度変化に対して非線形
性を有し、高いゲージ率での使用が制約される不都合が
あった。
Equation (1) becomes non-linear due to π (X) {1-π (X) s}. Therefore, there is a disadvantage that the gauge factor of the semiconductor resistance element in which the diffusion layer is formed by thermal diffusivity decreases with the increase of the piezoresistance coefficient and also decreases with the increase of the stress. Further, the piezoresistive coefficient has a non-linearity with respect to temperature change, and there is a disadvantage that use at a high gauge factor is restricted.

(課題を解決するための手段) 本発明はエキシマレーザドーピングの実験によって創作
されたものであって、請求項1記載の発明は、半導体抵
抗素子において、濃度勾配が急峻で深さが1000Å未満の
浅い拡散層をシリコン基板に設け、該拡散層でpn接合を
形成し、前記シリコン基板に加わる外力の変化を前記拡
散層の抵抗値の変化として検知することを特徴とし、請
求項2記載の発明は、請求項1記載の半導体抵抗素子に
おいて、前記拡散層の両端にオーミックコンタクト拡散
層を設け、前記シリコン基板表面に電流リーク防止用の
絶縁膜を成膜し、該絶縁膜を窓開けして前記オーミック
コンタクト拡散層上に電極を形成したことを特徴とし、
請求項3記載の発明は、請求項1または請求項2のいず
れか1項記載の半導体抵抗素子であって、前記拡散層を
同一のシリコン基板の片面又は両面に複数設け、ブリッ
ジ回路の全部又は一部を形成したことを特徴とする。
(Means for Solving the Problem) The present invention was created by an experiment of excimer laser doping, and the invention according to claim 1 is a semiconductor resistance element, in which the concentration gradient is steep and the depth is less than 1000Å. 3. The invention according to claim 2, wherein a shallow diffusion layer is provided on a silicon substrate, a pn junction is formed by the diffusion layer, and a change in external force applied to the silicon substrate is detected as a change in resistance value of the diffusion layer. Is a semiconductor resistance element according to claim 1, wherein ohmic contact diffusion layers are provided at both ends of the diffusion layer, an insulating film for preventing current leakage is formed on the surface of the silicon substrate, and the insulating film is opened. An electrode is formed on the ohmic contact diffusion layer,
A third aspect of the present invention is the semiconductor resistance element according to any one of the first and second aspects, wherein a plurality of the diffusion layers are provided on one side or both sides of the same silicon substrate, and all or a bridge circuit is provided. It is characterized in that a part is formed.

(作用) シリコン基板に不純物を拡散し、拡散層でpn接合を形成
し、外力が加わった場合に前記拡散層の抵抗値の変化を
検出すれば、前記シリコン基板に加わる外力の変化を求
めることができる。
(Operation) Obtaining a change in the external force applied to the silicon substrate by diffusing impurities in the silicon substrate, forming a pn junction in the diffusion layer, and detecting a change in the resistance value of the diffusion layer when an external force is applied. You can

その拡散層を、パルス波頭の立ち上がりが急峻なエキマ
シレーザドーピング法により形成すれば、第1図の実線
aのように、同図実線bの熱拡散法に比べて濃度勾配を
急峻とし、且つ深さが1000Å未満と浅い、いわゆるボッ
クスライクの不純物プロファイルに形成できるので、拡
散層が深さ方向の応力変化の影響を受けずに済むように
なり、ピエゾ抵抗係数の非線形性を小さくでき、200を
超える高いゲージ率での使用が可能となる。
If the diffusion layer is formed by the excimer laser doping method in which the rise of the pulse wave front is steep, the concentration gradient becomes steeper as compared with the thermal diffusion method of the solid line b in FIG. 1 as shown by the solid line a in FIG. Since the depth can be formed as shallow as less than 1000Å, that is, the so-called box-like impurity profile, the diffusion layer is not affected by the stress change in the depth direction, and the nonlinearity of the piezoresistive coefficient can be reduced. It is possible to use it with a high gauge rate exceeding.

また、前記拡散層の両端にオーミックコンタクト拡散層
を設け、前記シリコン基板表面に絶縁膜を成膜し、該絶
縁膜を窓開けして前記拡散層上に電極を形成すれば、電
流リークがなくなり、素子の性能を向上する。
Further, by providing ohmic contact diffusion layers at both ends of the diffusion layer, forming an insulating film on the surface of the silicon substrate, opening a window of the insulating film, and forming an electrode on the diffusion layer, current leakage is eliminated. , Improve the performance of the device.

更に、前記拡散層を同一のシリコン基板の片面又は両面
に複数設け、ブリッジ回路の全部又は一部を形成すれば
温度補正が行えるので、ピエゾ抵抗係数の温度変化に対
する変化を線形にでき、これにより高いゲージ率で使用
することが可能となる。
Furthermore, since a plurality of diffusion layers are provided on one surface or both surfaces of the same silicon substrate to form the bridge circuit in whole or in part, temperature correction can be performed, so that the change in the piezoresistive coefficient with respect to temperature change can be made linear. It can be used with a high gauge rate.

(実施例) 次に本発明の実施例を図面に基づいて説明する。(Example) Next, the Example of this invention is described based on drawing.

第2図は本発明の半導体抵抗素子の第1実施例を示すも
ので、その製造工程を以下に説明する。
FIG. 2 shows a first embodiment of the semiconductor resistance element of the present invention, and its manufacturing process will be described below.

先ずn形シリコン基板1(1a)をジボランガス(B2H6
の雰囲気中に置き、3ナノ秒と急峻な波頭を持つパルス
からなるXeClエキシマレーザ(波長308nm)を照射して
該基板1を瞬間的に溶融し、これに吸着したジボラガス
を分解して該基板1に硼素(B)をドーピングする。こ
のときレーザのパルス数、エネルギー密度を制御するこ
とにより不純物濃度プロファイルがボックスライクとな
る数百Å程度の浅いp形拡散層2(2b)が形成される。
First, the n-type silicon substrate 1 (1a) is set to diborane gas (B 2 H 6 ).
The substrate 1 is irradiated with an XeCl excimer laser (wavelength 308 nm) consisting of a pulse having a steep wave front of 3 nanoseconds to melt the substrate 1 instantaneously and decompose the dibola gas adsorbed on the substrate 1 to decompose the substrate. 1 is doped with boron (B). At this time, a shallow p-type diffusion layer 2 (2b) of about several hundred Å is formed in which the impurity concentration profile is box-like by controlling the number of laser pulses and the energy density.

次いで該基板1の該拡散層2の両端に同じくXeClエキシ
マレーザドーピングによりP+拡散層3(3b)を形成し、
次いでXeClエキシマレーザドーピングした該基板1の表
面全体に電流リークを防止する絶縁膜4を形成する。
Then, a P + diffusion layer 3 (3b) is formed on both ends of the diffusion layer 2 of the substrate 1 by the same XeCl excimer laser doping,
Next, an insulating film 4 for preventing current leakage is formed on the entire surface of the substrate 1 which is XeCl excimer laser doped.

最後に該絶縁膜4の該オーミックコンタクト拡散層3の
上方に位置する部分に孔5を明け、金から成る電極6を
真空蒸着により形成する。こうしてオーミック電極6を
備えた半導体抵抗素子7が得られる。
Finally, a hole 5 is formed in a portion of the insulating film 4 located above the ohmic contact diffusion layer 3 and an electrode 6 made of gold is formed by vacuum evaporation. In this way, the semiconductor resistance element 7 including the ohmic electrode 6 is obtained.

かくするときは、該拡散層2に外力(応力)が働くと該
拡散層2の比抵抗ρまたは抵抗値Rが変化して、次式に
より外力の変化が応力sまたは歪εの形で検知できる。
In this case, when an external force (stress) acts on the diffusion layer 2, the specific resistance ρ or the resistance value R of the diffusion layer 2 changes, and the change in the external force is detected in the form of stress s or strain ε according to the following equation. it can.

上記した製造工程により得られた半導体抵抗素子は、歪
−抵抗特性が少なくとも800kg重/cm2の応力までフルス
ケールの0.25%以下の直線性がある。
The semiconductor resistance element obtained by the above-described manufacturing process has a strain-resistance characteristic of linearity of 0.25% or less of full scale up to a stress of at least 800 kgf / cm 2 .

第3図は、エキシマレーザのエネルギー密度を0.5J/cm2
とし、ジボランガスの濃度を変えて、換言すれば不純物
濃度を制御して、拡散層2の比抵抗の値を変え、ゲージ
率を測定した結果の一例である。これによればゲージ率
は比抵抗の増加、換言すれば不純物濃度の減少とともに
増加して実線aのようになり、点線bの熱拡散法による
場合の値よりも高い値が得られているのがわかる。
Figure 3 shows the energy density of the excimer laser at 0.5 J / cm 2
Is an example of the result of measuring the gauge factor by changing the concentration of diborane gas, in other words, controlling the impurity concentration and changing the value of the specific resistance of the diffusion layer 2. According to this, the gauge factor increases as the resistivity increases, in other words, as the impurity concentration decreases, and becomes a solid line a, which is higher than the value of the dotted line b obtained by the thermal diffusion method. I understand.

第4図は、本発明の半導体抵抗素子の第2実施例を示す
もので、この場合には、p形シリコン基板1(1b)の片
面にn形拡散層2(2a)を形成した単一の半導体抵抗素
子7であって、p形シリコン基板1bの中にエキシマレー
ザドーピングにより形成した不純物濃度プロファイルが
ボックスストライクの浅いn形拡散層2aと、1対の電極
6、6とオーミックコンタクトするn+オーミックコンタ
クト拡散層3a、3bと、電流リークを防止する絶縁膜4と
が設けられる。
FIG. 4 shows a second embodiment of the semiconductor resistance element of the present invention. In this case, a single p-type silicon substrate 1 (1b) is provided with an n-type diffusion layer 2 (2a) on one side. In the semiconductor resistance element 7 of FIG. 1, the n-type diffusion layer 2a having a shallow impurity concentration profile formed by excimer laser doping in the p-type silicon substrate 1b is in ohmic contact with the pair of electrodes 6 and 6. + Ohmic contact diffusion layers 3a and 3b and an insulating film 4 for preventing current leakage are provided.

この場合にも前記第1実施例のものと同様、熱拡散法よ
りも高いゲージ率が得られる。
In this case as well, as in the case of the first embodiment, a higher gauge factor than the thermal diffusion method can be obtained.

第5図は本発明の半導体抵抗素子の第3実施例を示すも
ので、このものは、同一n形シリコン基板1aの片面にp
形拡散層2bからなる抵抗体を2つ設けて該抵抗体による
ブリッジ回路の半分を構成するようにしたp形半導体抵
抗素子7bであって、このp形半導体抵抗素子7bを2組用
いることによって該抵抗体によるブリッジ回路が構成さ
れる。
FIG. 5 shows a third embodiment of the semiconductor resistance element of the present invention, in which p is formed on one surface of the same n-type silicon substrate 1a.
A p-type semiconductor resistance element 7b in which two resistance bodies each including a diffusion layer 2b are provided to form a half of a bridge circuit of the resistance bodies. By using two sets of the p-type semiconductor resistance elements 7b, A bridge circuit is formed by the resistors.

尚、p形シリコン基板1bを用いればn形半導体抵抗素子
7aを作ることができる。
If a p-type silicon substrate 1b is used, an n-type semiconductor resistance element
You can make 7a.

第6図は本発明の半導体抵抗素子の第4実施例を示すも
ので、このものは、同一n形シリコン基板1aの片面にp
形拡散層2bからなる抵抗体を4つ設けて該抵抗体による
ブリッジ回路の全部を構成するようにしたp形半導体抵
抗素子7である。
FIG. 6 shows a fourth embodiment of the semiconductor resistance element of the present invention, in which p is formed on one surface of the same n-type silicon substrate 1a.
This is a p-type semiconductor resistance element 7 in which four resistors made up of the diffusion layers 2b are provided to form the entire bridge circuit of the resistors.

尚、p形シリコン基板1bを用いればn形半導体抵抗素子
7aを作ることができる。
If a p-type silicon substrate 1b is used, an n-type semiconductor resistance element
You can make 7a.

第7図は本発明の半導体抵抗素子の第5実施例を示すも
ので、このものは同一のn形またはp形のシリコン基板
1の両面に夫々p形またはn形の拡散層2から成る抵抗
体を2つずつ設けて該抵抗体によるブリッジ回路を構成
するようにしたp形またはn形の半導体抵抗素子7であ
る。
FIG. 7 shows a fifth embodiment of the semiconductor resistance element of the present invention, which is a resistor composed of a p-type or n-type diffusion layer 2 on both sides of the same n-type or p-type silicon substrate 1, respectively. It is a p-type or n-type semiconductor resistance element 7 in which two bodies are provided to form a bridge circuit by the resistors.

上記第3実施例乃至第5実施例のものでも、前記第1実
施例及び第2実施例のものと同様に、電極6とオーミッ
クコンタクトするオーミックコンタクト拡散層3と、電
流リークを防止する絶縁膜4とが設けられ、熱拡散法よ
り高いゲージ率が得られるのは勿論であるが、第3実施
例乃至第5実施例のものによれば、抵抗体によるブリッ
ジ回路が構成されるので、抵抗体の温度補正ができ、ピ
エゾ抵抗係数を温度変化に対して線形性にすることがで
き、前記第1実施例及び第2実施例のものよりも更に直
線性の良い歪−抵抗特性が得られる。
Also in the third to fifth embodiments, as in the first and second embodiments, the ohmic contact diffusion layer 3 which makes ohmic contact with the electrode 6 and the insulating film which prevents current leakage. 4 is provided to obtain a higher gauge factor than the thermal diffusion method. However, according to the third to fifth embodiments, since the bridge circuit is formed by the resistors, The temperature of the body can be corrected, the piezoresistive coefficient can be made linear with respect to the temperature change, and the strain-resistance characteristic having better linearity than that of the first and second embodiments can be obtained. .

尚、第8図及び第9図の実施例又は第10図乃至第12図の
実施例のように絶縁溝8を設けてメサ構造とすることに
より、電流リークをより一層確実に防止することができ
る。
By providing the insulating groove 8 to form the mesa structure as in the embodiment of FIGS. 8 and 9 or the embodiment of FIGS. 10 to 12, the current leakage can be prevented more reliably. it can.

(発明の効果) このように、本発明の半導体抵抗素子によるときは、熱
拡散法により抵抗体となる拡散層を形成する前記従来の
ものよりも高いゲージ率を有し、直線性の良い歪−抵抗
特性を有する半導体抵抗素子が得られ、この半導体抵抗
素子を用いれば外力の変化を高い感度で直線性良く抵抗
の変化として検出できる効果を有する。この半導体抵抗
素子の応用として高感度の半導体歪ゲージ、圧力セン
サ、加速度センサの製造等が期待でき、工業的用途とし
ても本発明の効果は大きい。
(Effects of the Invention) As described above, the semiconductor resistance element of the present invention has a higher gauge factor than that of the conventional one in which a diffusion layer serving as a resistor is formed by a thermal diffusion method, and strain with good linearity is obtained. A semiconductor resistance element having resistance characteristics can be obtained, and if this semiconductor resistance element is used, the change in external force can be detected as a change in resistance with high sensitivity and linearity. The application of this semiconductor resistance element can be expected to produce highly sensitive semiconductor strain gauges, pressure sensors, acceleration sensors, and the like, and the effect of the present invention is great even for industrial applications.

さらに請求項2の半導体抵抗素子によるときは電流リー
クが防止され、素子の性能が向上される効果を有する。
Further, when the semiconductor resistance element according to claim 2 is used, current leakage is prevented, and the element performance is improved.

さらに請求項3の半導体抵抗素子によるときは、拡散層
からなる抵抗体を温度補正することによりピエゾ抵抗係
数を温度変化に対して線形性にすることができ、高いゲ
ージ率でのより一層の安定使用が期待できる。
Further, according to the semiconductor resistance element of claim 3, the piezo resistance coefficient can be made linear with respect to the temperature change by correcting the temperature of the resistor formed of the diffusion layer, and the stability is further improved at a high gauge factor. Expected to be used.

【図面の簡単な説明】[Brief description of drawings]

第1図はエキシマレーザドーピングと熱拡散の不純物濃
度分布の違いを示す説明図、第2図は本発明の半導体抵
抗素子の第1実施例を示す裁断側面図、第3図は〈11
1〉方向のシリコン基板中にエキシマレーザドーピング
によりボロンを拡散したときの比抵抗−ゲージ特性、第
4図は本発明の半導体抵抗素子の第2実施例を示す裁断
側面図、第5図は本発明の半導体抵抗素子の絶縁膜を除
いた状態の第3実施例を示す平面図、第6図は本発明の
半導体抵抗素子の絶縁膜を除いた状態の第4実施例を示
す平面図、第7図は本発明の半導体抵抗素子の第5実施
例を示す裁断側面図、第8図は本発明の半導体抵抗素子
の第6実施例を示す裁断側面図、第9図はその平面図、
第10図は本発明の半導体抵抗素子の第7実施例を示す裁
断側面図、第11図はその平面図、第12図は第11図のXII
−XII線断面図である。 1…シリコン基板 1a…n形シリコン基板 1b…p形シリコン基板 2…拡散層 2a…n形拡散層 2b…p形拡散層 3…オーミックコンタクト拡散層 3a…n+オーミックコンタクト拡散層 3b…p+オーミックコンタクト拡散層 4…絶縁膜 5…孔 6…電極 7…半導体抵抗素子 7a…n形半導体抵抗素子 7b…p形半導体抵抗素子 8…絶縁溝
FIG. 1 is an explanatory view showing a difference in impurity concentration distribution between excimer laser doping and thermal diffusion, FIG. 2 is a cut side view showing a first embodiment of a semiconductor resistance element of the present invention, and FIG.
Resistivity-gauge characteristics when boron is diffused into a silicon substrate in the 1> direction by excimer laser doping, FIG. 4 is a cut side view showing a second embodiment of the semiconductor resistance element of the present invention, and FIG. FIG. 6 is a plan view showing a third embodiment of the semiconductor resistance element of the present invention excluding the insulating film, and FIG. 6 is a plan view showing the fourth embodiment of the semiconductor resistance element of the present invention excluding the insulation film. 7 is a cut side view showing a fifth embodiment of the semiconductor resistance element of the present invention, FIG. 8 is a cut side view showing a sixth embodiment of the semiconductor resistance element of the present invention, and FIG. 9 is a plan view thereof.
FIG. 10 is a cut side view showing a seventh embodiment of the semiconductor resistance element of the present invention, FIG. 11 is its plan view, and FIG. 12 is XII of FIG.
It is a -XII sectional view. 1 ... Silicon substrate 1a ... n type silicon substrate 1b ... p type silicon substrate 2 ... diffusion layer 2a ... n type diffusion layer 2b ... p type diffusion layer 3 ... ohmic contact diffusion layer 3a ... n + ohmic contact diffusion layer 3b ... p + Ohmic contact diffusion layer 4 ... Insulating film 5 ... Hole 6 ... Electrode 7 ... Semiconductor resistance element 7a ... N-type semiconductor resistance element 7b ... P-type semiconductor resistance element 8 ... Insulation groove

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】濃度勾配が急峻で深さが1000Å未満の浅い
拡散層をシリコン基板に設け、該拡散層でpn接合を形成
し、前記シリコン基板に加わる外力の変化を前記拡散層
の抵抗値の変化として検知する半導体抵抗素子。
1. A shallow diffusion layer having a steep concentration gradient and a depth of less than 1000Å is provided on a silicon substrate, a pn junction is formed by the diffusion layer, and a change in external force applied to the silicon substrate is measured by a resistance value of the diffusion layer. Semiconductor resistance element that detects changes in
【請求項2】前記拡散層の両端にオーミックコンタクト
拡散層を設け、前記シリコン基板表面に電流リーク防止
用の絶縁膜を成膜し、該絶縁膜を窓開けして前記オーミ
ックコンタクト拡散層上に電極を形成したことを特徴と
する請求項1記載の半導体抵抗素子。
2. An ohmic contact diffusion layer is provided on both ends of the diffusion layer, an insulating film for preventing current leakage is formed on the surface of the silicon substrate, and the insulating film is opened to form a window on the ohmic contact diffusion layer. The semiconductor resistance element according to claim 1, wherein an electrode is formed.
【請求項3】前記拡散層を同一のシリコン基板の片面又
は両面に複数設け、ブリッジ回路の全部又は一部を形成
したことを特徴とする請求項1または請求項2のいずれ
か1項記載の半導体抵抗素子。
3. The silicon substrate according to claim 1, wherein a plurality of the diffusion layers are provided on one surface or both surfaces of the same silicon substrate to form all or part of a bridge circuit. Semiconductor resistance element.
JP63089209A 1988-04-13 1988-04-13 Semiconductor resistance element Expired - Lifetime JPH07114287B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63089209A JPH07114287B2 (en) 1988-04-13 1988-04-13 Semiconductor resistance element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63089209A JPH07114287B2 (en) 1988-04-13 1988-04-13 Semiconductor resistance element

Publications (2)

Publication Number Publication Date
JPH01261878A JPH01261878A (en) 1989-10-18
JPH07114287B2 true JPH07114287B2 (en) 1995-12-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP63089209A Expired - Lifetime JPH07114287B2 (en) 1988-04-13 1988-04-13 Semiconductor resistance element

Country Status (1)

Country Link
JP (1) JPH07114287B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5907768A (en) * 1996-08-16 1999-05-25 Kobe Steel Usa Inc. Methods for fabricating microelectronic structures including semiconductor islands
US5872415A (en) * 1996-08-16 1999-02-16 Kobe Steel Usa Inc. Microelectronic structures including semiconductor islands
US9659775B2 (en) 2015-02-25 2017-05-23 Fuji Electric Co., Ltd. Method for doping impurities, method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH01261878A (en) 1989-10-18

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