JPH07114286B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved structure of a semiconductor device, particularly a field effect transistor.

[Conventional technology]

As a semiconductor device of this type according to a conventional example, here, a dual gate field effect transistor (hereinafter, referred to as FET) is used.
The cross-sectional structure of is shown in FIG.

That is, in the conventional example structure shown in FIG. 2, reference numeral 1 is a semi-insulating semiconductor substrate, and 2 and 3 are a buffer layer and a semiconductor active layer sequentially formed on the semiconductor substrate 1, 4, and Reference numeral 5 designates source and drain electrodes which are in ohmic contact with corresponding portions, and reference numerals 6 and 7 designate input side (source side) first 1 and output side (drain side) second gate electrodes, respectively.

Here, in general, the performance of a single-gate FET, especially the high-frequency characteristics, greatly depends on its gate length Lg. By shortening this gate length Lg as much as possible, It is known that performance enhancement can be achieved. Therefore, in order to improve the performance of the dual gate FET, therefore, the gate lengths Lg ₁ and Lg ₂ of both the input side and output side two gates 6.7 should be set to I try to shorten it.

In FIG. 2, Lsg ₁ is the distance between the source and the first gate, Lg ₁ g ₂ is the distance between the first gate and the second gate, and Lg ₂ d is the distance between the second gate and the drain. .

[Problems to be solved by the invention]

The dual gate FET in the conventional example is configured as described above, and for the purpose of high performance, two gates 6 and 7 on the input side and the output side, respectively, both have their respective gate lengths L.
Since g ₁ and Lg ₂ are shortened, if each of these gate lengths Lg ₁ and Lg ₂ is shortened to the submicron order, there is a problem that the manufacturing yield is lower than that of a single gate FET. It was

Therefore, in view of such problems in the conventional device, the object of the present invention is to achieve high performance without significantly lowering the manufacturing yield. Is to provide.

[Means for solving problems]

In order to achieve the above object, a dual gate FET according to the present invention includes a source electrode and a first gate electrode on an input side (source side), a first gate electrode on an input side and an output side (drain side). The input between the two gate electrodes and between the output side second gate electrode and the drain electrode has a length substantially equal to the length of the output side second gate electrode, and is formed between the source electrode and the drain electrode. The first on the side (source side)
And the second gate electrode on the output side (drain side),
Only the gate length Lg ₁ of the first gate electrode on the input side is shortened, and the gate length Lg ₂ of the second gate electrode on the output side is a length that does not lower the manufacturing yield (for example, in the case of a shape, Lg 1 ₂ = about 1.0 μm).

[Action]

That is, in the dual gate FET according to the present invention, by shortening only the gate length Lg ₁ of the first gate electrode on the input side (source side), the input side (source side) and the output side (drain) are reduced. Side) Compared to the case where the gate lengths Lg ₁ and Lg ₂ of both of the two gate electrodes are both shortened, the manufacturing yield is less decreased, and the improvement in performance such as high frequency characteristics is also small. The same effect can be obtained.

〔Example〕

An embodiment of the semiconductor device according to the present invention, here a dual gate FET, will be described in detail with reference to FIG.

FIG. 1 shows a dual gate FET to which the structure of this embodiment is applied.
FIG. 3 is a main-portion cross-sectional view schematically showing the schematic configuration of FIG.

That is, also in the embodiment structure shown in FIG. 1, reference numeral 11 is a semi-insulating semiconductor substrate, and 12 and 13 are a buffer layer and a semiconductor active layer sequentially formed on the semiconductor substrate 11, 14, and 15 are source and drain electrodes that are in ohmic contact with their corresponding parts, 1
Reference numerals 6, 17 denote input side (source side) first 1 and output side (drain side) second gate electrodes, respectively.

In the structure of this embodiment, the first gate electrode 16 on the input side (source side) and the second gate electrode 17 on the output side (drain side) formed between the source electrode 14 and the drain electrode 15 are formed. The gate length Lg ₁ of the first gate electrode 16 on the input side is made shorter than the gate length Lg ₂ of the second gate electrode 17 on the output side.

Here, in this kind of dual gate FET, since the input signal is generally given to the first gate electrode 16 on the input side (source side), the gate length Lg _{1 of} this first gate electrode 16 is In order to improve the high-frequency characteristics (especially noise characteristics) of the second gate electrode 17 on the output side by shortening only the gate length Lg ₂ of the second gate electrode 17, the respective gate electrodes 16 and 17 of both of them are shortened. It is possible to expect an effect equivalent to that of the above, and at the same time, shortening only the gate length Lg ₁ of the one first gate electrode 16 in this way is
And the gate length Lg ₁ of each of the gate electrodes 16 and 17 of the second both
-Compared to the case where Lg ₂ is shortened, the ease of manufacture is naturally obvious, and naturally, the manufacturing yield can be improved.

Here, for the purpose of confirming the above effect, the distance Lsg ₁ between the source and the first gate and the distance Lg ₁ g between the first gate and the second gate
₂ and each parameter in the dual gate FET such as the distance Lg ₂ d between the second gate and drain is fixed,
Table 1 shows the results of comparison of the characteristics when the gate lengths Lg ₁ and Lg _{2 of} the second gate electrodes are changed and these dual gate FETs are manufactured on the same wafer.

Supra, as is clear from the results in Table 1, reduction of only the gate length Lg ₁ in the first gate electrode, in enhancing the NF, the gate length of the first, second gate electrodes Lg ₁ , Lg ₂ are both shortened, the manufacturing yield can be improved about twice, and the gate length Lg ₂ at the second gate electrode is relatively large. The impedance on the output side was large, and it was confirmed that the gain was improved.

〔The invention's effect〕

As described above in detail, according to the present invention, in the dual gate FET, between the source electrode and the first gate electrode on the input side (source side), between the input side first gate electrode and the output side (drain side). The length between the second gate electrodes and between the output-side second gate electrode and the drain electrode is approximately equal to the length of the output-side second gate electrode, and the first gate on the input side (source side) By shortening only the gate length Lg _{1 of the} electrodes, the gate lengths Lg ₁ and Lg ₂ of both the input side (source side) and output side (drain side) gate electrodes are reduced. Compared with the case of shortening, the high yield characteristics of the device configuration can be greatly improved without significantly lowering the manufacturing yield, and the manufacturing itself is relatively simple and easy to perform. is there.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a main part schematically showing a schematic structure of a dual gate FET to which the structure of one embodiment of the present invention is applied,
Further, FIG. 2 is a cross-sectional view of an essential part schematically showing the schematic configuration of a dual gate FET according to the conventional example. 11 …… Semi-insulating semiconductor substrate, 12 ……, buffer layer, 13
...... Semiconductor active layer, 14 ...... Source electrode, 15 …… Drain electrode, 16 …… Input side (source side) first gate electrode, 17
The second gate electrode on the output side (drain side).

Claims (1)

[Claims] 1. In each electrode structure of a dual gate field effect transistor, an input side (source side) first gate electrode and an output side (drain side) second gate electrode are interposed in a channel region between a source electrode and a drain electrode. The length between the source electrode and the input-side first gate electrode, between the input-side first gate electrode and the output-side second gate electrode, and between the output-side second gate electrode and the drain electrode is the output-side second gate electrode. And a gate length of the input-side first gate electrode shorter than a gate length of the output-side second gate electrode.