JPH07113847A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit in which a partial logic circuit can be tested with no influence from other neighboring partial logic circuit and all routes of each partial logic circuit, through which the data passes under normal mode, can be tested for failure. CONSTITUTION:The semiconductor integrated circuit comprises a first partial logic circuit 102, a selector 110 receiving the output from the first partial logic circuit 102, a second partial logic circuit 103 receiving the output from the selector 110, and a flip-flop 109 receiving the output from the selector 110. The flip-flop 109 is connected with a scan path and can control the output value while observing the input value through scanning operation. The selector 110 selects any one of the output from the first partial logic circuit 102 or the flip-flop 109 under external control and delivers the selected one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for efficiently performing circuit failure inspection by scan-in and scan-out.

[0002]

2. Description of the Related Art When conducting a failure inspection of a semiconductor integrated circuit,
If there is a partial circuit that is difficult to test in the circuit, it becomes difficult to test the entire circuit. The reason for this is that it is difficult to observe the data that has reached the partial circuit that is difficult to test from other circuit parts, and it is difficult to control the output data of the partial circuit. This is because the test will be difficult. In order to deal with this problem, by adding a circuit for testing between a partial logic circuit which is conventionally difficult to test and another circuit part, both the partial logic circuit which is difficult to test and the other circuit part are added. I was testing.

The prior art will be described below with reference to FIG.
FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to the prior art. 301 is a semiconductor integrated circuit, 302 and 303 are partial logic circuits, 304 is a data input terminal for inputting data to the partial logic circuit 302, 305 is a data output terminal for outputting the output data of the partial logic circuit 303 to the outside, and 306 is a scan IN terminal, 307 is scan out terminal, 308
Is a mode select terminal, 309 is a scan flip-flop, and 310 is an input value of the mode select terminal 308 is 0.
The selector 311 selects the output data from the partial logic circuit 302 when, and the output data of the scan flip-flop 309 when the input value of the mode select terminal 308 is 1, The signal lines that pass before reaching the selector 310 are shown. The scan flip-flop 309 has a clock input terminal (not shown) as well as a mode select terminal (not shown) that can be directly controlled from the outside, and switches a normal operation and a scan operation according to an input signal to the mode select terminal. During operation, the output from the partial logic circuit 302 is fetched in synchronization with the clock signal, during scan operation, test data is scanned in from the scan-in terminal 306 in synchronization with the clock signal, and test results are scanned out from the scan-out terminal 307. .

In the normal mode, the mode select terminal 30
By inputting 0 to 8, the selector 310 selects the output data of the partial logic circuit 302 and selects the partial logic circuit 30.
Give to 3. Therefore, the data input from the data input terminal 304 is given to the partial logic circuit 302, the output data of the partial logic circuit 302 is given to the partial logic circuit 303 via the signal line 311, the selector 310, and the output of the partial logic circuit 303. The data is output from the data output terminal 305 to the outside of the semiconductor integrated circuit 301.

Next, the operation when testing the semiconductor integrated circuit 301 will be described. When testing the partial logic circuit 302, test data is input from the data input terminal 304 and given to the partial logic circuit 302. The output result of the partial logic circuit 302 is the scan flip-flop 309.
And is observed at the scan-out terminal 307 by the scan-out operation.

When testing the partial logic circuit 303, the selector 310 causes the scan flip-flop 309 by inputting 1 to the mode select terminal 308.
Output data is selected and given to the partial logic circuit 303.
Test data is input from the scan-in terminal 306,
Scan flip-flop 3 by scan-in operation
09 is applied to the partial logic circuit 303. The output result of the partial logic circuit 303 is observed at the data output terminal 305.

With the above configuration, the partial logic circuit 302,
Since each 303 can be tested independently, even if one of the partial logic circuits is difficult to test, it does not affect the testability of the other partial logic circuit.

[0008]

However, according to the above conventional configuration, the signal line 311 from the partial logic circuit 302 through which data passes in the normal mode to the selector 310 is provided.
If there is a failure, there is a problem that the test for the failure of the signal line 311 cannot be performed because the test data does not pass through the signal line 311.

In view of the above problems, it is an object of the present invention to provide a semiconductor integrated circuit equipped with a test circuit that enables testing of all signal line faults through which data passes in the normal mode.

[0010]

In order to solve this problem, a semiconductor integrated circuit according to the present invention includes a first partial logic circuit, a selector having an output of the first partial logic circuit as an input, and the selector. A second partial logic circuit whose input is the output of the selector, and a flip-flop whose input is the output of the selector, the flip-flop being connected to the scan path, controlling the output value by the scan operation, and It is observable, and the selector selects and outputs one of the output of the first partial logic circuit and the output of the flip-flop under external control.

[0011]

With the above configuration, when the semiconductor integrated circuit is tested, the data output from the first partial logic circuit reaches the flip-flop through the selector and is supplied to the second partial logic circuit. By reaching the second partial logic circuit via the flip-flop and selector, it is possible to test all failures on the signal line between the two partial logic circuits used in the normal mode.

[0012]

【Example】

(Embodiment 1) FIG. 1 is a circuit diagram showing the configuration of Embodiment 1 of a semiconductor integrated circuit according to the present invention. 101 is a semiconductor integrated circuit, 102 and 103 are partial logic circuits, 104 is a data input terminal for inputting data to the partial logic circuit 102, 10
5 is a data output terminal for outputting the output data of the partial logic circuit 103 to the outside, 106 is a scan-in terminal, 107 is a scan-out terminal, 108 is a mode select terminal, 1
Reference numeral 09 is a scan flip-flop, and 110 is a partial logic circuit 10 when the input value of the mode select terminal 108 is 0.
The output data from 2 is selected, and the mode select terminal 10
When the input value of 8 is 1, the scan flip-flop 109
, A selector for selecting the output data, and a signal line 111. Further, the scan flip-flop 109 takes in the output from the selector 110 during normal operation. Further, the scan flip-flop 109 has a clock input terminal (not shown) similar to a mode select terminal (not shown) that can be directly controlled from the outside, and switches a normal operation and a scan operation according to an input signal to the mode select terminal. During operation, the output from the selector 110 is fetched in synchronization with the clock signal, and during scan operation, scan-in terminal 1
The test data is scanned in from 06 in synchronization with the clock signal, and the test result is scanned out from the scan out terminal 107.

The semiconductor integrated circuit according to the first embodiment will be described below with reference to FIG. In the normal mode, by inputting 0 to the mode select terminal 108, the selector 110 selects the output data of the partial logic circuit 102 and supplies it to the partial logic circuit 103. Therefore, the data input terminal 104
The data input from is supplied to the partial logic circuit 102, and the output data of the partial logic circuit 102 is signal line 111,
Partial logic circuit 10 via selector 110 and signal line 112
3 and the output data of the partial logic circuit 103 is output from the data output terminal 105 to the outside of the semiconductor integrated circuit 101.

Next, the operation when testing the semiconductor integrated circuit 101 will be described. When testing the partial logic circuit 102, by inputting 0 to the mode select terminal 108, the selector 110 selects the output data of the partial logic circuit 102. The test data is the data input terminal 10
It is input from 4 and given to the partial logic circuit 102. The output result of the partial logic circuit 102 reaches the scan flip-flop 109 via the signal line 111 and the selector 110, and the scan-out terminal 1 is operated by the scan-out operation.
It is observed at 07.

When the partial logic circuit 103 is tested, the selector 110 causes the scan flip-flop 109 by inputting 1 to the mode select terminal 108.
Output data is selected and given to the partial logic circuit 103.
The test data is input from the scan-in terminal 106,
Scan flip-flop 1 by scan-in operation
09, and is supplied to the partial logic circuit 103 via the selector 110 and the signal line 112. Partial logic circuit 10
The output result of No. 3 is observed at the data output terminal 105.

With the above configuration, the test for the failure of the signal lines 111, 112 through which the data passes in the normal mode can be performed at the time of the test, and the partial logic circuit 102,
Since each 103 can be tested independently, even if one of the partial logic circuits is difficult to test, it does not affect the testability of the other partial logic circuit.

(Embodiment 2) FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the semiconductor integrated circuit according to the present invention. 201
Is a semiconductor integrated circuit, 202 to 204 are partial logic circuits, and 203 is a RAM in this embodiment. Two
Reference numeral 05 is a data input terminal for inputting data to the partial logic circuit 202, 206 is a data output terminal for outputting output data of the partial logic circuit 204 to the outside, 207 is a scan-in terminal, 208 is a scan-out terminal, and 209 and 210 are modes. Select terminals 211, 212 are scan flip-flops, and 213 selects output data from the partial logic circuit 202 when the input value of the mode select terminal 209 is 0, and scan flip-flops when the input value of the mode select terminal 209 is 1. A selector for selecting the output data of the block 211, 214 selects the output data from the RAM 203 when the input value of the mode select terminal 210 is 0,
Selectors 215 to 218 which select the output data of the scan flip-flop 212 when the input value of the mode select terminal 210 is 1, and signal lines 215 to 218. The scan flip-flops 211 and 212 have a clock input terminal (not shown) as well as a mode select terminal (not shown) that can be directly controlled from the outside, and switch between normal operation and scan operation according to an input signal to the mode select terminal. During normal operation, the outputs from the selectors 213 and 214 are taken in in synchronization with the clock signal. During the scan operation, the test data is scanned in from the scan-in terminal 207 in synchronization with the clock signal, and the scan-out terminal 20.
Scan out test results from 8. The scan flip-flops 211 and 212 have scan-in terminals 20.
7, the scan flip-flops 211 and 212, and the scan-out terminal 208 are connected in this order to form a scan path.

The semiconductor integrated circuit of the second embodiment will be described below with reference to FIG. In the normal mode, by inputting 0 to the mode select terminals 209 and 210, the selectors 213 and 214 respectively cause the partial logic circuit 202 and the RAM.
The output data of 203 is selected and RAM 203,
It is given to the partial logic circuit 204. Therefore, the data input from the data input terminal 205 is stored in the partial logic circuit 202.
The output data of the partial logic circuit 202 is supplied to the RAM 2 via the signal line 215, the selector 213, and the signal line 216.
03, and the output data of the RAM 203 is the signal line 2
The data is supplied to the partial logic circuit 204 via the selector 17, the selector 214 and the signal line 218, and the output data of the partial logic circuit 204 is output from the data output terminal 206 to the outside of the semiconductor integrated circuit 201.

Next, the operation of testing the semiconductor integrated circuit 201 will be described. When testing the partial logic circuit 202, by inputting 0 to the mode select terminal 209, the selector 213 selects the output data of the partial logic circuit 202. Test data is data input terminal 20
It is inputted from 5 and given to the partial logic circuit 202. The output result of the partial logic circuit 202 reaches the scan flip-flop 211 via the signal line 215 and the selector 213, and is observed at the scan-out terminal 208 via the scan flip-flop 212 by the scan-out operation.

When the RAM 203 is tested, the selectors 213 and 214 select the output data of the scan flip-flop 211 and the RAM 203 by inputting 1 and 0 to the mode select terminals 209 and 210, respectively. Test data is scan-in terminal 2
07, is set in the scan flip-flop 211 by a scan-in operation, and the selector 21
3, and is given to the RAM 203 via the signal line 216. R
The output result of the AM 203 is the signal line 217 and the selector 214.
After reaching the scan flip-flop 212, it is observed at the scan-out terminal 208 by the scan-out operation.

When the partial logic circuit 204 is tested, the selector 214 causes the scan flip-flop 212 by inputting 1 to the mode select terminal 209.
Output data is selected and given to the partial logic circuit 204.
The test data is input from the scan-in terminal 207,
By the scan-in operation, it is set in the scan flip-flop 212 via the scan flip-flop 211, and given to the partial logic circuit 204 via the selector 214 and the signal line 218. The output result of the partial logic circuit 204 is observed at the data output terminal 206.

With the above configuration, the test for the failure of the signal lines 215 to 218 through which the data passes in the normal mode can be performed at the time of the test, and the partial logic circuit 202,
Since the 204 and the RAM 203 can be independently tested, even if one of the partial logic circuits is difficult to test, it does not affect the testability of the remaining partial logic circuits.

Although the partial logic circuit 203 is a RAM in this embodiment, the same effect can be obtained even if it is a general logic circuit such as a storage circuit such as a ROM or PLA, a combination circuit, or a sequential circuit. Is clear.

[0024]

As described above, according to the present invention, an externally controllable selector arranged on the path for transmitting data from the first partial logic circuit to the second partial logic circuit and the output of the selector are provided. By providing a scan flip-flop whose input is the output and whose output is the input of the selector, all failures on the path from the first partial logic circuit through which data passes in the normal mode to the second partial logic circuit are tested. Since it can be detected by the mode and each partial logic circuit can be tested independently, the test of each partial logic circuit becomes easy.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment.

FIG. 2 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment.

FIG. 3 is a configuration diagram of a semiconductor integrated circuit according to a conventional technique.

[Explanation of symbols]

 109 scan flip-flops 110 selectors 111, 112 signal lines 211, 212 scan flip-flops 213, 214 selectors 215-218 signal lines

Claims (1)

[Claims] 1. A first partial logic circuit, a selector having an output of the first partial logic circuit as an input, a second partial logic circuit having an output of the selector as an input, and an output of the selector. A flip-flop as an input, the flip-flop is connected to a scan path, the output value can be controlled and the input value can be observed by a scan operation, and the selector is controlled from the outside by the first part. A semiconductor integrated circuit characterized by selecting and outputting one of an output of a logic circuit and an output of the flip-flop.