JPH07112011B2 - Semiconductor memory - Google Patents

Description

The present invention relates to a memory cell for a high-speed bipolar memory LSI,
In particular, the present invention relates to a memory cell that is strengthened against soft error caused by radiation incidence.

[Conventional technology]

Circuit Diagram of Fastest Memory Cell Currently Known 12th
Figure (ISSCC Digest of technical Papers, 1977, pp
108-109). In this memory cell, it is necessary to insert a capacitance in parallel with the SBD in order to improve the strength against soft error due to radiation incidence (it is also possible to make the SBD a large area to obtain the required capacitance with the SBD capacitance). Therefore, the memory cell area increases. On the other hand, a memory cell that eliminates this defect and essentially improves the soft error strength is disclosed in Japanese Patent Application No.
-225738. This memory cell is a combination of a reverse-operating transistor and a shield type Schottky barrier diode (hereinafter abbreviated as SBD), and its plan view and sectional view are shown in FIGS.
In general, electrons of the charge pairs generated in the substrate 50 due to the incidence of radiation (eg, α-rays) are collected in the n ⁺ buried layer and cause a soft error. However, in the memory cell of this structure, the n ⁺ buried layers (transistor emitter layers 21 and 22 and shielded SBD shield n ⁺ BL layer 20) are
(Lower side) Word line (31 in Fig. 14), bit line (Fig. 14)
32a or 32b), connected to a suitable power supply or word line 30, etc. On the other hand, the p layer 23 is connected to an appropriate potential (for example, the lower word line 31) so that the junction between the n layers 20 and 24 is reverse biased. The SBD is formed between the electrode 30 (upper word line) and the n layer 24, and the low resistance R _L is the n layer 24.
It is formed by its own resistance, and is connected to the collector of the transistor by the conductive layer 25 (Al electrode, silicided polycrystalline silicon, or high-impurity-concentration polycrystalline silicon layer). In this embodiment, the high resistance R _H is formed by the high resistivity polycrystalline silicon 26 connected between the word line 31 and the p-type polycrystalline silicon 27 for drawing out the base. Of course, it goes without saying that the high resistance may be formed by any other method.

[Problems to be solved by the invention]

However, in the structure of the shield type SBD of the conventional example (Japanese Patent Application No. 59-225783), it is difficult to reduce the resistance of the n layer 24. That is, in order to manufacture a high performance transistor, it is necessary to form a shallow junction, so that it is necessary to reduce the thickness of the epitaxial layer (that is, the sum of the thicknesses of the n layer 24 and the p layer 23). Further, in order to form the p layer 23, whether p ⁺ is buried in the step before and after the formation of the n ⁺ buried layer, and is formed by rising (forming the p ⁺ buried layer) during the formation of the n epitaxial layer. Alternatively, a method of implanting a p-type impurity with high energy after the formation of the epitaxial layer or the like is conceivable. Regardless of whether the above method or other methods are used, since a considerable part of the epitaxial layer is the p layer, the specific resistance of the n layer is considerably high, and the n-layer is manufactured by the current standard process to have several KΩ. / It will be about mouth. Since the thickness of the epitaxial layer becomes thinner as the shallow junction is further advanced for higher performance in the future, it is difficult to lower this resistance in the future even if it increases. By the way, since the resistance of this n-layer is the series resistance of SBD (a part of R _L in Fig. 12), this resistance is 100 to 200 Ω in order to pass an operating current of several mA for high-speed operation of the memory cell. It is necessary to make it below, but it is usually because of high resistivity as mentioned above.
It can only be about 1KΩ. Of course, in FIG. 13, SBD
If the width of the memory cell is made extremely large, the resistance can be lowered, but the area of the memory cell becomes very large, which is unrealistic.

Thus, if the resistance in series with the SBD is large, the read current cannot be increased and it is impossible to realize a high-speed memory.

The above is a memory cell that uses a reverse-direction transistor and a shield-type SBD.However, even with a conventional memory cell that uses a forward-direction transistor, in order to reduce the cell area, a dedicated capacitor for soft error countermeasures is used. (For example, digging holes in silicon and using side walls
Capacitors that utilize high dielectrics such as Ta ₂ O ₅ ) are being used to reduce the SBD. In that case, as the area of the SBD becomes smaller, the series resistance associated therewith becomes larger, which also makes it impossible to operate at a large current, thus making it impossible to realize a high-speed memory.

[Means for solving problems]

In order to allow a large read current (up to several mA) to flow even if the SBD has a large series resistance of several hundreds to several KΩ, use a memory cell load consisting of a high resistance, SBD and low resistance parallel circuit. Further, some clamp circuit may be provided in parallel to bypass a large current. With such a structure, a large read current can be passed, and the speed can be increased.

[Action]

According to the present invention, in a memory cell in which a forward transistor and an SBD are combined or in which a reverse operation transistor and a shield type SBD are combined, a transistor is further arranged in parallel with a load device of the memory cell. A memory cell is provided. With this configuration, even if a large read current is passed through the memory cell, a part or most of the current flows from the parallel transistor of the load, so that the voltage of the memory cell is clamped and a substantially constant amplitude can be obtained. Therefore, even if the series resistance of the SBD is quite large (several KΩ), a large read current of several mA can flow. If there are no parallel transistors, all the current will flow through the SBD series resistance and the memory cell amplitude (voltage drop across the resistance) will be several KΩ.
× A very large value of several mA 10V. This is feasible and the memory cell transistors saturate well before such amplitudes appear. If the transistor is deeply saturated in this way, the read / write time becomes long, the high speed performance is impaired, and even isolation between adjacent memory cells is lost. Therefore, if the SBD has a large series resistance, it is impossible to flow a large read current to increase the speed.

That is, when the SBD has a large series resistance, a large read current can be made to flow by providing a parallel transistor according to the present invention, and high-speed read is possible for the first time.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to examples.

FIG. 1 is a circuit diagram of an embodiment of the present invention. The difference from the conventional memory cell in Fig. 12 is that the conventional load device (SBD
And a low resistance series circuit and a high resistance R _H are connected in parallel), and the transistor 33 (or 34) is further connected in parallel. That is, the base of transistor 33 or 34 is the upper word line and the collector is ground Vcc.
The emitters are connected to the collectors of the flip-flop transistors that make up the memory cell (not necessarily the ground, but an appropriate potential). Therefore, SB
The series resistance R _{L of} D is large and the voltage drop across SBD and the resistance R _L due to the read current I _R
When it becomes larger than the forward voltage V _BE between the emitters, the transistor 33 or 34 becomes conductive to bypass the read current and at the same time clamp the collector potential of the memory cell. Without this clamping effect, the voltage drop across the resistor R _L would be large and the on-side transistor 35 would saturate. When saturation begins, h _FE becomes smaller, the base current increases, and the base voltage also follows the collector voltage and drops. The current dependence of the collector potential of such a memory cell is shown in FIG. In this figure, the horizontal axis represents the total current flowing in the memory cell (the sum of the read current I _R and the information holding current I _st ) and the vertical axis represents the collector potential (high potential) V _c1 of the off-side transistor 36 and the on-side transistor 35. The collector potential (low voltage) V _c0 is shown. The collector potential is a potential measured with the word line as a reference (0V). It can be seen that the solid lines are V _c1 and V _c0 for the memory cell of the present invention shown in FIG. 1 and can be used without saturation of the transistor up to several mA.
On the other hand, the broken line shows the current dependence of the memory cell collector potential without the clamping transistors 33 and 34.Since the SBD series resistance is as high as 2 KΩ, the read current I _R is 0.2 to 0.3 mA at maximum. I can only run it. The delay time of the memory cell array and the sense circuit is determined by the read current. In the simulation result, the read current is
Access time can be reduced to about 1/3 by increasing from 0.2 to 0.3mA to 2mA.

FIG. 2 (b) shows an embodiment in which a memory cell array having a characteristic as described above is used to configure a memory cell array suitable for taking advantage of its high speed. According to the present application, since a large current can be passed through the memory cell, a large current can be passed as the read current I _{R to} increase the speed. Further, the word line discharge circuit 2 is provided in order to speed up the fall of the word line, but the discharge current by this circuit can be large because a large current can flow. Needless to say, any type of word line discharge circuit may be used (for example,
ISSCC Digrst '76, pp188-189, same '79, pp108-109, same '83,
pp108-109) FIG. 3 shows another embodiment of the present invention in which the collectors of the transistors 33 and 34 shown in FIG. 1 are connected to the upper word line instead of the ground. In the case of this embodiment, as will be described later, although the area is slightly larger than that of the embodiment of FIG. 1 by design, the n layers 24 and n of FIG. ^{+ When} there is a short circuit with the BL layer 20, no current flows between these layers, so the soft error strength increases.

FIG. 4 is a sectional view of the memory cell of the embodiment of FIG. 1 or FIG. Any device structure may be used as the transistor and the shield type device, but as in FIG. 14, the side wall base transistor structure mentioned in Japanese Patent Application No. 59-225738, 59-227730 is used as in FIG. I have given an example. The difference between this embodiment and the conventional example (Fig. 14) is that the shield type SBD 40 is surrounded by p ⁺ type polycrystalline silicon 41, and this polycrystalline silicon 41 is the word line.
Being connected to 30. That is, in the conventional example
In contrast to the SBD cathode layer (n-type layer) 24 and the shield p-type layer 24, a reverse bias or a small forward voltage (generally about 0.4 to 0.5 V) that does not allow the pn junction to conduct is applied. In the present invention, this pn junction is made completely conductive. When such an operation is performed, the n layer 24 functions as an emitter, the p layer 23 functions as a base, and the n ⁺ BL layer 20 functions as a collector, and these layers function as a transistor. Since the n ⁺ BL layer 20 is connected to the power supply Vcc when the clamping transistor is operated as an emitter follower, it may be shared with the same n ⁺ BL of the adjacent memory cells as shown by the solid line in FIG. But the third
When n ⁺ BL20 and the word line are connected as in the embodiment shown in the figure, it is of course necessary to separate them from the n ⁺ BL of the adjacent memory cell as indicated by the broken line.

FIG. 5 shows an embodiment in which the memory cell shown in the circuit diagram of FIG. 1 is actually laid out. Since the P-type polycrystalline silicon 41 is connected to the word line 30 as shown in FIG. 4, the high resistance 26 has a collector region as shown in FIG.
It can be connected to the word line without the need for providing 26 '. Therefore, the area of the memory cell can be reduced. Also, shielded SBD
Lower n ⁺ BL (Clamp transistor collector: 4th
In the figure, 20) is connected to the ground (Vcc) at a ratio of one to several to several tens of memory cells (in some cases, only at both ends of the memory cell array). Whether they should be connected at a different ratio depends on the current flowing through the clamp transistor, the specific resistance of the n ⁺ BL layer, and so on. Of course, if the number of connection points to the ground is small, the chip area can be reduced accordingly.

FIG. 6 is an embodiment of the layout of the memory cell of the circuit diagram of FIG. In this example, the shield SBD
The lower n ⁺ BL layer (collector of the clamp transistor: 20 in FIG. 4) is connected to the word line 30. The connection to the word line may be made every several to several tens between n ⁺ BL and the word line as in the embodiment of FIG. 5, but in this embodiment, the silicon region 42 (the structure is Each memory cell is provided with a word line (Al first layer in this embodiment) and n ⁺ BL (fourth region) which is similar to the collector contact and serves as an n ⁺ region.
It is connected to 20) in the figure.

FIG. 7 is a circuit diagram of another embodiment of the present invention.
In this embodiment, the base of the clamping transistor is
It is connected to two high resistance connection points connected in series. Therefore, the clamp level can be appropriately selected by appropriately selecting the division ratio of the high resistance, and the flexible design can be performed.

FIG. 8 shows an embodiment in which the memory cell of FIG. 7 is actually laid out. In this embodiment, the polycrystalline silicon 41 surrounding the SBD in FIG. 5 is divided into 41a and 41b. Therefore, in the cross-sectional view of FIG.
1) does not surround the p-type region 24 and is connected to the region 24 only at the left and right ends of the region 24. Therefore, when the right polycrystalline silicon (41a) is connected to the upper word line 30, the resistance of the p layer 24 is connected to the high resistance 26 in series. For the shield SBD40 to operate as a transistor, n ⁺ layer 2
Since it is in the vicinity of 8 (normal emitter layer), the base of the clamp transistor is connected to the connection point between the resistance of the p layer 24 and the polycrystalline silicon 26. The resistance division ratio can be designed to a desired value by appropriately selecting each parameter such as the impurity concentration, shape, and thickness of each resistance. Of course, it goes without saying that the two resistors may be resistors of the structure used conventionally or in the future.

FIG. 9 is another embodiment of the present invention in which the base of the clamp transistor is connected to the dividing point of the resistor and the collector is connected to the upper word line. With this configuration, flexibility in designing the memory cell potential can be obtained, and the strength against soft error can be improved.

FIG. 10 shows still another embodiment of the present invention, in which a resistor R _L ′ is further connected between the emitter of the clamping transistor and the series resistor of the SBD and the collector of the memory cell transistor. There is. This configuration also increases the degree of freedom in designing the memory cell at a low potential and enables flexible design.

FIG. 11 is another embodiment of the present invention, which also provides design flexibility and increased soft error resistance.

〔The invention's effect〕

According to the present invention, by connecting a clamping transistor in parallel with a load in a load-switching type memory cell by SBD, a large (several mA or more) read current can flow even when the SBD has a large series resistance. It becomes possible to achieve a very high speed in a large capacity memory.

[Brief description of drawings]

FIG. 1 is a circuit diagram of one embodiment of the memory cell of the present invention, and FIG.
FIG. 3A is a diagram showing voltage-current characteristics showing a difference in direct current characteristics between the conventional memory cell and the memory cell of the present invention,
FIG. 2 (b) is a diagram in which an array is formed by using the memory cell of the present invention, FIG. 3 is a diagram showing another embodiment of the memory cell of the present invention, and FIG. 4 is a diagram of FIG. Alternatively, FIG. 5 is a sectional view of the embodiment of the memory cell shown in FIG. 3, FIG. 5 is a plan view showing the actual layout of the memory cell shown in FIG. 1 or FIG.
FIG. 8 is a plan view of the actual layout of the memory cell of FIG. 3, FIG. 7 is a view showing another embodiment of the memory cell of the present invention, and FIG. 8 is a layout of the memory cell of FIG. FIG. 9 is a plan view showing another embodiment of the memory cell of the present invention, FIG. 10 is a view showing another embodiment of the present invention, and FIG. 11 is another view of the present invention. 12 is a diagram showing an embodiment of
The figure is a circuit diagram of a memory cell that has been conventionally used for high-speed operation. Fig. 13 is a plan view of the actual layout of the conventional memory cell of Fig. 12. Fig. 14 is Fig. 13 3 is a cross-sectional view of the memory of FIG. 1 taken along line AA ′.

Claims (2)

[Claims] 1. At least two transistors each having a collector and a base cross-connected to each other, a diode having a low forward voltage characteristic connected between a collector of the transistor and a word line, and a first resistor. A first load circuit consisting of a series circuit and a second resistor consisting of a second resistor connected between the transistor and the word line.
And a collector connected to a power supply or the word line,
A semiconductor having a clamping transistor whose base is connected to the word line or the middle point of the second resistance, and the emitter is connected to the collector of the transistor or the middle point of the first resistance. memory. 2. A semiconductor memory according to claim 1, wherein the clamping transistor is a transistor having an n-type silicon layer of a cathode of a Schottky barrier diode as an emitter layer.