JPS6132465A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase the operating margin at the time of transition by a method wherein required terminals symmetric in a circuit meaning are connected to each word line by two-division of the word line arranged in a memory array and connected to each memory. CONSTITUTION:The word line is two-divided into W1 and W2: a current stand- by line IST is so arranged as to pass through the center of a memory cell, and the word lines W1 and W2 are arranged in parallel with the current stand-by line IST and in symmetry across this line. Then, the anode side terminal of the first layer Schottky barrier diode SBD1 and SBD2 are connected to the second layer word lines W1 and W2 through-holes TH1 and TH2, respectively. One-ends of diffused resistors r2 and r1 are brought into contact with the aluminum electrode (first layer) of the diodes SBD1 and SBD2 via contact holes CH1 and CH2, respectively, and the other ends of the resistors r2 and r1 are joined to the base regions B1 and B2 of transistors Q1 and Q2 via P type semiconductor region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technology that is effective when applied to semiconductor integration technology and also to the formation of wiring in a semiconductor device, for example, a technology that is effective when applied to the formation of word lines in a bipolar memory. .

[Background Art] As a structure of a memory cell in a bipolar semiconductor memory, for example, the structure shown in FIG. 1 is known ("Memory", p. 94, published by the Institute of Electronics and Communication Engineers).

This memory cell has a Schottky barrier diode D1 with low forward resistance connected in parallel with a load resistor R1°R2 connected between the collectors of multi-emitter transistors Ql and Q2 constituting a blip-prop and the word line W.
By connecting +D2, the read current is increased, making it possible to reduce power consumption and increase the read speed.

In the figure, D is a digit line through which read and write currents are passed, and IST is a current standby line through which a holding current of a memory cell is passed during normal operation (standby).

By the way, in semiconductor memory, since it is necessary to configure a memory array by arranging memory cells with the above configuration in a matrix, the layout of the elements in each memory cell is designed in a form that allows for as high integration as possible. It is desirable to reduce the area occupied by the array.

Therefore, the layout of the memory cells is designed so that each element fits perfectly within, for example, a rectangular region that has good matching with adjacent memory cells. A matrix-like memory array M-ARY as shown in FIG. 2 is constructed by arranging a large number of such memory cells in parallel in the vertical and horizontal directions.

Therefore, in the memory array, word lines W, digit lines D, and a current standby line IST must be provided in order to select each memory cell and cause read, write, or holding current to flow therein. .

However, in order to reduce the occupied area of the memory array, in addition to the consistency of each memory cell, a set of word lines W, digit lines D, and current standby lines are provided on the occupied area of each memory cell row or column. The wiring layout must be designed so that the IST is completely accommodated.

Therefore, the present inventor arranged a pair of digit lines D along and above each column of memory cells MC using the first layer of aluminum wiring, as shown by the chain lines in FIG. One word line W and one current standby line IST are each provided on i along the row of cells MC using second layer aluminum wiring. A diode D1 . in the memory cell is connected to the word line W. We considered a method in which the anode side terminal of D2 was connected through the first aluminum layer.

As a result, each memory cell M can be
C can be closely wired without gaps to minimize the area occupied by the memory array.

However, when applying the word line W arrangement method as described above, if the layout of each memory cell is not symmetrical with respect to the memory cell center line in the direction perpendicular to the word line W, the word line W The distances of the first-layer aluminum wiring (wire corresponding to the aluminum bond lines ρ1 and Q2 in FIG. 4) connecting the cathode terminal, base, and collector of each Schottky barrier diode in the memory cell are not equal. Therefore, as shown in FIG. 1, the magnitudes of the coupling capacitances C1 and C2 parasitically connected between the word line W and the node notnl in the memory cell are different, resulting in an imbalance in the readout of retained information. This will cause

In other words, if the coupling capacitances C1t and C2 have different sizes, when the level of the word line W is raised during reading, if the coupling capacitances C1 and C2 are equal, the levels of nodes nO and 11i will be as shown in FIG. As shown by the solid line A, if the coupling capacitances C1 and C2 are unbalanced, the level of the node connected to the larger coupling capacitance will rise to the third level. As shown by the broken line B in the figure, it is pushed up at the end of the rise, creating a peak.

As a result, the margin of the read level (110' level and '1' level) with respect to the read reference voltage V r e f becomes small, which causes problems such as erroneous reading and making design difficult. revealed by.

[Objective of the Invention] An object of the present invention is to provide a semiconductor memory device consisting of memory cells of a flip-flop configuration.
An object of the present invention is to provide a wiring layout method that increases the operating margin of the device, facilitates design, and enables accurate readout.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, in a semiconductor memory device equipped with a memory array consisting of memory cells having a flip-flop configuration, the present invention divides a word line arranged in the memory array and connected to each memory into two to create a circuit symmetrical structure. By connecting a predetermined terminal to each word line, even if the memory cell is laid out asymmetrically with respect to the center line in the direction perpendicular to the word line, the cup can be connected to the node in the memory cell. This achieves the above-mentioned objective of increasing the operating margin during transient times by making the ring capacitances equal and preventing unbalance in the read level.

The present invention will be described in detail below along with examples.

Embodiment FIG. 4 shows an embodiment of a memory array in which the present invention is applied to a bipolar memory consisting of memory cells having a flip-flop configuration.

In FIG. 4, 5BD1.5BD2 is a Schottky barrier diode, Bly El
1 y El 2 r CN1 and B2+E21,
The multi-emitter transistors Q1.R22 and CN2 respectively constitute flip-flops. Q
2 base, emitter opening 11 (contact hole)
and a collector drawer. Note that the load resistors R1 and R2 on the collector side are formed as diffused resistors at locations as indicated by broken lines r1+r2 in FIG. here,
In accordance with the symmetrical memory cell configuration shown in Figure 1, by designing the layout of each element to be point symmetrical as shown in Figure 1, the memory cell can be made compact and the adjacent memory Improved consistency with cells,
High integration is possible.

In other words, by arranging a large number of memory cells MC with a layout like the one shown above in succession in the vertical and horizontal directions, no extra blank area (gap) is created between adjacent memory cells. can be placed. This allows memory arrays to be highly integrated.

However, in the layout of the memory array as described above, if the word lines W are arranged along the horizontal direction of the drawing in the same manner as shown in FIG. Since the memory cell is off-center and the memory cell does not have layout symmetry with respect to the memory cell center line in the direction perpendicular to the word line, there is a gap between the word line W and the node no+nl in the memory cell. The sizes of the coupled coupling capacitors C1 and C2 are not equal. In order to make this equal, the word line W is arranged at the center of the memory cell MC, and two terminals (anode side terminals of Schottky barrier diodes D1 and D2) that are symmetrical in circuit with respect to the word line W are arranged. ) can also be considered to make the distances equal.

However, if the word line W is arranged at the center of the memory cell MC, when attempting to arrange the current standby line IST while ensuring a predetermined wiring pitch, the current standby line IST will protrude outside the memory cell MC. There is a problem of it being put away.

Therefore, in this embodiment, although not limited to, the word line W is formed to have a wider line width than the current standby line IST in order to allow a relatively large current to flow therethrough. The word line W was divided into two parts, Wl and W2. The current standby line IST is arranged to pass through the center of the memory cell MC, and the divided word lines W1 and W2 are connected to the current standby line IST.
It was arranged parallel to and symmetrically across it.

In this way, for the word line WllW2 made of the second aluminum layer divided into two and symmetrically arranged,
The anode side terminals (electrodes) of Schottky barrier diodes 5BD1 and 5BD2 made of the first aluminum layer are coupled through through holes TH1 and TH2, respectively. Note that the diffused resistors r1 and r2 constituting the load resistors R1 and R2 are connected to Schottky barrier diodes 5BD2 and 5BD1 on opposite sides, respectively, due to layout considerations.
It is located adjacent to. In addition, the cathode side terminals of the Schottky barrier diodes S B D i and S B D 2 are connected to the transistor Ql via the N+ buried layer below the semiconductor region constituting the Schottky barrier diodes S B D i and S B D 2, as will be explained later by showing a cross section. , Q2 (N+ diffusion layer).

On the other hand, one ends of the diffused resistors r2 and rl are connected to the Schottky barrier via contact holes CH1 and CH2, respectively.
Aluminum electrodes of diodes 5BD1 and 5BD2 (first layer)
The other ends of resistors r2 and rl are connected to the base regions (BitB) of transistors Q1 and Q2 via a P-type semiconductor region.
2) respectively. Furthermore, this base region (B1°B2) is the first aluminum wiring layer U1+Q2
via contact holes CH3 and CH4 to the other transistor Q2. Collector region CN2°CN of Qh,
It is connected to the. Further, the emitter regions E11 and E21 of the transistors Q1 and Q2 are connected to each other via a common first aluminum wiring layer Q3, and this first aluminum wiring layer Q3 is connected to a current standby layer formed by a second aluminum layer. It is connected to ST through a through hole TH3.

The data lines D are connected to the word lines W1. by the first aluminum layer. It is arranged along the direction perpendicular to w2, and the emitter region (E2□) of transistor Q2 is located on the data line.
However, the emitter region (E12) of transistor Q1 is also coupled to each data line.

A cross section taken along the line AA' and line B-B' in FIG. 4 will be described with reference to FIGS. 5 and 6.

In FIG. 5 showing a cross section along the line AA' in FIG. 4, the Schottky barrier diode 5BD2 is
N+ selectively formed on P-type silicon semiconductor substrate 1
A P-type semiconductor region 4 is formed by selectively introducing P-type impurities into a part of the main surface of an N-type epitaxial layer 3 grown in vapor phase on the buried layer 2, and a P-type semiconductor region 4 is formed by vapor-depositing on the surface thereof. and a barrier electrode 5 made of the first aluminum layer formed. A Schottky barrier diode 5BD3 of an adjacent memory cell is formed adjacent to this Schottky barrier diode 5BI)2. These Schottky barrier diodes 5BD2
Although not particularly limited, and 5BD3 are separated by a U-groove isolation region 6 formed relatively deeply so as to penetrate the N+ buried layer 2. The U-groove isolation region 6 is formed using a known element isolation technique in which a trench is dug in a semiconductor substrate, the inside of the trench is oxidized to form an insulating film 7, and then a dielectric material 8 such as polysilicon is filled. be. This U-trench isolation region 6 can also be replaced with a relatively thick field oxide film.

Although not particularly limited, the electrodes 5 of the Schottky barrier diodes 5BD2 and 5BD3 that are adjacent to each other are integrated by continuously forming an aluminum layer, a part of which is connected to the diffused resistor r1, which is the load resistor R1. It is extended to cover one end.

The semiconductor region 9 made of a single N layer on the cathode side of the Schottky barrier diode 5BD2 is connected to the collector region 20 (of the transistor Q2) via the N+ buried layer 2 below.
(See Figure 6).

The diffused resistance r1 is a P-type semiconductor region I formed by introducing P-type impurities onto the N-type epitaxial layer 3.
Consists of O. This P-type semiconductor region 10 as the diffused resistance r1 and the Schottky barrier diode 5BD2
It is separated from the P-type semiconductor region 4 constituting the N-type epitaxial layer 3 by a relatively shallow U-groove isolation region 6' penetrating the N-type epitaxial layer 3.

By introducing P-type impurities onto the main surface of the N-type epitaxial layer 3 so as to be in contact with the P-type semiconductor region 10 serving as the diffused resistor r1, a P-type semiconductor region 11 that will become the base region of the transistor Q2 is formed. It is formed. Further, by introducing an N-type impurity into a part of the main surface of this P-type semiconductor region 11, N-type semiconductor regions 12a and 12b are formed as two emitter regions (E2□tE21) of the transistor Q2. ing.

A portion of the insulating film 13 on the surface of the N-type semiconductor regions 12a and 12b and the surface of the P-type semiconductor region 11 between these semiconductor regions 12a and 12b is removed to form an opening, in which a data line is inserted. In order to connect the aluminum wiring layer 15 (Qs) for connecting the aluminum wiring 14 and the emitter region of the other transistor Q1 and the P-type semiconductor region 11 serving as the base region to the collector region (not shown) of the other transistor Q1. Aluminum wiring layer 16 (C2)
are each formed by a first aluminum layer and are in contact with a corresponding semiconductor region.

A silicon oxide film or a PSG film (phosphorus silicate glass film) is formed on the barrier electrode 5 of the Schottky barrier diode 5BD2 and each of the aluminum wiring layers 14 to 16.
An interlayer insulating film 17 is formed, on which an aluminum wiring layer 18 that becomes a current standby line IST and an aluminum wiring layer 19 that becomes a word line W2 are formed by a second aluminum layer. .

FIG. 6, which shows a cross section taken along the line BB' in FIG. .2b is shown. An N1 type semiconductor region 20 is formed adjacent to this N type semiconductor region 12b and serves as a collector pull-up port of the transistor Q2. The P-type semiconductor 11 and the N+ type semiconductor region 20 are separated by a shallow U-groove isolation region 6'.

Then, adjacent to the N+ type semiconductor region 20 which becomes the collector pull-up port of the transistor Q2, a P type semiconductor region 21 which becomes the base region of the other transistor Q1 is formed. That is, the collector of the transistor Q2 and the base of the transistor Q1 are connected by an aluminum wiring layer 22 (Ql) made of the first aluminum layer. The opening 23 formed in the insulating film 13 on the N+ type semiconductor region 20 is the contact hole CH3 shown in FIG. 4. The N + -type semiconductor region 20 and the P-type semiconductor region 21 are separated by a deep U-groove isolation region 6 .

A glabellar insulating film 17 is formed on the aluminum wiring layer 22, and a word line 24 (Wl) made of a second aluminum layer is formed on the glabella insulating film 17, and the word line 19 (Wl) and the current standby line 18 ( IST).

The structure of the transistor C2 side has been described above using the cross-sectional diagram, but the structure of the transistor C1 side is also similar.

FIG. 7 shows a circuit diagram of a memory cell with wiring and connections as described above.

Note that, although not particularly limited, the word lines W1 and Wl divided into two are coupled to one word line outside the memory array M-ARY and driven by a common word line drive circuit.

By doing this, the wiring pitch can be secured and the word line W1
．． Even if W2 and the current standby line IS'l'' are arranged, the wiring can be completely contained within the width of the memory cell MC, and the wiring can be placed neatly without creating a blank area between adjacent memory cells. A memory array can be arranged.

Moreover, the word line W1. which is divided into two and arranged symmetrically as described above. Schottky barrier diode D in W2
1. D2 is connected, the node no+nl in memory cell MC and word line W1. Coupling capacitances C1 and C2 connected between W2 become equal. Therefore, there is no imbalance caused by the coupling capacitors C1 and C2 in changes in the levels of the nodes n0 and n during a transition such as during reading.

As a result, the transient characteristics of nodes nO and 01 become uniform,
The peak as shown in FIG. 3 disappears and the reference voltage Vre
Since the margin for f becomes larger, design becomes easier and erroneous reading is also prevented.

Furthermore, the current standby line IST is also connected to the memory cell MC.
Since the current standby line IST
The capacitances connected to are also made equal.

Furthermore, by designing the width of the word line to be wider than the current standby line as described above, it is possible to design a memory that has the function of simultaneously reading multiple bits of memory cells by flowing a large current through the word line, for example. becomes easier.

In the above embodiment, the word line W is divided into two parts and arranged symmetrically across the current standby line IST, but the word line W is arranged in the center and the current standby line IST is divided into two parts.
It may be divided and arranged symmetrically on both sides of the word line W.

Further, the layout of the memory cells is not limited to that shown in FIG. 4.

[Effect] In a semiconductor memory device equipped with a memory array consisting of memory cells in a flip-flop configuration, a word line arranged in the memory array and connected to each memory cell is divided into two, and a predetermined line symmetrical in terms of circuitry is formed. Since the terminals are connected to each word line, the coupling capacitance connected to the node within the memory cell can be reduced even if the layout of the memory cell is asymmetrical with respect to the center line in the direction perpendicular to the word line. By making them equal, there will be no unbalance in the level during reading, which will allow for a large operating margin during transients, which will facilitate design and prevent erroneous data reading. There is.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the configuration of a flip-flop type memory cell is not limited to that of the above embodiment, but may be one in which the Schottky barrier diode is omitted, or one in which a Schottky barrier diode is used in parallel to increase speed.・It may be in the form of a capacitor connected.

[Field of Application] In the above description, the invention made by the present inventor was mainly applied to bipolar memory, which is the field of application that formed the background of the invention, but the present invention is not limited thereto.
It can also be used for MOS type memory, etc.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell in a conventional bipolar memory. FIG. 2 is a configuration diagram showing an example of the layout configuration of a conventional memory array. 4 is a configuration diagram showing an example of the layout configuration of a memory cell when the present invention is applied to a bipolar memory, and FIG. 5 is a waveform diagram showing the transient characteristics of the node in FIG. 6 is a sectional view taken along the line BB' in FIG. 4. FIG. 7 is a circuit configuration when the layout configuration as shown in FIG. 4 is adopted. It is a circuit diagram. Ql, Q2...Multi-emitter transistor, R
,, R2...Load resistance, Dl, D2,5BD7,5
BD2...Schottky barrier diode, cl
, C2...Coupling capacity, W. Wl, W2...word line, IST...current standby line, D, D...digit line. Figure 1 Figure 2 Figure-11KI

Claims (1)

[Claims] 1. In a semiconductor memory device including a memory array consisting of memory cells having a circuit-symmetrical flip-flop configuration, the same wiring is connected to each memory cell arranged in the memory array. A semiconductor memory device characterized in that the memory cell is divided into two parts and arranged symmetrically, and symmetrical predetermined terminals in the memory cell are connected to the divided wirings. 2. A patent claim characterized in that the memory cells are laid out asymmetrically with respect to a center line in a direction orthogonal to the word line, and the word line is divided into two and arranged symmetrically. The semiconductor memory device according to item 1.