JPS62256469A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make a large readout current flow even in case the series resistance of an SBD is large and to contrive the speedup of a large-capacity memory by a method wherein, in a load change-over type memory cell using the shield type Schottky barrier diode (SBD), a transitor for clamp is connected in parallel to a load. CONSTITUTION:The base, collector and emitter of a transistor 33 or 34 are respectively connected to an upper side word line, a ground VCC (Even though it is not a ground, it can be a proper potential.) and the collector of a flip-flop transistor constituting a memory cell. Accordingly, when the series resistance RL of an SBD is large and the voltage drop and the SBD and the resistance RL due to readout current IR becomes larger than the base-emitter forward voltage VBE of the transistor 33 or 34, the transistor 33 or 34 is conducted and with the readout current bypassed, the collector potential of the memory cell comes to be clamped. If there is no this clamping effect, a transistor 35 on an ON side is saturated because the voltage drop at the resistance RL is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory cell for a high-speed bipolar memory LSI, and in particular to a memory cell reinforced against soft errors due to radiation incidence.

[Conventional technology]

The first circuit diagram of the fastest memory cell currently known.
As shown in Figure 2 (ISSCCDigest of technology
nicalPapers, 1977, pp 10
8-109). In this memory cell, S
Inserting a capacitor in parallel with the BD (making the SBD large area
(It is also possible to obtain the necessary capacity with the BD capacity), the memory cell area increases by 19. On the other hand, a memory cell which eliminates this drawback and essentially improves the strength against soft errors is described in Japanese Patent Application No. 59-225738. This memory cell consists of a reverse-operating transistor and a shielded Schottky barrier diode (hereinafter abbreviated as S).
BD), the plan view and cross-sectional view of which are shown in FIGS. It collects in the buried layer and causes soft errors. However, in the memory cell with this structure, the n+ buried layers (the emitter layers 21 and 22 of the transistor and the shield n+ BLR 420 of the shielded SBD) are (
The lower part) is connected to the word wIi (31 in FIG. 14), the bit line (32a or 32b in FIG. 14), a suitable power supply or word line 30, etc. On the other hand, the 2nd layer 23 is the 0th layer 2
The junctions between 0 and 24 are connected to a suitable potential (eg, lower word line 31) such that both are reverse biased. The SBD is formed between the electrode 30 (upper word line) and the first layer 24, the low resistance RL is formed by the resistance of the n layer 24 itself, and the conductive layer 25 (Ajl electrode, silicided polycrystalline silicon, or high polycrystalline silicon layer with impurity concentration)
connected to the collector of the transistor. Also high resistance R
In this embodiment, o is formed of polycrystalline silicon 26 having a high specific resistance and connected between word line 31 and p-type polycrystalline silicon 27 for leading out the base.

Of course, it goes without saying that the high resistance may be formed by any other method.

[Problem that the invention seeks to solve]

However, in the structure of the shield type SBD of the conventional example (Japanese Patent Application No. 59-225783), it is difficult to form one layer 24 with a low resistance. In other words, in order to make a high-performance transistor, it is necessary to form a shallow junction, so the thickness of the epitaxial layer (that is, the sum of the thicknesses of the first layer 24 and the second layer 23) must also be made thin. In addition, in order to form the second layer 23, it is necessary to bury the p layer in the steps before and after forming the n ÷ buried layer, and then let it rise up during the n epitaxial formation (p ÷ form the buried layer), or Possible methods include implanting p-type impurities with high energy after forming an epitaxial layer.

Regardless of whether these or other methods are used, since a significant portion of the epitaxial layer will be the p-layer, the resistivity of the n-layer will be quite high and can be manufactured using current standard processes by several Ω/Ω. It will be about a mouthful. The thickness of the epitaxial layer will become thinner as junctions become shallower in order to improve performance in the future, so although this resistance may increase in the future, it will be difficult to reduce it. By the way, this n-layer resistance is the series resistance of the SBD (part of Rt in Figure 12), so in order to flow an operating current of several mA for high-speed operation of the memory cell, this resistance must be 100 to 2000 mA. However, since the resistivity is high as mentioned above, it is usually only possible to set it to a value of about IKΩ.Of course, the resistance can be lowered by making the width of the SBD very large in Figure 13, but the area of the memory cell becomes very large and unrealistic.

If the resistance in series with the SBD is large as described above, the read current cannot be increased, making it impossible to realize a high-speed memory.

The above is a memory cell using a reverse transistor and a shielded SBD, but even with a conventional memory cell using a forward transistor, in order to reduce the cell area,
Efforts have begun to be made to reduce the SBD by using a dedicated capacitance (for example, by drilling a hole in silicon and using the side wall, or by using a high Vi electric material such as TazO+%) as a capacitor to prevent soft errors. In this case, as the area of the SBD is made smaller, the accompanying series resistance becomes larger, resulting in the problem that large current operation becomes impossible and it becomes impossible to realize a high-speed memory.

[Means for solving problems]

In order to be able to flow a large read current (~several mA) even if the series resistance of the SBD is large, on the order of several hundred to several ohms, a memory cell consisting of a high resistance, SBD and a low resistance parallel circuit is required. What is necessary is to further provide some sort of clamp circuit in parallel with the load to bypass a large current. By adopting such a structure, a large read current can flow, and high speeds can be achieved.

[Effect]

According to the present invention, in a memory cell that combines a forward transistor and an SBD or a memory cell that combines a reverse operation transistor and a shielded SBD, a transistor is further arranged in parallel with the load device of the memory cell. A memory cell is provided. With the second configuration, even if a large read current is passed through the memory cell, part or most of the current flows from the parallel transistors of the load, so the voltage of the memory cell is clamped and a substantially constant amplitude can be obtained. Therefore, even if the series resistance of the SBD is quite large (several ohms), a large read current of several mA can flow. Without parallel transistors, all current is SB
The amplitude of the current flowing through the series resistor D (voltage drop across the resistor) of the memory cell becomes a very large value of several Ω×several mA and about 10 V. This is achievable and the memory cell transistor saturates long before such an amplitude appears.

If the transistor becomes deeply saturated in this way, the read/write time becomes long, which not only impairs high speed performance but also causes a situation where isolation between adjacent memory cells is lost. Therefore, if the series resistance of the SBD is large, it is impossible to increase the speed by passing a large read current.

That is, when the series resistance of the SBD is large, by providing parallel transistors according to the present invention, it becomes possible to flow a large read current, and high-speed read becomes possible for the first time.

〔Example〕

Hereinafter, the present invention will be explained in detail using examples.

FIG. 1 is a circuit diagram of an embodiment of the present invention. The difference from the conventional memory cell in Figure 12 is that the conventional load device (S
A transistor 33 (or 34) is further connected in parallel to a circuit in which BD, a low-resistance series circuit, and a high-resistance RH are connected in parallel. In other words, transistor 33
Alternatively, the base of 34 is connected to the upper word line, the collector is connected to ground Vcc (which may be any suitable potential other than ground), and the emitter is connected to the collector of the flip-flop transistor constituting the memory cell. Therefore, the series resistance RL of the SBD is large and the read current I
The voltage drop across SBD and resistor R is the base-emitter forward voltage V of transistor 33 or 34.
When it becomes larger than Bp, the transistor 33 or 34 becomes conductive, thereby bypassing the read current and simultaneously clamping the collector potential of the memory cell. Without this clamping effect, the voltage drop across the resistor R would increase, causing the on-side transistor 35 to saturate.

When saturation begins, hrp decreases, the base current increases, and the base voltage also decreases, almost following the collector voltage.

The current dependence of the collector potential of such a memory cell is shown in FIG. 2(a). In this figure, the horizontal axis shows the total current flowing through the memory cell (the sum of the readout current 8 and the information holding current Ixt), and the vertical axis shows the collector potential of the off-side transistor 36 (
(high potential) Val and the collector potential (low voltage) Vco of the on-side transistor 35. The collector potential is a potential measured with the word line as a reference (Ov). The solid line indicates the Vct for the memory cell of the present invention shown in FIG.
y Vco, it can be seen that it can be used up to several mA without saturating the transistor. On the other hand, the broken line shows the current dependence of the memory cell collector potential in the absence of the clamping transistors 33 and 34, and the series resistance of the SBD is 2.
Since the current is as high as Ω, the read current I++ is at most 0.2~
The delay time of the memory cell array and sense circuit, which can only flow 0.3 mAL, is determined by the read current. In the simulation results, the read current is, for example, 0.2~
By increasing from 0.3 mA to 2 mA, the access time can be reduced by about 1/3.

Figure 2(b) shows an example of a memory cell array suitable for taking advantage of its high speed using memory cells with such characteristics. Therefore, a large current can be passed as the read current IR to increase the speed. Also.

A word line discharge circuit 2 is provided in order to speed up the falling of the word line, and this circuit allows a large current to flow as a discharge current, making it possible to speed up the falling of the word line. It goes without saying that any type of word line discharge circuit may be used (for example, 15SCCDi
grst '76, ppl 88-189, same'
79. pp108-109. #83゜ρp108-1
09) FIG. 3 is another embodiment of the invention in which the collectors of transistors 33, 34 of FIG. 1 are connected to the upper word line instead of to ground. In the case of this embodiment, as will be described later, the area may be somewhat larger than the embodiment shown in FIG. 1 depending on the design, but due to the so-called funneling effect that occurs when α rays are incident, layer 20
Because no current flows between these layers when the top 20 is shorted.

The soft error strength increases.

FIG. 4 is a cross-sectional view of the memory cell of the embodiment of FIG. 1 or 3. FIG. Although any device structure may be used for the transistor and shield type device, FIG. 4 is similar to FIG.
An example using the sidewall-based transistor structure mentioned in No. 9-227730 is given. The difference between this embodiment and the conventional example (Fig. 14) is that the shield type 5BD40
is surrounded by p-type polycrystalline silicon 41, and this polycrystalline silicon 41 is connected to word line 30. That is, in the conventional example, the cathode layer (n
In contrast, only a reverse bias or a small forward voltage (generally about 0.4 to 0.5 V) to the extent that the p-n junction is not conductive was applied to the p-type layer 24 and the p-type layer 24 for shielding. Now, this pn junction is made completely conductive. When this operation is performed, the first layer 24 becomes an emitter, pJFt23
is the base, n+BLJf[J20 is the collector, and these layers perform a transistor action. n÷R
Since the L Ji920 is connected to the power supply Vcc when the clamping transistor is operated as an emitter follower, it is connected to the similar n of the adjacent memory cell as shown by the solid line in Figure 4.
However, when connecting n+BL 20 and the word line as in the embodiment shown in FIG.
Must be separated from L.

FIG. 5 shows an example of an actual layout of the memory cells shown in the circuit diagram of FIG. The p-type polycrystalline silicon 41 is as shown in FIG.

Since it is connected to the word line 30, the high resistance 26 is connected to the first
As shown in FIG. 3, it is possible to connect to the word line without providing a contact region 26'. Therefore, the area of the memory cell can be reduced. In addition, H+BL below the shield type SBD
(Collector of clamp transistor: 20 in Figure 4)
is connected to ground (Vcc) at one location for every several to several dozen memory cells (in some cases, only at both ends of the memory cell array), but in reality, it is connected at one location for every few memory cells. Whether this should be done depends on the current flowing through the clamp transistor, the specific resistance of the n+BL layer, etc. Of course, the smaller the number of connection points to ground, the more the chip area can be reduced.

FIG. 6 is an example of the layout of the memory cells in the circuit diagram of FIG. 3. In this example, the shield SB
The n+BL layer below D (collector of the clamp transistor: 20 in FIG. 4) is connected to the word line 30.

The connection to the word line may be made between n+B L and the word line every few to several dozen words as in the embodiment shown in FIG. 5, but in this embodiment, the silicon region 42 (
The structure is similar to a collector contact and is an n+ region) is provided in each memory cell to connect the word line (in this example, the first layer of AJ) and n+BL (20 in Figure 4). .

FIG. 7 is a circuit diagram of another embodiment of the present invention.

In this example, the base of the clamping transistor is
It is connected to two high resistance connections connected in series. Therefore, by appropriately selecting the high resistance division ratio, the clamp level can be appropriately selected, allowing for flexible design.

No. 8.4 is an example of an actual layout of the memory cells shown in FIG. 7. In this embodiment, the polycrystalline silicon 41 surrounding the SBD in FIG.
It is divided into b. Therefore, in the cross-sectional view of FIG. 4, the polycrystalline silicon (41) does not surround the p-type head region 24;
It is connected to the area 24 only at the left and right ends of the area 24. Therefore, when the right polycrystalline silicon (41a) is connected to the upper word line 30, the resistance of the second layer 24 is connected in series with the high resistance 26. Since the shield 5BD40 operates as a transistor near the n10 layer 28 (normal emitter layer), the base of the clamping transistor is connected to the connection point between the resistor formed by the two layers 24 and the polycrystalline silicon 26. It turns out. The division ratio of the resistors can be designed to a desired value by appropriately selecting parameters such as impurity concentration, shape, and thickness of each resistor. Of course, it goes without saying that resistors of any conventional or future construction may be used as the two resistors.

FIG. 9 shows another embodiment of the invention in which the base of the clamp transistor is connected to the dividing point of the resistor and the collector is connected to the upper word line.

This configuration provides flexibility in designing the memory cell potential and improves resistance to soft errors.

FIG. 10 shows yet another embodiment of the present invention, in which a resistor RL/ is further inserted between the emitter of the clamping transistor and the collector of the memory cell transistor as the connection point between the series resistor of the SBD. . With this configuration, the degree of freedom in designing the low potential of the memory cell increases and flexible design becomes possible.

FIG. 11 shows another embodiment of the present invention, which also provides design flexibility and increased resistance to soft errors.

〔Effect of the invention〕

According to the present invention, by connecting a clamping transistor in parallel with the load in a load switching type memory cell using an SBD, it is possible to flow a large read current (several mA or more) even when the series resistance of the SBD is large. This has the effect of greatly increasing speed in large-capacity memory.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the memory cell of the present invention, and FIG.
Figure (a) is a diagram showing voltage-current characteristics showing the difference in DC characteristics between a conventional memory cell and a memory cell of the present invention;
FIG. 2(b) is a diagram showing an array constructed using the memory cell of the present invention, FIG. 3 is a diagram showing another embodiment of the memory cell of the present invention, and FIG. 4 is a diagram similar to the one shown in FIG. 3, FIG. 5 is a plan view of the memory cell shown in FIG. 1 or 3, and FIG. 6 is a plan view of the memory cell shown in FIG. FIG. 7 is a plan view showing the actual layout of the cell; FIG. 81i2I is a plan view showing the layout of the memory cell of FIG. 7; FIG. , FIG. 10 is a diagram showing another embodiment of the present invention, FIG. 10 is a diagram showing another embodiment of the present invention, FIG. 11 is a diagram showing another embodiment of the present invention, and FIG. The figure is a circuit diagram of a memory cell suitable for high speed that has been used conventionally.
4 shows the memory in FIG. 13 along the line A-A'. Figure 8 Figure 9 Figure Io Figure % u Figure 12

Claims (1)

[Claims] 1. At least two transistors whose collectors and bases are cross-connected to each other, a diode having low forward voltage characteristics connected between the collectors of the transistors and a word line, and a first A memory cell having a first load circuit comprising a series circuit with a resistor, and a second load resistor comprising a second resistor in which the transistor is connected between the collector and the word line, further comprising: is connected to the power supply or the word line,
A semiconductor comprising a clamping transistor whose base is connected to the word line or a point halfway through the second resistor and whose emitter is connected to the collector of the transistor or a point halfway through the first resistor. memory. 2. The semiconductor memory according to claim 1, wherein the clamping transistor is a transistor whose emitter layer is an n-type silicon layer of a cathode of a Schottky barrier diode.