JPH07111764B2 - PCM signal reproduction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION When recording and reproducing an audio signal, high-quality recording and reproduction can be performed by converting the audio signal into PCM.

1 and 2 show an example of a recording system and a reproducing system of such a PCM tape recorder.

That is, in the recording system of FIG. 1, the audio signal Sa
Is supplied to the A / D converter (12) through the input terminal (11) and is converted into a PCM signal Sp with a sampling frequency of 44.656 kHz and 1 word 16 bits as shown in FIG. 5A. 5th through recording encoder (13)
As shown in FIG. B, the memory circuits (14A) and (14B) have, for example,
The data are written alternately for 1/60 seconds, and the written signal Sp is read alternately for each period T ₁ at a speed twice as fast as the writing as shown in FIG. 5C.

In this case, in FIG. 5, the periods Ta and Tb are unit periods alternately located every 1/60 seconds, and the periods T ₀ and T ₁ are the period T.
These are the first half and the second half of the period when a and Tb are divided into two equal parts.

Therefore, from the encoder (13), as shown in FIG. 5D, the PCM signal whose time axis is compressed to 1/2 and located in the period T _1.
Sc is taken out. That is, each block of the signal Sc is
It is a PCM signal which has audio information for each 1/60 second and is located in the period T ₁ with the time axis compressed to 1/2.

At this time, an error correction / correction code forming circuit (15) is connected to the encoder (13), and processing for error correction and error correction is performed for each block of the signal Sc. , Interleaving is performed within one block of the signal Sc, and CRC and parity bit are added every two words. The signal Sc also has a brimble (running in) at the beginning of each block.

The processing by the circuits (12) to (15) described above is performed in synchronization with the clock and the control signal from the clock forming circuit (30).

Then, this signal Sc is supplied to the rotary magnetic heads (1A) and (1B) through the recording amplifier (16).

As shown in FIG. 3, the heads (1A) and (1B) have an angular interval of 180 ° with each other, and the motor (4) passes through the rotating shaft (3) at a rate of 30 times per second to indicate the arrow (6H). ), The magnetic tape (2) is slanted around the rotating peripheral surface over an angular range of a little over 90 °, and the tape (2) is held by a capstan and a pinch roller (not shown). ) Is driving at a constant speed in the direction of the arrow (6T).

Further, the rotations of the heads (1A) and (1B) are synchronized with the periods Ta and Tb by servo control. That is, for example, as shown in FIG. 5E, a pulse Pr is taken out from the forming circuit (30) at each start time of the period T ₁ in the period Ta, and this pulse Pr is supplied to the servo circuit (41) and the For example, the rotating shaft (3) of (1A), (1B) is provided with a pulse generating means (42), and one pulse is taken out for each rotation of the heads (1A), (1B), and this pulse is outputted to the servo circuit. (41), the output of the servo circuit (41) is supplied to the motor (4), and as shown in FIG. 3, the head (1A) is at the entry point of the tape (2) at the time of pulse Pr. The rotation phases of the heads (1A) and (1B) are controlled as shown.

Therefore, the head (1A) is taped (2) during the period T ₁ of the period Ta.
And the head (1B) scans the tape (2) during the period T ₁ of the period Tb. Therefore, as shown in FIG.
Is a magnetic track whose one block is diagonal (3)
Are sequentially recorded as.

Further, the pulse Pr from the control circuit (30) is applied to the recording amplifier (4
It is supplied to the magnetic head (44) through 3) and recorded on the edge of the tape (2) as a track (3C) for a control pulse at the time of reproduction as shown in FIG.

As described above, in the recording system of FIG. 1, the audio signal is
Sa is recorded in PCM.

On the other hand, in the reproducing system shown in FIG. 2, the head (42) reproduces the pulse Pr from the track (3C) of the tape (2), and the pulse Pr is supplied to the servo circuit (41), and the head (1A), (1B) is the same track as when recording (3)
Is servo controlled to scan. In this way, the signal Sc is taken out from the heads (1A) and (1B) every period T _{1 as} shown in FIG. 5F.

Then, when this signal Sc is supplied to the reproduction decoder (22) through the reproduction amplifier (21), the original PCM signal Sp is demodulated. That is, the signal Sc supplied to the decoder (22) is alternately written into the memory circuits (23A) and (23B) every block as shown in FIG. 5G, and as shown in FIG. 5H. The written signal Sc is alternately read at a speed half that at the time of writing, and accordingly, the PC expanded from the decoder (22) to the original time axis as shown in FIG. 5I.
The M signals Sp are continuously extracted.

At this time, an error check circuit (24) is connected to the decoder (22) to perform error check from the CRC and parity bit, etc., and error correction is performed based on the check result.

Then, this signal Sp is supplied to the error correction circuit (25) to correct the error that could not be corrected, and the error-corrected signal Sp is supplied to the D / A converter (26). It is converted into Sa and this signal Sa is taken out to the output terminal (27).

Even during this reproduction, the clock and the control signal are formed in the clock forming circuit (30) and the circuits (22) to (26) are formed.
At the same time, the pulse Pr from the head (42) is supplied to the forming circuit (30) as a signal indicating the start time of the period T ₁ in the period Ta.

As described above, in the tape recorder of FIGS. 1 and 2, the audio signal Sa is converted into PCM and recorded and reproduced, so that high-quality recording and reproduction can be performed.

By the way, in such a tape recorder, an error may occur in the PCM signal Sc (signal Sp) due to dropout during playback. At this time, if the error correction or error correction is not performed, the reproduced audio signal Sa It causes noise.

Therefore, the decoder (22) and the error correction circuit (25) of the reproduction system (FIG. 2) perform error correction and error correction. For the error correction, mean value interpolation, 3
There are methods such as next interpolation and previous value hold. The mean value interpolation and the cubic interpolation are quite effective methods because the detection limit frequency is high, but they cannot be used when there are continuous errors. Particularly, in the above-mentioned tape recorder, since the time axis of the audio signal Sa is compressed and recorded to about 1/2, the influence of the dropout is increased by the amount of the compression, and even more.

For this reason, correction (interpolation) by the previous value hold is performed for continuous errors, but since the detection limit frequency of the previous value hold is low, the number of continuous errors increases or the continuous errors increase significantly. If it becomes too long, it cannot be said to be an effective method and the sound quality will be deteriorated.

Further, as shown in FIG. 4, when the track (3) is formed obliquely, dust, scratches on the tape (2), and the like may extend over two or more tracks (3). When an error occurs in the signal Sc, it may occur over two blocks or more. In such a case, when the noise due to the error is muted because the error cannot be corrected or corrected, this becomes conspicuous.

The present invention seeks to be able to effectively correct large errors, even when they occur consecutively to the block of the signal Sc.

Therefore, considering the audio signal Sa, the audio signal Sa is a signal with a relatively large degree of redundancy and has a high correlation. And for a short time, when a part of the audio signal Sa is missing, if the waveform in the vicinity is fitted into the missing part, it will not cause much trouble to the auditory sense, and it is a very effective error correction method for large errors. It turned out to be

The present invention utilizes such a point to correct an error.

Let me explain one example below.

In FIG. 7, as shown in FIG. 6A, the signal Sc is continuously taken out from the amplifier (21) by one block in each period T _{1. In} order to distinguish these blocks, the following explanation will be given. In FIG. 6 and FIG. 6, the symbols from block to are added. Further, in FIG. 6, it is assumed that many errors occur in the blocks marked with a cross, and error correction and error correction cannot be performed.

The signal Sc from the amplifier (21) is sequentially supplied to delay circuits (51) and (52) composed of, for example, a memory, and the delay circuit (51) outputs, for example, one unit period as shown in FIG. 6B. The signal Sd delayed (1/60 seconds) is taken out, and the signal Se delayed from the signal Sd by, for example, one unit period is taken out from the delay circuit (52) as shown in FIG. 6C. Then, this signal Se is supplied to the decoder (22) through a switch circuit (53) described later.

In addition, the signal Sc from the amplifier (21) is supplied to the error check circuit (54) to check whether error correction and error correction are possible for each block of the signal Sc. , Flag Pd that becomes "1" if impossible
Is taken out. Therefore, in the signal Sc of FIG. 6A, it is impossible to perform error correction and error correction of blocks .about., And in this case, as shown in FIG. 6D,
During the period from block to block of the signal Sc, Pd = "1" (the flag is "0" at the end of 1 block,
Since it becomes "1", Pd = "1" until the block ends
Is).

Further, the signal Sd from the delay circuit (51) is supplied to the error check circuit (55) to extract the similar flag Pe,
That is, the flag Pe shown in FIG. 6E is taken out. Then, these flags Pd and Pe are supplied to the logic circuit (56) to extract the pulse Pf represented by Pf = Pd · Pe as shown in FIG. 6F, and this pulse Pf is supplied to the decoder (22) in the memory circuit. It is supplied as a write inhibit signal for (23A) and (23B).

Further, the signal Sd from the delay circuit (51) is changed to the switch circuit (5
6) from the logic circuit (56) while being supplied to
As shown in Fig. G, the pulse indicated by Pg = ▲ ▼ Pe
Pg is taken out and this pulse Pg (or pulse Pe) is supplied to the switch circuit (53) as a control signal, and the switch circuit (53) is connected to the state shown in the figure when Pg = “0”.

According to such a configuration, since Pg = “0” until time t ₂ , the switch circuit (53) is in the state shown in the figure, and the signal Se is supplied to the decoder (22). And until time t ₁ , Pf
= "0", so signal Se to memory circuits (23A) and (23B)
Is permitted to be written, and as shown in FIG. 6H, the signal Se
Are alternately written to the memory circuits (23A) and (23B) every block.

Then, at time t ₁ , since Pf = “1”, writing to the memory circuits (23A) and (23B) is prohibited, and accordingly, as shown by the broken line in FIG. Block ~ will not be written. That is, blocks with many errors are not written in the memory circuits (23A) and (23B).

Further, at time t ₂ , Pf = “0”, and after that, writing to the memory circuits (23A) and (23B) is permitted,
Since Pg = “1” in the periods t _{2 to} t ₃ , the switch circuit (53) is connected in the state opposite to that shown in the figure and the signal Sd is supplied to the decoder (22). Therefore, as shown in FIG. 6H,
Memory circuit (23A), with respect to (23B), block signal Sd is written in the period t ₂ ~t _3, time t ₃ after the signal Se
After the block of No. is written alternately.

The memory circuits (23A) and (23B) are shown in FIG.
Since blocks ~, ~ are written as shown in Fig. 6, the blocks read from the memory circuits (23A), (23B) are as shown in Fig. 6I. That is, the reading to the memory circuits (23A) and (23B) is
The writing is performed alternately using a period in which the writing is not performed, but since the blocks ~ have been written alternately before the time point t ₁ , they are read alternately.

However, since the period t ₁ ~t ₂ no writing is performed, the memory circuit (23A), is repeatedly read from the (23B) last written block, but alternately.

Then, the block is written in the period t _{2 to} t ₃ ,
After t ₃ , it is written sequentially from the block, so
The blocks are read out, and the blocks 1 to 3 are read out alternately.

Therefore, the blocks ~ are read from the memory circuits (23A) and (23B) as shown in Fig. 6I.
From the decoder (22), as shown in FIG.
Is taken out. Then, this signal Sp is supplied to the D / A converter (26) through the error correction circuit (25), and the audio signal Sa is reproduced.

In other words, among the signals Sc, the block with many errors ~ is not used for reproducing the audio signal Sa, and the blocks before and after that are used instead of the blocks with many errors ~ to reproduce the audio signal Sa. is there.

The PCM signal reproducing device of the present invention includes memory means 23A, 23B for temporarily holding data, and a decoding means 2 for decoding the reproduced PCM signal supplied to the memory means.
Since the decoding means controls the writing of the reproduction signal to the memory means, the PCM signal stored in the memory means is repeatedly decoded when an error is detected in the reproduction PCM signal. By doing so, it has an excellent feature that it is not necessary to provide a new memory means for holding the alternative data when an error is detected in the reproduced PCM signal.

[Brief description of drawings]

1 to 6 are diagrams for explaining the present invention, and FIG. 7 is a system diagram of an example of the present invention. (22) is a reproduction decoder, (23A) and (23B) are memory circuits, (51) and (52) are delay circuits, and (54) and (55) are error check circuits.

Front Page Continuation (72) Inventor Tadashi Fukami 1-7-4 Konan, Minato-ku, Tokyo Soni Co., Ltd. Shibaura Factory (56) References JP-A-55-14503 (JP, A)

Claims (1)

[Claims] 1. A delay means for delaying a reproduced PCM audio signal for a predetermined time, a memory means for temporarily holding data, and an error correction process for the reproduced PCM audio signal supplied to the memory means. Decoding means for applying and decoding, error correcting means for correcting an error which the output signal of the decoding means is unable to correct by the decoding means, and output signal of the error correcting means for supplying analog audio D / A converting means for generating a signal, and error checking means for checking whether the reproduced PCM audio signal can be corrected by the decoding means in units of blocks and whether the error correction means can correct the error. The playback PCM audio signal is provided by the error checking means. When an error that cannot be corrected or corrected is detected, the writing of data to the memory means is prohibited, and the data held in the memory means is supplied to the error correction means, whereby the error in the decoding means A PCM signal reproducing device characterized by being able to deal with errors that cannot be corrected and cannot be corrected.