JPH07111312A - Semiconductor capacitive element - Google Patents

Abstract

PURPOSE:To make the capacitance higher without increasing the occupied area of a semiconductor chip and also without increasing the size of an element. CONSTITUTION:A groove M, reaching a diffusion region 2 from a lower conductive film 4, is formed, the surface of the groove is covered by an insulating film 10 to be used for a capacitor, and a capacitor structure, in which the lower conductive film 4 is pinched by the upper conductive film 5 and the diffusion region 2, is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor capacitor element used in semiconductor devices, semiconductor integrated circuit devices and the like.

[0002]

2. Description of the Related Art Conventionally, in this type of semiconductor capacitor element, the structure shown in FIG. 6 has been used. In the figure, a capacitance in which a capacitor insulating film 24 covering the surface of the lower conductive film 23 is sandwiched by a lower conductive film 23 provided on the field oxide film 22 on the silicon substrate 21 and an upper conductive film 25 above it. It constitutes the element.

[0003]

However, since the element capacitance of the above structure is determined by the overlapping area of the capacitor insulating film 24 on the flat lower conductive film 23 with the upper conductive film 25, a large capacitance is obtained. In order to obtain the above, there is a problem that the area becomes large and the element size is expanded, or the area occupied by the capacitive element in the semiconductor chip becomes large.

Therefore, in order to expand this capacitance area, D
In a stack structure capacitor such as a RAM cell, a method of forming fine wrinkles on the surface layer of a polysilicon film has been proposed (see Japanese Patent Application Laid-Open No. 2-203557). According to this, after the polysilicon film is formed, microscopic unevenness is generated on the silicon surface by utilizing the interference fringes of light by the photoexcited CVD method. However, in this case, the surface area is increased only by forming the irregularities on the surface of the silicon film, and there is a limit to increase the capacity.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a semiconductor capacitive element capable of achieving a large capacity without increasing the element size.

[0006]

In order to achieve the above-mentioned object, the present invention forms a lower conductive film on a semiconductor substrate, and provides a diffusion region under the lower conductive film, and the lower conductive film is provided. A groove is formed by engraving the film and its diffusion region, the surface of the lower conductive film and the inner surface of the groove are covered with an insulating film for a capacitor, and an upper conductive film is provided on the insulating film for the capacitor. Is characterized by.

[0007]

According to the semiconductor capacitive element of the present invention, by forming the groove extending to the diffusion region, the capacitor insulating film formed on the surface of the groove is diffused through the upper conductive film and the lower conductive film. It is a capacitor structure sandwiched by a region, the upper conductive film serves as an upper electrode, and the diffusion region serves as a part of a lower electrode.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic sectional view showing a semiconductor capacitor element according to an embodiment of the present invention.

The field oxide film 3 on the silicon substrate 1,
The diffusion region 2 is formed between the regions 3. A lower conductive film 4 of polysilicon is formed on the diffusion region 2 and the field oxide film 3, and a plurality of trenches M reaching the inside of the diffusion region 2 are formed in the central portion thereof. The capacitor insulating film 10 covers the surfaces of the groove M and the lower conductive film 4.
Are formed. A high dielectric material such as a silicon nitride (Si ₃ N ₄ ) film or a tantalum oxide (Ta ₂ O ₅ ) film is used as the capacitor insulating film 10. An upper conductive film 5 made of polysilicon is laminated on the surface of the capacitor insulating film 10 so as to be buried in the groove M. The upper conductive film 5 and the lower conductive film 4 are covered with an interlayer film of a silicon oxide film 6, and are connected to aluminum external electrodes 7 and 8 through holes provided at predetermined positions of the oxide film, respectively. The external electrodes 7 and 8 correspond to the upper electrode and the lower electrode, respectively. The upper conductive film 5 and the external electrode 7 may be integrally formed of an aluminum layer without using a polysilicon film.

In the above structure, the insulating film for a capacitor 1
0 is the upper conductive film 5 and the lower conductive film 4 via the diffusion region 2.
Since a plurality of trenches M extend inside the diffusion region 2, the capacitor insulating film 10 is thinly formed on the inner surface of the trench M extending over the lower conductive film 4 and the diffusion region 2. By forming it, a sufficient capacitor area for high capacity can be obtained.

Next, a method of manufacturing the capacitive element of the above embodiment will be described with reference to FIGS. First, a field oxide film 3 is formed on the main surface of the N-type silicon substrate 1 together with gate oxidation.
Are formed by thermal diffusion, and the gate oxide region (not shown) is removed by etching to form an active region B (FIG. 2). An N-type silicon substrate having an N-type well region formed in the surface layer may be used as the substrate material in the present invention. Then active area B
The polysilicon lower conductive film 4 is formed by the CVD method so that the surface of the is not oxidized (FIG. 2). The polysilicon film 4 has a thickness of about 4500 angstroms, which reduces the film resistance value and reduces the active region B.
Contains phosphorus (P) for forming the diffusion region 2. P in the polysilicon lower conductive film 4 is 900 to 950.
The N ⁺ -type diffusion region 2 having a diffusion depth of about 0.5 to 0.6 μm is formed by thermal diffusion at a high temperature of ℃ (FIG. 3).

After the above phosphorus (P) diffusion, the lower conductive film 4
Patterning of the polysilicon layer is performed. A resist film 11 is formed on the film, and an opening A for forming the groove M is formed by patterning (FIG. 3). Using the resist film 11 as a mask, the insides of the lower conductive film 4 and the diffusion region 2 are etched to etch a plurality of grooves M (FIG. 4). Diffusion area 2
Inside, etching may be performed up to about 0.3 to 0.4 μm from the substrate surface.

The surface of the lower conductive film 4 in which the groove M is formed and the surface of the diffusion region 2 are silicon nitride (Si ₃
An N ₄ ) film insulating film 10 for capacitors is formed (FIG. 5). The silicon nitride film is formed so as to cover the surface of the lower conductive film 4 and the inner surface of the groove M. Since the surface of the polysilicon film of the lower conductive film 4 is oxidized during the formation of the capacitor insulating film 10, the insulating film 10 is finely turned on (Oxide).
-Nitride) It becomes a laminated structure. After the silicon nitride film is formed, the film surface is oxidized to turn ONO (Oxide-Nitride-Oxi).
de) With the laminated structure, it is possible to obtain an element having excellent withstand voltage without current leakage.

Further, a polysilicon film for forming the upper conductive film 5 is laminated (FIG. 5). Also in this case, phosphorus (P)
To reduce the film resistance value. Then, an external electrode is formed. Similar to the formation of a normal semiconductor element, an inter-layer silicon oxide film 6 is formed, and contact holes are formed in the lower conductive film 4 and the upper conductive film 5,
The aluminum outer electrodes 7 and 8 are formed (see FIG. 1).

[0016]

According to the present invention, since the inner surface of the groove reaching the inside of the diffusion region is used as the capacitor area as compared with the case where the surface of the lower conductive film is simply processed to have unevenness, a larger capacitance can be obtained without increasing the element area. Can be realized.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a semiconductor capacitor element which is an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a step of forming an active region of the capacitive element of the above embodiment.

FIG. 3 is a schematic cross-sectional view showing the patterning process of the lower electrode film of the capacitive element of the above embodiment.

FIG. 4 is a schematic cross-sectional view showing a groove forming step of the capacitive element of the above embodiment.

FIG. 5 is a schematic cross-sectional view showing a step of forming an insulating film for a capacitor of the capacitive element of the above embodiment.

FIG. 6 is a schematic cross-sectional view showing the structure of a conventional semiconductor capacitive element.

[Explanation of symbols]

 1 Substrate 2 Diffusion Region 4 Lower Conductive Film 5 Upper Conductive Film 10 Capacitor Insulating Film M Groove

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/108

Claims (1)

[Claims] 1. A lower conductive film is formed on a semiconductor substrate, a diffusion region is provided under the lower conductive film, and the lower conductive film and the diffusion region are engraved to form a groove. A semiconductor capacitor element, wherein a surface of the lower conductive film and an inner surface of the groove are covered with a capacitor insulating film, and an upper conductive film is provided on the capacitor insulating film.