JPH07109549B2 - Graphic processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic processing device, and more particularly to a process of updating data for one pixel, which can read a memory from a memory, update the data, and rewrite the data in the memory at substantially the same time. The present invention relates to an image processing apparatus suitable for improving the processing speed.

[0002]

2. Description of the Related Art Conventionally, one pixel per pixel has been used as a graphic processing apparatus which has realized a graphic processing function with an integrated circuit.
It has been known to process graphic display data of a single color represented by bits.

FIG. 1 is a block diagram showing an example in which such a conventional graphic processing apparatus is applied to multicolor or multi-gradation graphic processing.

In FIG. 1, 11 is a processing device, 12 is an address decoder, and 13 is a plurality of memories.

Here, the address signal AD output from one processing unit 11 is decoded by the address decoder 12,
A predetermined one of the plurality of display memories 13 is selected, and the data signal DT from the processing device 11 is written in the address of the memory 13 designated by the address signal AD.

When it is desired to rewrite the storage contents of a predetermined address of a predetermined memory 13, the address signal AD output from one processing unit 11 is decoded by the address decoder 12, and a plurality of predetermined display memories 13 are displayed. The data DT in the address designated by the processing device 11 is read into the processing device 11, the data is updated, and the data DT is written in the same address in the same memory 13 again.

Further, the address decoder 12 decodes the address signal AD output from one processing unit 11,
A predetermined one of the plurality of display memories 13 is selected, and the video signal V is generated based on the address signal AD from the processing device 11.
, DD ₂ , VD ₂ , ..., VD _n are obtained, and these are combined and displayed on a display device (not shown).

However, according to such a device,
In multi-color (n-color) or multi-gradation (n-gradation) processing, the same image processing is repeated n times, or 1 bit of 1
In order to display pixels, it was necessary to repeat image processing n times.

Therefore, there is a disadvantage that processing time is n times as long as that of the binary image processing.

Also, as shown in FIG. 2, a system has been proposed in which n display memories 13 are processed by one processing device 11 each.

According to such a system, the processing time is almost the same as in the case of the binary image, but there is a disadvantage that the apparatus becomes large and complicated and the load on the central processing unit increases. It was

Further, in the case of attempting to perform such processing by an integrated circuit, there is a disadvantage that the number of terminals is excessive and it is difficult to realize.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned inconvenient problems, and an object of the present invention is to provide a binary image even in the case of multi-color or multi-gradation in which one pixel is represented by a plurality of bits. To provide a graphic processing device capable of drawing at almost the same processing speed.

[0014]

SUMMARY OF THE INVENTION To achieve the above object, the present invention comprises:
A pixel address consisting of information designating the address of the display memory and the pixel position in the display data of one word in the display memory is sequentially calculated, and display is performed from the address information of the display memory at the calculated pixel address. A plurality of bit positions corresponding to designated pixel positions formed by reading one-word display data in the memory for reading and decoding the read display data based on the pixel position designation information at the pixel address. The drawing logical operation is performed only on the bits of a predetermined pixel of the display data, and the result of the logical operation is written again in the display memory.

Since the present invention is constructed as described above,
It can be drawn at the same processing speed as in the case of the value image.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings, but before that, the matters on which the present invention is based will be described.

The matters on which the present invention is based will be described below.

The present invention is as follows.

First, one pixel is represented by (a) one bit, (b) two bits are represented,
Five types of pixel modes can be selected, such as (c) 4-bit representation, (d) 8-bit representation, (e) 16-bit representation (see FIG. 9). .

Secondly, the pixel address is adopted. Therefore, this pixel address is composed of address information MAD that specifies the address of the display memory and in-word address information WAD that specifies which position in one word specified by the address. (See Figure 10).

Thirdly, the display data of one word at the display memory address specified by the address information in the pixel address is read out from the display memory and then specified by the in-word address information in the pixel address. Rewriting only a predetermined bit part in the display data and writing it again to the address part of the display memory, so that multiple bits of data for one pixel can be simultaneously processed. It is in. Next, examples of the present invention will be described.

Further, hereinafter, the same reference numerals denote the same objects.

FIG. 3 is a block diagram showing an example of an apparatus to which the graphic processing apparatus according to the present invention is applied.

In FIG. 3, the graphic processing device comprises an arithmetic unit 30 for controlling the writing, rewriting and reading of the display data in the display memory 13, and a control unit 20 for controlling the arithmetic unit 30 in a fixed order. It is configured. Further, the display data read from the display memory 13 by the graphic processing device is converted into a video signal by the display conversion device 40 and displayed on the display device 50.

The arithmetic unit 30 sequentially calculates a pixel address consisting of information designating the address of the display memory 13 and the pixel position in the display data of one word in the display memory 13, and the calculated pixel address is calculated. The display data of one word in the display memory 13 is read from the address information of the display memory 13 at the address, and the display data thus read is decoded based on the pixel position specifying information at the pixel address. With the information for designating a plurality of bit positions corresponding to the designated pixel position formed by the above, the drawing logic calculation is performed only on the bits of a predetermined pixel of the display data, and the result of the logical operation is written in the display memory 13 again. It was done.

Reference numeral 60 denotes an external computer, and the graphic processor operates according to control data from the external computer 60.

FIG. 4 is a block diagram showing an embodiment of the graphic processing apparatus according to the present invention.

In the figure, the control unit 20 includes a micro program memory 100, a micro program address register 110, and a return address register 120.
, A micro instruction register 130, a micro instruction decoder 200, a flag register 210, a pattern memory 220, and an instruction control register 230.

The arithmetic unit 30 is the arithmetic control unit 30.
0 and first-in first-out (First-In, First-Out (FIFO))
And a memory 400.

The respective constituent elements are used in ordinary digital control and need not be described in particular. However, according to this embodiment, the arithmetic and control unit 300 is divided into a logical address arithmetic unit (A unit) 310, a physical address arithmetic unit (B unit) 320, and a color data arithmetic unit (C unit) 330. ing.

The A unit 310 mainly calculates where the drawing point is on the screen according to the drawing algorithm, the B unit 320 calculates the necessary address of the display memory, and the C unit 330 writes it in the display memory. The color data is calculated.

FIG. 5 shows an example of the configuration of a display device which displays one pixel in 4 bits. The configuration in which the display data designated by the graphic processing device of FIG. 4 is displayed on the display device 50 is shown. It is shown.

In FIG. 5, D ₀ , D ₄ , D ₈ , D _{12 of} the display data DT read from the display memory 13 based on the address AD command from the graphic processor (FIG. 4).
Is a 4-bit parallel-serial converter 4 in the display converter 40.
Supplied to 10. Video signal AD from this converter 410
0 is obtained. _{Similarly, D 1, D 5, D} 9, D 13 and display converter parallel 40 of the display data DT - fed to serial converter 420, a video signal AD1 is obtained from the transducer 420 . D ₂ of the display data DT,
D ₆ , D ₁₀ , and D ₁₄ are supplied to the parallel-serial converter 430 in the display conversion device 40, and the video signal A is supplied from this converter 430.
D2 is obtained. _{Moreover, D 3, D 7, D} 11, D parallel ₁₅ display conversion device 40 of the display data DT - fed to serial converter 440, a video signal AD3 is obtained from the transducer 440. The video signals AD0 to AD3 are video interface circuits 450 that constitute the display conversion device 40.
To the display device 5 after undergoing processing such as color conversion and DA conversion.
It is displayed as 0.

Next, a specific configuration of each unit of the arithmetic and control unit 300 will be described with reference to FIGS. 6 to 8.

The logical address operation unit 310, which is the A unit in FIG. 6, is as shown in FIG. 4, and includes a FIFO buffer (FBUF) 3101 and a general-purpose register 3102.
, Area management registers 3103 and 3105, area judgment comparator 3104, end point register 3106, end judgment comparator 3107, and source latches 3108 and 31.
09, an arithmetic logic unit (ALU) 3110, a destination latch (DLA) 3111, a bus switch 3112, and a read bus (UBA, UBB) 31.
13 and 3114 and write bus (WBA) 3115
It has and.

In FIG. 7, the physical address operation unit 320, which is the B unit, is connected to the destination latch (D
LB) 3201, arithmetic operation unit (A) 3202, source latches 3203 and 3204, offset register 3205, screen width register 3206, command register 3207, general register 3208, read bus (UBB) 3209, Write bus (WBB) 321
It has 0 and. The general-purpose register 3208 is a current address register (DPH, DPL) for a pixel unit command.
And the word address command address register (RWPH, R
WPL) and work registers (T ₂ H, T ₂ L).

Further, in FIG. 8, the color data operation unit 330, which is a C unit, includes a barrel shifter 3301.
, Color register 3302, and mask register 330
3, a color comparator 3304, and a logical operator 3305
A write data buffer 3306, a pattern RAM buffer 3307, a pattern counter 3308, a pattern control register 3309, a read data buffer 3310, a memory address register 3311, a memory output bus 3312, and a memory input bus 3313. ing. The mask register 3303 is a register (C
MSK) and a register (GMSK).

The operation of the embodiment configured as described above will be described.

First, the basic operation of each element will be described. Control data CDT such as commands and parameters sent from another device such as a central processing unit is written to the memory 400 on the one hand and directly to the instruction control register 230 on the other hand.

The register 230 stores various graphic bit modes, and will be described later.
According to this embodiment, one of the five pixel modes can be selected. This selection is the usage data C
It can be done in DT.

The memory 400 is a so-called "First-In, Fi".
rst-Out ”(hereinafter also referred to as“ FIFO ”) memory, and the instruction stored in the memory 400 is read by the arithmetic control unit 300 and stored in a register in the arithmetic control unit 300. Further, one of the instruction information is stored. The copy CID is transferred to the address register 110.

The address register 110 manages the address of the microprogram memory 100, and this address is updated in synchronization with the clock. The address register 1
A micro instruction as shown in FIG. 13 is read from the micro program memory 100 in accordance with the address output from 10. The instruction read from the memory 100 is shown in FIG.
As shown in FIG. 3, it is made up of 48 bits, and the control modes # 0 to # 7 can be selected. Then,
The instruction is temporarily stored in the register 130, and the register 23
The arithmetic and control unit 3 generates a predetermined control signal CCS via the decoder 200 which operates according to the selected mode of 0.
Control each part of 00. Here, the function of each field of the micro instruction of FIG. 13 will be described.

In FIG. 13, "RU" is the UBA bus 3
This is an instruction to specify a register connected to 113.
“RV” is an instruction that specifies a register connected to the VBA bus 3114. “RW” is an instruction that specifies a register in which data on the WBA bus 3115 is written. “FUNCA” is the calculation logic calculator 311 of the A unit.
This is an instruction that specifies the operation of 0. “SFT” is an instruction to specify the shift mode of the shifter (SFTA) added to the lease latch 3108. “ADF-L” is an instruction to specify the lower 4 bits of the next address returned to the microprogram address register 110. “AC” is an instruction that controls the next address of a micro instruction. "A
DF-H "is the microprogram address register 11
This instruction specifies the upper 6 bits of the next address that is returned to 0. Further, the upper 6 bits of the address cannot be updated by each microinstruction # 4 to # 7. "FUNCB" is B
It is an instruction to specify the operation mode of the arithmetic operation unit 3202 of the unit. “ECD” is an instruction that specifies the execution condition of the operation. “BCD” is an instruction that specifies a branch condition. “FLAG” is an instruction that specifies the reflection of the flag in the flag register 210. “V” is the display memory 13
This is an instruction that specifies whether to test whether or not to access. “FIFO” is an instruction for controlling reading and writing to the FIFO 400. “LITERAL” is an instruction that specifies 8-bit literal data. “LC” is an instruction that specifies the generation mode of literal data. “FF” is an instruction to control the setting and resetting of special flip-flops of each part. “S” is an instruction that specifies selection of the code flag. “MC” is an instruction for controlling read / write of the display memory 13. “DR” is an instruction that controls the scanning of the pattern RAM.

"BC" is the arithmetic unit 320 of the B unit.
This is an instruction for controlling the input path to the input terminal 2. “RB” is an instruction to select the read / write register of the B unit. The micro-instruction has the above-mentioned instruction, whereby the control device 20 controls the arithmetic unit 30.

The return address register 120 stores the return address of the subroutine. Flag register 21
0 stores various condition flags. Pattern memory 22
0 stores a basic pattern used for graphic processing.

The operation of storing the image data in the memory will be described. Before that, the bit layout of each data used in this embodiment will be described.

First, the graphic mode will be described.

In this embodiment, the command control register 23
Five different operation modes can be selected according to the designation of the graphic bit mode (GBM) stored in 0.

FIG. 9 shows the bit configuration of one word of the display memory in each mode. (a). 1 bit / pixel mode (GBM = “000”) This is a mode used when expressing 1 pixel by 1 bit like a black and white image, and 1 word of the display memory has data of 16 consecutive pixels. Will be stored.

(B). 2-bit / pixel mode (GBM = 0
01) This expresses one pixel by 2 bits, and can be used for display of up to 4 colors or 4 gradations. Therefore, one word of the display memory 13 can store data of 8 consecutive pixels.

(C). 4-bit / pixel mode (GBM = 0
10) This expresses one pixel by 4 bits, and one word of data in the display memory can store continuous data of four pixels.

(D). 8-bit / pixel mode (GBM = 0
11) This expresses one pixel by 8 bits, and one word of the display memory can store data for two pixels.

(E). 16 bits / pixel mode (GBM =
100) This represents one pixel with 16 bits, and one word in the display memory corresponds to one pixel data.

Next, the pixel address will be described.

FIG. 10 explains the pixel address corresponding to each mode of FIG. The register 3208 of the physical address calculation unit manages a bit address (physical address) WAD in which 4 bits are added to the lower order of the memory address. The lower 4-bit information WAD is used to specify the pixel position within one word, and operates according to each bit / pixel mode. In the figure, "*" indicates a bit unrelated to the operation.

FIG. 11 shows the spatial arrangement of the display memory by taking the "4 bit / pixel mode" of the item (c) as an example. The memory address is given as a linear address as shown in the memory map of FIG. (A), and this is displayed as a two-dimensional image as shown in FIG. (B). The horizontal axis of the screen is the screen width register (MW) 3 in FIG.
Stored in 206, this MW indicates how many bits the horizontal width of the screen is composed of. Therefore,
In the 4-bit / pixel mode, MW / 4 pixels are displayed in the horizontal direction. Since one pixel is displayed with 4 bits, in the case of 1-word data, FIG.
As shown in, the data is displayed as data for four pixels continuous in the horizontal direction. In the offset generation circuit 2001 of FIG. 7, "4" is generated as an offset value and stored in the offset register. Therefore, it is understood that the offset value may be added or subtracted to move the physical address by one pixel in the horizontal direction. Further, in order to move one pixel in the vertical direction, the value of the register (MW) 3206 may be added or subtracted.

The example of the bit layout of the data used in this embodiment has been described above.

Next, the operation of storing image data in the display memory 13 using these data will be described.

On the other hand, the control data CDT such as commands and parameters sent from the external central processing unit is stored in the memory 4 on the other hand.
00, while on the other hand the instruction control register
Written in 230.

Here, the graphic bit mode (GBM) stored and designated in the instruction control register 230 is
For example, a case of 4-bit / 1-pixel mode (GBM = 010) will be described.

When the graphic bit mode (GBM) is designated as 4 bits / 1 pixel by the instruction control register 230, the data of one word in the display memory 13 is divided into 4 bits as shown in FIG. Will be treated as if it were

CDTs such as commands and parameters from an external central processing unit are stored in the memory 400 one after another. The data stored in the memory 400 is transferred to the FI of the A unit 310.
It is taken into the FO buffer 3101. The operation of the A unit 310 will be described below. This FIFO buffer 310
The data taken in 1 is exchanged with the internal bus 3113 and stored in the necessary registers. This is input from the bus to the logical operation unit 3110 via the lease latch 3109, a predetermined operation is performed, and the result is stored in the temporary destination latch (DLA) 3111. The result is stored in the general register 3102. This general-purpose register 3102 stores the current coordinate point in the meter coordinate space of the parameter.

Current XY in general register 3102
Coordinates are read from either of the read buses 3113 and 3114 and input to the calculated width current arithmetic unit (ALu) 3110. The result calculated by the calculator (ALu) 3110 is the destination latch (DLA) 3
111, general-purpose register 3 via write bus 3115
It is stored again in 102. These series of operations are executed according to the instructions of the microprogram shown in FIG.

The data on the write bus 3115 is input to the area management registers 3103 and 3105. The data input to the area management registers 3103 and 3105 are compared by the area determination comparator 3104. From these data, in the comparator 3104, the minimum value on the X axis or X
Whether the maximum value of the axis, the minimum value of the Y axis, or the maximum value of the Y axis is determined, and the determination result is sent to the flag register 210.

Further, the data on the write bus 3115 is stored in the end point register 3106, and is input to the end determination comparator 3107 via this. Completion judgment comparator 31
In 07, the end points of the X-axis and the Y-axis stored in advance in the comparator 3107 are compared with the above data, and it is detected whether or not the end point and the above data match. The comparison detection result is reflected in the flag register 210.

As mentioned above, the comparators 3104 and 310.
7. The result of the arithmetic unit 3110 is collected in the flag register 210 and input to the micro instruction decoder 200,
It will be used to change the flow of microprograms.

As described above, the A unit 310 operates, decodes the XY coordinate values given by the parameters,
Each interprets commands such as drawing a line or writing a circle.

Next, the operation of the B unit 320 will be described.

The data interpreted by the A unit 310 is input to the register 3208. The data of the register 3208 is input to the arithmetic unit (ALL) 3202 via the read bus 3209 and the lease latch 3204. The result calculated by the calculator 3202 is temporarily stored in the destination latch 3201 and is stored in each of the buses 3113, 3
114, 3209 and 3210. Here, it is written in the register 3208 via the bus 3210. The register 3208 consists of two 16-bit 1-word registers, and a total of 32 bits 1-word.
Store physical address in words. The register 3208 has three types of the 32-bit registers and can store three types of data. That is, the register DP of the register 3208 stores the physical address of the actual drawing point corresponding to the current drawing point XY. Then, when the XY coordinates of the register 3102 of the A unit 310 moves, the physical address of the register DP moves correspondingly.

To change the physical address, a predetermined value that can be variably set to the original physical address in the X-axis direction is used.
(Offset value x value up to point to move) may be added or subtracted, and a predetermined value may be added or subtracted in the Y-axis direction. That is, a constant for moving the pixel address by one pixel in the horizontal direction is set in the offset register 3205 based on the image mode designated by the register 2001. The moving physical address in the horizontal direction is calculated by calculating the constant and the data in the calculator 3202. For example, when the pixel mode is "1 bit / pixel mode", the constant is 1, and when the pixel is moved by 1 pixel, it is shifted by 1 bit. When this is the "4 bits / pixel mode", the constant is 4, and when moved by 1 pixel, it shifts by 4 bits.

Further, in order to move vertically by one pixel, it is possible to move by one pixel if calculation is performed using a constant set in the screen width register 3206. Of course, for example, in order to move by 4 pixels, if 4 bits are added, it will move by that amount.

The B unit 320 operates as described above to obtain the actual physical address corresponding to the XY coordinates determined by the A unit 310.

Finally, the operation of the C unit 330 will be described.

The C unit 330 has an output bus 3312 and an input bus 3313 with respect to the display memory 13 shown in FIG.
Connected with. C unit on output bus 3312
The address information AD is first output from the 330, and then the data DT is output.

First, the address information AD is stored in the B unit 32.
It is written in the memory address register 3311 via 0 and via the UBB bus 3209, and is stored in (MALL) and (MARH) of the memory address register 3311. When the memory address stored in the register 3311 is sent to the display memory 13 via the output bus 3312, the display data DT of the designated one word in the memory 13 is sent from the display memory 13 via the input bus 3313. Is read. The read display data DT is stored in the read data buffer 3310. Here, when the display data DT draws a figure, it is input to the calculator 3305.

Next, the mask information (information designating which bit of one word is masked) from the mask register 3303 is input to the arithmetic unit 3305. The mask information is a register (CMSK) directly written from the WBB bus 3201 or the address decoder 20 within one word.
A register (G
MSK).

In addition, color information is stored in the color register 3302.
And gives it to the calculator 3305. And the arithmetic unit 3
At 305, a logical operation is performed based on the data DT, mask information and color information, and the operation result is output to the write register 3306. The color information and the pattern information are specified by the address signal formed by the pattern counter 3308 and the drawing pattern register 3309, so that the pattern RAM 220 changes the pattern RA to the pattern RA.
It is stored in the M buffer 3307. This can be taken into the color register 3300, or directly operated by the arithmetic unit 3305.
To enter.

In this way, the C unit 330 operates to perform conversion processing on color information.

Next, a method of drawing calculation will be described. FIG. 12 schematically shows the flow of the drawing calculation for one pixel in the 4-bit / pixel mode.

The drawing color data (C0, C1) is read from the pattern RAM 220 at the addresses designated by the drawing pattern register 3309 and the pattern register 3308 and stored in the color register 3302 via the pattern RAM buffer 3307. The data (C _a , C _b , C _c , C _d ) read from the display memory 13 is stored in the read data buffer 3310. The color data and the data are 4-bit color information or gradation information. 1-bit pattern information is read out from the pattern memory 220, and the color register 0 or the color register 1 is selected according to "0" or "1" of the data and supplied to the logical operation unit 3305. The lower 4 bits of the physical address information stored in the memory address register 3311 are “10 *” in the figure.
This is "*", and this information is obtained in the intra-word address decoder 2002 and the mask information GM is obtained by the master register 3303.
Generate SK. On the other hand, the memory address register 3311
The upper field except the lower 4 bits is output as a display memory address and one word of the display memory 13 is read. In the logical operation unit 3305, the mask register 330
The logical operation is performed only on the portion designated by the "1" bit of GMSK 3 to obtain write data Cy, and the write data Cy is stored in the write buffer 3306. Here, the computing unit 3305
The types of the logical operation of (1) include rewriting to the value of the color register, logical operation (AND, OR, EOR), and conditional drawing (drawing only when the read color satisfies a predetermined condition). When the bit / pixel mode is another mode, the same operation is performed except that the generated GMSK information is different. Then, the address information AD and the data DT are again sent in order from the address register 3311 and the register 3306 to the output bus 33312 and written in a predetermined address of the display memory 13.

As described above, according to this embodiment, the data for one pixel can be updated at one time by one read, update, and write processing, so that drawing with high processing efficiency can be performed. Further, even in cases other than the 16-bit / pixel mode, the data of a plurality of pixels is packed into the 16-bit length and processed, so that the memory usage efficiency is good and the data transfer efficiency between other devices and the display memory is also good. Further, in the present embodiment, the operation modes are provided for five types having different bit lengths per pixel, so that the configuration is highly versatile.

[0082]

As described above in detail, according to the present invention, one read, update, and write processing is performed.
Since all data for pixels can be changed, there is an effect that the drawing process can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional graphic processing device.

FIG. 2 is a block diagram showing a conventional graphic processing device.

FIG. 3 is a block diagram showing an apparatus to which the graphic processing apparatus according to the present invention is applied.

FIG. 4 is a block diagram showing an embodiment of a graphic processing device according to the present invention.

FIG. 5 is a block diagram showing a display device to which the embodiment is applied.

6 is a block diagram showing details of the graphic processing device of FIG. 4;

FIG. 7 is a block diagram showing details of the graphic processing device of FIG. 4;

8 is a block diagram showing details of the graphic processing device in FIG. 4;

FIG. 9 is an explanatory diagram showing a bit layout of display data used in the embodiment.

FIG. 10 is an explanatory diagram showing a bit layout of pixel addresses used in the embodiment.

FIG. 11 is a block diagram showing a configuration between an image memory and a display device.

FIG. 12 is an explanatory diagram shown for explaining a drawing calculation operation of the embodiment.

FIG. 13 is an explanatory diagram showing a format of a macro instruction used in the same embodiment.

[Explanation of symbols]

20 ... Control device, 30 ... Arithmetic device, 300 ... Arithmetic control device, 310 ... Logical address arithmetic unit, 320 ... Physical address arithmetic unit, 330 ... Color data arithmetic unit, 2002 ... Intra-word address decoder.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location G06T 1/00 1/60 (72) Inventor Hisashi Kajiwara 3-2-1, Saiwaicho, Hitachi, Ibaraki (56) Reference JP-A-56-31154 (JP, A) JP-A-57-53784 (JP, A) JP-A-58-187995 (JP, A) JP-A-53 -29033 (JP, A) JP-A-57-127980 (JP, A)

Claims (16)

[Claims] 1. A plurality of pixel data are included in one word, and 1
The one pixel data is composed of a plurality of bits, and the pixel data is image data accessed in units of one word, and a graphic processor for accessing the memory means for holding the image data to process the image data.
A support, and a register means for holding a plurality of pixel data, supplied from the outside, at least representative of the shape of the display image 1
Depending on the content of the pattern data composed of bits,
A graphic comprising selection means for selecting pixel data held in the register means, and writing means for writing the selected pixel data in the memory means .
Processor. 2. The graphic processor according to claim 1, wherein the pattern data is held in a pattern memory . 3. The graphic processor according to claim 2, wherein the pattern memory is included in the graphic processor.
Sa. 4. The pixel data stored in the selected register according to claim 1, wherein the register means is composed of a plurality of registers, and the selection means selects from the plurality of registers. graphics professionals and outputting to the writing means
Sessa. 5. A plurality of pixel data are included in one word and 1
The one pixel data is composed of a plurality of bits, and the pixel data is image data accessed in units of one word, and a graphic processor for accessing the memory means for holding the image data to process the image data.
A support, and a register means for holding a plurality of pixel data, supplied from the outside, at least representative of the shape of the display image 1
Depending on the content of the pattern data composed of bits,
Selecting means for selecting the pixel data held in the register means; reading means for reading the pixel data held in the memory means at a specified address; and the selected pixel data and the read pixel data A graphic processor comprising: a logical operation means for performing a logical operation from the above and a writing means for writing the logically operated pixel data at a specified address of the memory means . 6. The graphic processor according to claim 5, wherein the pattern data is held in a pattern memory . 7. The graphic processor according to claim 5, wherein the pattern memory is included in the graphic processor.
Sa. 8. The pixel data stored in the selected register according to claim 5, wherein the register means is composed of a plurality of registers, and the selection means selects from the plurality of registers. graphics professionals and outputting to the writing means
Sessa. 9. The replacement operation according to claim 5, wherein the logical operation replaces the read pixel data with the selected pixel data, and AND
Operation, OR operation, EOR operations, Gras the read pixel data and executes at least one operation of the conditional operation for performing an operation when a predetermined condition is satisfied
Fick processor. 10. The memory device according to claim 5, wherein the read means specifies a memory address for specifying one word of the image data stored in the memory means, and a pixel data position within the one word specified by the memory address. Has a physical address processing means for generating a physical address from a pixel address for specifying the pixel address, and reads one word including the pixel data to be read by the memory address from the memory means, and obtains the pixel data to be read by the pixel address. A graphic processor characterized by specifying . 11. The read means according to claim 9 or 10, wherein in order to specify the pixel data to be read by the pixel address, the reading means generates mask information for extracting only pixel data to be read based on the pixel address. A graphic processor , wherein the generated mask information and the read-out one-word pixel data are masked . 12. The graphic processor according to claim 11, further comprising pixel data bit number designating means for setting the number of bits constituting one pixel, and the mask information is generated based on the set number of bits. A graphic processor characterized by . 13. The read / write means according to claim 5, wherein the read / write means is a common I / O.
A graphic that features control through a buffer
Processor. 14. A plurality of pixel data are included in one word,
One piece of the pixel data is composed of a plurality of bits, and the pixel data is image data accessed in units of one word, and a graphic processor for accessing the memory means for holding the image data to process the image data.
A Tsu Sa, the pixel data is an image data indicating a data value representing the gray level or color, a pattern data composed of at least one bit that represents the shape of the display image, based on the pattern data A first register and a second register respectively holding the first data value and the second data value corresponding to the first shape value and the second shape value, and a shape value based on the pattern data. The first register or the second register is selected accordingly, and the data value held in the selected register is expanded as pixel data expanded from the pattern data. Graphics processor. 15. The graphic processor according to claim 14, wherein each of the registers holds a plurality of pixel data . 16. The expansion means according to claim 14, wherein the plurality of pixel data are composed of a plurality of bits.
Image data composed of multiple pixel data
A graphic processor that is characterized by the extension.