JPH07106973A - Converter - Google Patents

Abstract

PURPOSE:To provide a converter which has a small chip area and the facilitated designing of layout. CONSTITUTION:Four MOS transistors TR 2, 3, 4 and 5 of the same layout are provided on the same substrate 1, and a polycrystalline silicon layer 15 is formed under a TR 2-5 within the substrate 1. At the same time, the voltage of a prescribed level is applied to the layer 15. Thus the threshold voltage Vt of those TR 2-5 are continuously controlled. Then the analog signals are supplied to the gate terminals of the TR 2-5 respectively. These analog signals are turned into the digital signals by the ON/OFF states of TR 2-5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a converter, and more particularly to a converter that can be used as a flash type A / D converter or the like.

[0002]

2. Description of the Related Art Conventionally, the L / W of a transistor has been changed in order to change the threshold voltage Vt of a flash type inverter using CMOS (eg, 1992 Spring Meeting of the Institute of Electronics, Information and Communication Engineers, C-60
8. "AD converter with CMOS inverter as basic component").

[0003]

However, in order to arrange a large number of transistors having different L / W on the same substrate, the layout design becomes complicated. Further, in order to arrange a large number of transistors having different L / W on the same substrate, it is necessary to match the minimum transistor with the minimum rule, and in order to arrange a transistor of a larger size, the chip area is large. There was a problem of becoming.

Therefore, an object of the present invention is to provide a converter whose layout design is easy and whose chip area is small.

[0005]

According to a first aspect of the present invention, a plurality of MOS transistors having the same layout are arranged on the same substrate, and a conductive layer is extended below each of the MOS transistors in the substrate. A threshold voltage of each MOS transistor is continuously controlled by applying a predetermined voltage to the gate terminal, and an analog signal is input to the gate terminal of each MOS transistor and digitized by the ON / OFF state of each MOS transistor. The converter which was made into is the gist.

According to a second aspect of the present invention, a plurality of sets of MOS transistors having the same layout and CMOS inverter structure are arranged on the same substrate, and the CMOS in the substrate is arranged.
A conductive layer is provided below each MOS transistor of the inverter structure, and a threshold voltage of each MOS transistor of the CMOS inverter structure is continuously controlled by applying a predetermined voltage to the conductive layer. The gist of the present invention is a converter which inputs an analog signal to the gate terminal and digitizes it by turning on / off each of the MOS transistors.

[0007]

According to the invention of claim 1, the substrate potential is continuously controlled by applying a predetermined voltage to the conductive layer to continuously control the threshold voltage of each MOS transistor. And
An analog signal is input to the gate terminal of each MOS transistor and digitized by the ON / OFF state of each MOS transistor. Therefore, since the MOS transistors having the same layout can be arranged on the same substrate, the layout design can be facilitated, and the MOS transistors having the same layout can be adjusted to the minimum rule, and the chip area can be reduced.

According to a second aspect of the present invention, the substrate potential is continuously controlled by applying a predetermined voltage to the conductive layer, and the CMO is obtained.
The threshold voltage of each MOS transistor of the S inverter structure is continuously controlled. Then, an analog signal is input to the gate terminal of each MOS transistor and digitized by the ON / OFF state of each MOS transistor. Therefore, since the MOS transistors having the same layout can be arranged on the same substrate, the layout design can be facilitated, and the MOS transistors having the same layout can be adjusted to the minimum rule, and the chip area can be reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment embodying the present invention will be described below with reference to the drawings.

An example in which a MOS transistor using a thin film SOI structure is applied to a 2-bit analog-digital converter is shown below. FIG. 1 shows the electrical configuration and FIG.
2 shows a plan view of the substrate, and FIG. 3 shows a sectional view taken along line AA of FIG.

As shown in FIG. 3, four NMOS transistors 2, 3, 4, 5 having the same layout are arranged in a horizontal row on the substrate 1. That is, four thin film silicon layers (thin film SOI) 6, 7, 8, 9 are arranged on the surface of the substrate 1, and gate oxide films 10, 11, 12 are formed on the thin film silicon layers 6, 7, 8, 9. , 13, a common gate electrode 14 common to each transistor is extended. or,
The NMOS transistors 2, 3, 4, and 5 are arranged at equal intervals.

Further, below the NMOS transistors 2, 3, 4, 5 in the substrate 1, a polycrystalline silicon layer 15 as a conductive layer is extended. One end of the polycrystalline silicon layer 15 has a thin film silicon layer (thin film SOI) 16
And a thin film silicon layer (thin film S
OI) 17 is connected. Also, the thin film silicon layer 16
Is connected to the aluminum electrode 18, and the thin film silicon layer 17 is connected to the aluminum electrode 19.

The surface of the substrate 1 is covered with a BPSG film 20. In order to fix the substrate potential of the NMOS transistors 2, 3, 4, 5 to the aluminum electrodes 18 and 19, the aluminum electrode 18 is set to the ground potential, and the aluminum electrode 19 is connected to the bias power source 21 (see FIG. 1). ing. In this embodiment, the bias power supply 21 is a constant power supply of -6 volts.

Then, each NMOS transistor 2, 3,
The substrate potentials of 4 and 5 are fixed to potentials proportional to the distance, as shown in FIG. On the other hand, the threshold voltage Vt of each NMOS transistor 2, 3, 4, 5 is, as shown in FIG.
It changes linearly with the substrate potential. At this time, the transistors are arranged so that the distances between adjacent transistors are equal, and the differences in threshold voltage Vt between adjacent transistors are equal. In this state, if an analog signal is applied to the common gate electrode 14 of each of the NMOS transistors 2, 3, 4, 5 then each of the NMOS transistors 2, 3, 4, 5
As shown in Table 1, each NMOS transistor 2, 3,
Depending on the threshold voltage Vt of 4, 5 and the input voltage Vin, it is turned on at any time and outputs a digital value for the input signal.

[0015]

[Table 1]

By using this configuration as described above, it can be used as a flash type A / D converter. Next, a method of manufacturing the analog-digital converter thus configured will be described. The analog-digital converter of this embodiment is manufactured by using the laminating method. The explanation of the manufacturing process is
It is assumed that the region shown by B in FIG.

First, as shown in FIG. 6, a single crystal silicon substrate 24 is prepared, and a pad oxide film 25 is formed on the entire surface thereof. Further, a nitride film 26 is formed on the entire surface of the pad oxide film 25. Then, the nitride film 26 is patterned with a mirror inversion pattern of a silicon region (SOI region) 27 of an element to be formed later, and a region 28 to be a field portion is formed.
The nitride film of is removed.

Then, as shown in FIG. 7, thermal oxidation is performed by the LOCOS method so that the film thickness of the oxide film 29 of the field portion 28 becomes, for example, about 600 nm. Next, as shown in FIG. 8, after removing the nitride film 26 and the pad oxide film 25, the entire surface is thermally oxidized to form a silicon region (SOI region) 27.
An oxide film 30 having a thickness of, for example, about 300 nm is formed thereon.

Further, as shown in FIG. 9, after the oxide film 30 is patterned for forming a contact hole, it is etched by, for example, a reactive ion etching method to form a contact hole 31.

Next, as shown in FIG. 10, polycrystalline silicon 32 is deposited on the entire surface of the silicon substrate 24. The polycrystalline silicon 32 is non-dove or N ⁻ . Then, as shown in FIG. 11, after patterning the polycrystalline silicon 32 in a desired region and etching the polycrystalline silicon 32, a film having a thickness of about 1 is formed on the surface of the polycrystalline silicon 32 by, for example, a thermal oxidation method.
An oxide film 33 of 00 nm is formed. Further, as shown in FIG. 12, the thick film polycrystalline silicon 34 is transferred to the silicon substrate 24.
About 5 μm is deposited on the upper surface, and the surface of the thick film polycrystalline silicon layer 34 is flattened and polished as shown in FIG.

Next, as shown in FIG. 14, the mirror surface 35a of the single crystal silicon substrate 35 and the polishing surface 34a of the polycrystalline silicon 34 are brought into contact with each other, for example, 1100 in a nitrogen atmosphere.
Heat treatment is performed at 1 ° C. for 1 hour to directly bond and integrate the two substrates. Then, as shown in FIG. 15, the field oxide film 29 is selectively polished from the back surface side of the single crystal silicon substrate 24 as a polishing stopper, and the thin film silicon layer (thin film SO
I region) 36 is formed. Finally, after adjusting the SOI film thickness,
As shown in FIG. 3, a gate electrode is formed on the thin film silicon layer (thin film SOI region) 36, a source / drain region is formed, and an interlayer insulating film is formed by a normal MOSIC process.
The element is completed by forming metal electrodes.

As described above, in this embodiment, as shown in FIGS. 1 to 3, four MOSs having the same layout on the same substrate 1 are used.
The transistors 2, 3, 4, and 5 are arranged, and the polycrystalline silicon layer 15 (conductive layer) is extended below the MOS transistors 2, 3, 4, and 5 in the substrate 1 to form the polycrystalline silicon layer 15. By applying a predetermined voltage, each M
The threshold voltage Vt of the OS transistors 2, 3, 4, 5 is continuously controlled, an analog signal is input to the gate terminals of the respective MOS transistors 2, 3, 4, 5 and the respective MOS transistors 2, 3, 4, 5 are inputted. It was made to digitize by the on / off state of.

Therefore, when the threshold voltage Vt is changed by changing the L / W of the conventional transistor, the layout design becomes complicated if a large number of transistors having different L / W are arranged in the same substrate. Alternatively, it is necessary to match the minimum transistor with the minimum rule, and there is a problem that the chip area becomes large in order to arrange a transistor of a larger size. However, in the present embodiment, since the MOS transistors 2, 3, 4, 5 having the same layout can be arranged on the same substrate 1, the layout design is facilitated and the MOS transistors 2, 3, 4, 5 having the same layout are arranged. The chip area can be small because it can meet the minimum rules. (Second Embodiment) Next, the second embodiment will be described focusing on the differences from the first embodiment.

In the first embodiment, the thin film SOI structure is formed by the bonding method of two substrates, but in this embodiment, the structure shown in FIG.
As shown in FIG. 6, a thin film SOI structure is formed by an insulating layer burying method using SIMOX.

The manufacturing method will be described below. Shown in Figure 17
So that the N of about 10-50 μm^-(10¹⁶cm^-3Since
Bottom) P with epi layer 37⁺(10¹³cm^-3) Epitachy
A chart board 38 is prepared, and as shown in FIG.
Separation P⁺Boron is added to the region forming part at 150 keV, 1
× 10 ¹⁶cm^-2With resist 39 as a mask
To enter.

Next, as shown in FIG. 19, in order to form a separation layer of an oxide film, 150 KeV and 1.3 are formed on the entire surface of the wafer.
Oxygen ions are implanted at × 10 ¹⁸ cm ^-2 . After that, FIG.
1300 to activate the isolation layer as shown in FIG.
Anneal at 6 ° C. for 6 hours. As a result, the P ⁺ diffusion layer 40 for element isolation, the SiO ₂ layer 41, the thin film silicon layer 42
Is formed. At this stage, the formation of the substrate electrode portion is completed.

Below, as shown in FIG. 21, a normal MO is used.
By performing the S process, LOCOS isolation is performed, a gate oxide film 43 is formed, and a gate polysilicon electrode 44 is further formed. Finally, as shown in FIG. 22, the through hole 45 for forming the substrate electrode is formed in the LOCOS.
After forming the oxide film by the method described above, ions are implanted into the source / drain regions, an interlayer insulating film is formed, and aluminum is further formed in the through holes 45 by vapor deposition.

As a result, as shown in FIG. 16, aluminum electrodes 46 and 47 are electrically connected to N ^- epi layer 37 as a conductive layer through N ⁺ diffusion layers 48 and 49. here,
The N ⁺ diffusion layers 48 and 49 are formed at the same time when the source / drain ions are implanted. (Third Embodiment) Next, a third embodiment will be described.

This embodiment is applied to a 2-bit analog-digital converter. 23 shows an electrical configuration, FIG. 24 shows a plan view of the substrate, and FIG.
4 is a sectional view taken along line CC of FIG. In the first and the examples, the substrate is S
Although it has an OI structure, as shown in FIG. 25, a bulk structure is adopted in this embodiment.

On the N type silicon substrate 50, the P well region 5 is formed.
1 is formed, and in the P well region 51, four NMOS transistors 52, 53, 54 and 55 having the same layout are arranged in a horizontal row. That is, the N-type silicon substrate 50
Four N-type diffusion layers 56, 57, 58 and 59 are formed on the surface of the
A common gate electrode 64 common to the respective transistors is provided on the gates 8 and 59 via gate oxide films 60, 61, 62 and 63. Here, the P well region 51 serves as a conductive layer for adjusting the threshold voltage Vt of each NMOS transistor 52, 53, 54, 55.

Aluminum electrodes 67, 6 are formed on both sides of the P well region 51 where the NMOS transistors 52, 53, 54, 55 are arranged via N-type diffusion layers 65, 66.
8 is electrically connected.

The aluminum electrode 67 is set to the ground potential, and the aluminum electrode 68 is connected to the bias power source 69 (see FIG. 23). In this embodiment, the bias power source 6
9 uses a constant power supply of -16 volts. At this time, the substrate potential of each of the NMOS transistors 52, 53, 54, 55 is fixed to a potential proportional to the distance as shown in FIG. On the other hand, the NMOS transistors 52 and 5
The threshold voltages Vt of 3, 54 and 55 are proportional to the square root of the substrate potential, as shown in FIG. At this time, the neighboring NM
The NMOS transistors 52, 53, 54 and 55 are arranged so that the threshold voltages Vt of the OS transistors are equal to each other (see FIGS. 24 and 25). In this state, NMO
When an analog signal is applied to the common gate electrode 64 of the S transistors 52, 53, 54, 55, each of the NMOS transistors 52, 53, 54, 55, as shown in Table 2,
The NMOS transistors 52, 53, 54 and 55 are turned on at any time according to the threshold voltage Vt and the input voltage Vin, and the digital value corresponding to the input signal is output.

[0033]

[Table 2]

With this configuration, it can be used as a flash type A / D converter. Further, it is also possible to use it as a non-linear converter if it is not arranged so that the difference between the threshold voltages Vt of the adjacent NMOS transistors 52, 53, 54 and 55 becomes equal. (Fourth Embodiment) Next, a fourth embodiment will be described.

Although only the NMOS alone is described in each of the above embodiments, the same can be applied to an inverter having a CMOS structure. In other words, CMs with the same layout on the same substrate
A plurality of sets of MOS transistors having an OS inverter structure are arranged, a conductive layer is extended below each MOS transistor having a CMOS inverter structure in the substrate, and a predetermined voltage is applied to the conductive layer, thereby each of the CMOS inverter structures is provided. The threshold voltage of the MOS transistor may be continuously controlled, an analog signal may be input to the gate terminal of each MOS transistor, and digitized by the ON / OFF state of each MOS transistor.

In this case, the substrate potential is continuously controlled by applying a predetermined voltage to the conductive layer, and the CM is
The threshold voltage of each MOS transistor of the OS inverter structure is continuously controlled. Then, an analog signal is input to the gate terminal of each MOS transistor and digitized by the ON / OFF state of each MOS transistor. Therefore, since the MOS transistors having the same layout can be arranged on the same substrate, the layout design can be facilitated, and the MOS transistors having the same layout can be adjusted to the minimum rule, and the chip area can be reduced.

[0037]

As described above in detail, according to the present invention,
The layout design is easy and the chip area can be reduced, which is an excellent effect.

[Brief description of drawings]

FIG. 1 is an electrical circuit diagram showing an electrical configuration of a first embodiment.

FIG. 2 is a plan view of the substrate of the first embodiment.

3 is a cross-sectional view taken along the line AA of FIG.

FIG. 4 is a characteristic diagram showing a relationship between a position of a transistor and a substrate potential.

FIG. 5 is a characteristic diagram showing a relationship between a substrate potential and a threshold voltage.

FIG. 6 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 7 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 8 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 9 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 10 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 11 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 12 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 13 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 14 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 15 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 16 is a sectional view of the second embodiment.

FIG. 17 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 18 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 19 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 20 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 21 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 22 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 23 is an electrical circuit diagram showing the electrical configuration of the third embodiment.

FIG. 24 is a plan view of the substrate of the third embodiment.

25 is a cross-sectional view taken along line CC of FIG.

FIG. 26 is a characteristic diagram showing the relationship between the position of a transistor and the substrate potential.

FIG. 27 is a characteristic diagram showing a relationship between a substrate potential and a threshold voltage.

[Explanation of symbols]

 1 Substrate 2, 3, 4, 5 NMOS Transistor 15 Polycrystalline Silicon Layer as Conductive Layer

Claims (2)

[Claims] 1. A plurality of MOS transistors having the same layout are arranged on the same substrate, a conductive layer is extended below each of the MOS transistors in the substrate, and a predetermined voltage is applied to the conductive layers to form each MOS. A converter characterized in that a threshold voltage of a transistor is continuously controlled, an analog signal is inputted to a gate terminal of each of the MOS transistors, and digitized by an ON / OFF state of each of the MOS transistors. 2. A plurality of sets of MOS transistors of CMOS inverter structure having the same layout are arranged on the same substrate, and a conductive layer is extended below each MOS transistor of the CMOS inverter structure in the substrate, and a predetermined layer is formed on the conductive layer. Voltage is applied to continuously control the threshold voltage of each MOS transistor of the CMOS inverter structure, an analog signal is input to the gate terminal of each MOS transistor, and a digital signal is output depending on the on / off state of each MOS transistor. A converter characterized by being adapted.