JP3265756B2 - converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a converter, for example, a converter which can be used for a flash A / D converter and the like.

[0002]

2. Description of the Related Art Conventionally, in order to change the threshold voltage Vt of a flash inverter using CMOS, the L / W of a transistor has been changed (for example, the 1992 IEICE Spring Conference, C-60
8. "AD converter using a CMOS inverter as a basic component").

[0003]

However, arranging a large number of transistors having different L / W on the same substrate complicates the layout design. Further, in order to arrange a large number of transistors having different L / W on the same substrate, it is necessary to match a minimum transistor with a minimum rule. In order to arrange a transistor having a larger size, a large chip area is required. There was a problem of becoming.

SUMMARY OF THE INVENTION An object of the present invention is to provide a converter having a small chip area and easy layout design.

[0005]

According to a first aspect of the present invention, there is provided a MOS transistor using a thin-film SOI structure having the same layout on the same substrate.
A plurality of transistors are arranged, a conductive layer is extended below the MOS transistors in the substrate, and a predetermined voltage is applied to the conductive layer to continuously control a threshold voltage of each MOS transistor. Each MOS
A gist of the present invention is to provide a converter in which an analog signal is input to a gate terminal of a transistor and digitized according to the on / off state of each MOS transistor.

According to a second aspect of the present invention, a plurality of sets of MOS transistors having a CMOS inverter structure using a thin-film SOI structure having the same layout are arranged on the same substrate, and a conductive material is provided below each MOS transistor having the CMOS inverter structure in the substrate. A threshold voltage of each MOS transistor of the CMOS inverter structure is continuously controlled by extending a layer and applying a predetermined voltage to the conductive layer;
An analog signal is input to the gate terminal of each MOS transistor, and the ON / OFF state of each MOS transistor
A gist of the present invention is a converter that is digitized by an OFF state.

[0007]

According to the first aspect of the present invention, the threshold voltage of each MOS transistor is continuously controlled by continuously controlling the substrate potential by applying a predetermined voltage to the conductive layer. And
An analog signal is input to the gate terminal of each MOS transistor and digitized according to the ON / OFF state of each MOS transistor. Therefore, since MOS transistors having the same layout can be arranged on the same substrate, layout design becomes easy, and MOS transistors having the same layout can be matched to the minimum rule, and the chip area can be reduced.

According to a second aspect of the present invention, a substrate voltage is continuously controlled by applying a predetermined voltage to
The threshold voltage of each MOS transistor having the S inverter structure is continuously controlled. Then, an analog signal is input to the gate terminal of each MOS transistor and digitized according to the ON / OFF state of each MOS transistor. Therefore, since MOS transistors having the same layout can be arranged on the same substrate, layout design is facilitated, and MOS transistors having the same layout can be adjusted to the minimum rule, so that the chip area can be reduced.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

An example in which a MOS transistor using a thin film SOI structure is applied to a 2-bit analog-to-digital converter will be described below. FIG. 1 shows the electrical configuration, and FIG.
2 shows a plan view of the substrate, and FIG. 3 shows a cross-sectional view taken along line AA of FIG.

As shown in FIG. 3, on a substrate 1, four NMOS transistors 2, 3, 4, and 5 having the same layout are arranged in a horizontal row. That is, four thin-film silicon layers (thin-film SOI) 6, 7, 8, 9 are arranged on the surface of the substrate 1, and gate oxide films 10, 11, 12, 12 are formed on the thin-film silicon layers 6, 7, 8, 9, respectively. , 13 extend a common gate electrode 14 common to the transistors. or,
The NMOS transistors 2, 3, 4, and 5 are arranged at equal intervals.

Further, below the NMOS transistors 2, 3, 4, and 5 in the substrate 1, a polycrystalline silicon layer 15 as a conductive layer extends. One end of the polycrystalline silicon layer 15 is connected to a thin film silicon layer (thin film SOI) 16.
And the other end is a thin film silicon layer (thin film S
OI) 17. The thin silicon layer 16
Is connected to the aluminum electrode 18, and the thin film silicon layer 17 is connected to the aluminum electrode 19.

The surface of the substrate 1 is covered with a BPSG film 20. The aluminum electrodes 18 and 19 are connected to a ground potential, and the aluminum electrode 19 is connected to a bias power supply 21 (see FIG. 1) to fix the substrate potentials of the NMOS transistors 2, 3, 4 and 5 to the aluminum electrodes 18 and 19, respectively. ing. In this embodiment, a constant power supply of -6 volts is used as the bias power supply 21.

Then, each of the NMOS transistors 2, 3,
As shown in FIG. 4, the substrate potentials 4 and 5 are fixed to potentials proportional to the distance. On the other hand, the threshold voltage Vt of each of the NMOS transistors 2, 3, 4, and 5 is as shown in FIG.
It changes linearly with the substrate potential. At this time, the transistors are arranged so that the distance between the adjacent transistors is equal, and the difference between the threshold voltages Vt of the adjacent transistors is equal. In this state, when an analog signal is applied to the common gate electrode 14 of each of the NMOS transistors 2, 3, 4, 5, 5, the respective NMOS transistors 2, 3, 4, 5,
Is, as shown in Table 1, the respective NMOS transistors 2, 3,
It is turned on as needed according to the threshold voltages Vt of 4 and 5 and the input voltage Vin, and outputs a digital value corresponding to the input signal.

[0015]

[Table 1]

With this configuration, it can be used as a flash A / D converter. Next, a method of manufacturing the analog-to-digital converter configured as described above will be described. The analog-to-digital converter according to the present embodiment is manufactured using a bonding method. The description of the manufacturing process
This is performed for the area indicated by B in FIG.

First, as shown in FIG. 6, a single crystal silicon substrate 24 is prepared, and a pad oxide film 25 is formed on the entire surface thereof. Further, a nitride film 26 is formed on the entire surface of the pad oxide film 25. Then, the nitride film 26 is patterned by a mirror inversion pattern of a silicon region (SOI region) 27 of an element to be formed later, and a region 28 serving as a field portion is formed.
Is removed.

Then, as shown in FIG. 7, thermal oxidation is performed by the LOCOS method so that the thickness of the oxide film 29 of the field portion 28 becomes, for example, about 600 nm. Next, as shown in FIG. 8, after removing the nitride film 26 and the pad oxide film 25, the entire surface is thermally oxidized to form a silicon region (SOI region) 27.
An oxide film 30 of, for example, about 300 nm is formed thereon.

Furthermore, as shown in FIG. 9, after the patterning for forming contact holes with respect to oxide film 30, to form a contact hole 31 is etched by, for example, reactive ion etching method.

Next, as shown in FIG. 10, a polycrystalline silicon 32 is deposited on the entire surface of the silicon substrate 24. The polycrystalline silicon 32 is Nondobu or N ^- and. Then, as shown in FIG. 11, after the polycrystalline silicon 32 is patterned into a desired region and etched, a film thickness of about 1 is formed on the surface of the polycrystalline silicon 32 by, for example, a thermal oxidation method.
An oxide film 33 of 00 nm is formed. Further, as shown in FIG.
Then, the surface of the thick polycrystalline silicon layer 34 is flattened and polished as shown in FIG.

Next, as shown in FIG. 14, the mirror surface 35a of the single crystal silicon substrate 35 is brought into contact with the polished surface 34a of the polycrystalline silicon 34, for example, in a nitrogen atmosphere.
A heat treatment is performed at a temperature of 1 ° C. for one hour to directly bond and integrate the two substrates. Then, as shown in FIG. 15, the portion of the field oxide film 29 is selectively polished from the back surface side of the single crystal silicon substrate 24 as a polishing stopper, and the thin film silicon layer (thin film SO) is formed.
I region 36 is formed. Finally, after adjusting the SOI film thickness,
As shown in FIG. 3, a gate electrode is formed on the thin film silicon layer (thin film SOI region) 36 by a normal MOSIC process, a source / drain region is formed, and an interlayer insulating film is formed.
An element is completed by forming a metal electrode.

As described above, in this embodiment, as shown in FIGS. 1 to 3, a thin film SOI structure having the same layout is formed on the same substrate 1.
Four MOS transistors 2, 3, 4, and 5 using the structure are arranged, and a polycrystalline silicon layer 15 (conductive layer) is extended below each of the MOS transistors 2, 3, 4, and 5 in the substrate 1. , By applying a predetermined voltage to the polycrystalline silicon layer 15, the MOS transistors 2, 3, 4,
5 is continuously controlled, an analog signal is input to the gate terminals of the MOS transistors 2, 3, 4, 5 and digitized by the on / off states of the MOS transistors 2, 3, 4, 5 I did it.

Therefore, when the threshold voltage Vt is changed by changing the L / W of the conventional transistor, the layout design becomes complicated when a large number of transistors having different L / W are arranged on the same substrate. In addition, there is a problem that the minimum transistor must be adjusted to the minimum rule, and a chip area becomes large in order to arrange a transistor having a larger size. However, in this embodiment, the MOS transistors 2 and 3 using the thin-film SOI structure having the same layout on the same substrate 1 are used.
4 and 5 can be arranged, so that the layout design becomes easy and the MOS transistors 2 and 2 having the same layout are arranged.
3, 4, and 5 can be matched to the minimum rule, and the chip area can be small. (Second Embodiment) Next, a second embodiment will be described focusing on differences from the first embodiment.

In the first embodiment, a thin film SOI structure is formed by a method of laminating two substrates.
As shown in FIG. 6, a thin film SOI structure is formed by an insulating layer embedding method using SIMOX.

Hereinafter, the manufacturing method will be described. As shown in FIG.
As described above, about 10 to 50 μm N^-(10¹⁶cm^-3Less than
Bottom) P with epilayer 37⁺(10¹³cm^-3) Epitaki
A substrate 38 is prepared, and as shown in FIG.
Release P⁺Boron is applied at 150 keV, 1
× 10 ¹⁶cm^-2Injection using resist 39 as a mask
Enter.

Next, as shown in FIG. 19, 150 KeV, 1.3 is applied over the entire surface of the wafer to form an oxide separation layer.
Oxygen ions are implanted at × 10 ¹⁸ cm ^-2 . Then, FIG.
As shown in FIG.
Anneal at 6 ° C for 6 hours. As a result, the device isolation P ⁺ diffusion layer 40, the SiO ₂ layer 41, the thin silicon layer 42
Is formed. At this stage, the formation of the substrate electrode portion is completed.

Hereinafter, as shown in FIG.
By performing the S process, LOCOS isolation is performed, a gate oxide film 43 is formed, and further, a gate polysilicon electrode 44 is formed. Finally, as shown in FIG. 22, a through-hole 45 for forming a substrate electrode is
Then, ion implantation is performed on the source / drain regions, an interlayer insulating film is formed, and aluminum is formed in the through holes 45 by vapor deposition.

As a result, as shown in FIG. 16, aluminum electrodes 46 and 47 are electrically connected to N-epi layer 37 as a conductive layer via N + diffusion layers 48 and 49. here,
The N + diffusion layers 48 and 49 are formed at the same time as source / drain ion implantation .

[0029]

[0030]

[0031]

[0032]

[0033]

( Third Embodiment) Next, a third embodiment will be described.

In each of the above embodiments, only the NMOS is described. However, the present invention can be similarly applied to a CMOS inverter. In other words, thin films with the same layout on the same substrate
By arranging a plurality of sets of MOS transistors having the CMOS inverter structure using the SOI structure, extending a conductive layer below each MOS transistor having the CMOS inverter structure in the substrate, and applying a predetermined voltage to the conductive layer. The threshold voltage of each MOS transistor having a CMOS inverter structure is continuously controlled, an analog signal is input to the gate terminal of each MOS transistor, and each M
Digitalization may be performed according to the ON / OFF state of the OS transistor.

In this case, by applying a predetermined voltage to the conductive layer, the substrate potential is continuously controlled to control the CM.
The threshold voltage of each MOS transistor having the OS inverter structure is continuously controlled. Then, an analog signal is input to the gate terminal of each MOS transistor and digitized according to the ON / OFF state of each MOS transistor. Therefore, since MOS transistors having the same layout can be arranged on the same substrate, layout design is facilitated, and MOS transistors having the same layout can be adjusted to the minimum rule, so that the chip area can be reduced.

[0037]

As described in detail above, according to the present invention,
It offers an excellent effect of easy layout design and small chip area.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing an electric configuration of a first embodiment.

FIG. 2 is a plan view of the substrate of the first embodiment.

FIG. 3 is a sectional view taken along line AA of FIG. 2;

FIG. 4 is a characteristic diagram showing a relationship between a transistor position and a substrate potential.

FIG. 5 is a characteristic diagram showing a relationship between a substrate potential and a threshold voltage.

FIG. 6 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 7 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 8 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 9 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 10 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 11 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 12 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 13 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 14 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 15 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 16 is a sectional view of the second embodiment.

FIG. 17 is a cross-sectional view showing a manufacturing step of the second embodiment.

FIG. 18 is a cross-sectional view showing a manufacturing step of the second embodiment.

FIG. 19 is a cross-sectional view showing a manufacturing step of the second embodiment.

FIG. 20 is a cross-sectional view showing a manufacturing step of the second embodiment.

FIG. 21 is a cross-sectional view showing a manufacturing step of the second embodiment.

FIG. 22 is a cross-sectional view showing a manufacturing step of the second embodiment.

[Explanation of symbols]

 Reference Signs List 1 substrate 2, 3, 4, 5 NMOS transistor 15 polycrystalline silicon layer as conductive layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88 H01L 21/8234 H01L 27/088

Claims (2)

(57) [Claims] 1. A thin film SOI having the same layout on the same substrate
A plurality of MOS transistors using the structure are arranged, a conductive layer is extended below the MOS transistors in the substrate, and a predetermined voltage is applied to the conductive layer to continuously set a threshold voltage of each MOS transistor. Wherein the analog signal is input to the gate terminal of each of the MOS transistors and digitized according to the on / off state of each of the MOS transistors. 2. A thin film SOI having the same layout on the same substrate.
A plurality of sets of MOS transistors having a CMOS inverter structure using a CMOS structure are arranged, and the C
A conductive layer is extended below each MOS transistor having a MOS inverter structure, and a predetermined voltage is applied to the conductive layer to continuously control a threshold voltage of each MOS transistor having the CMOS inverter structure. A converter characterized in that an analog signal is input to a gate terminal of a transistor and digitized according to an on / off state of each of the MOS transistors.