JPH07106511A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a parasitic capacity of a predetermined conductor pattern formed on a semiconductor substrate without making the construction more complicated and without considering the restrictions such as the width of a predetermined conductor pattern. CONSTITUTION:In a region below a load resistor R1 connected to a collector of a bipolar transistor forming a differential amplifying circuit of an ECL circuit in a semiconductor layer formed through an insulation layer, a first insulation separating portion 3a is formed to a frame shape surrounding the load resistor R1, and a semiconductor layer inside the first insulation separating portion 3a is separated into a plurality of the regions of semiconductor layers 2c1 by the second insulation separating portion 3b formed to a grid shape.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device technique, and more particularly to a technique effectively applied to a semiconductor integrated circuit device which is required to operate at high speed.

[0002]

2. Description of the Related Art How to reduce the parasitic capacitance associated with a predetermined conductor pattern formed on a semiconductor substrate is an important subject for improving the operating speed of a semiconductor integrated circuit device.

Conventionally, in order to reduce the parasitic capacitance, for example, a shield layer made of a conductor is provided between wiring layers formed on a semiconductor substrate, or the width of a predetermined conductor pattern is narrowed.

The parasitic capacitance is described, for example, in "CMOS Device Handbook", P367 to P370, published on September 29, 1987 by Nikkan Kogyo Shimbun Co., Ltd. Capacity is described.

[0005]

However, the present inventor has found that the above-mentioned conventional technique has the following problems.

First, in the technique of providing a shield layer between wiring layers, it becomes difficult to manufacture a semiconductor integrated circuit device because the structure of a connection hole portion for connecting the wiring layers becomes complicated, and the semiconductor integrated circuit is difficult to manufacture. There is a problem that the yield and reliability of the device are lowered.

Further, in the technique of narrowing the width of the predetermined conductor pattern, there is a problem that the width of the predetermined conductor pattern is limited due to electrical restrictions and the like.

The present invention has been made in view of the above problems, and an object of the present invention is not to complicate the structure of a semiconductor integrated circuit device and to consider a constraint such as a width of a predetermined conductor pattern. Another object is to provide a technique capable of reducing the parasitic capacitance of a predetermined conductor pattern formed on a semiconductor substrate.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

[0010]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the invention according to claim 1 is a semiconductor integrated circuit device having a predetermined conductor pattern on an upper layer of a semiconductor layer formed on a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor integrated circuit device structure has a parasitic capacitance and another capacitance smaller than the parasitic capacitance connected in series.

[0012]

According to the invention described in claim 1, the substantial parasitic capacitance value formed between the predetermined conductor pattern and the semiconductor substrate is formed between the predetermined conductor pattern and the semiconductor substrate. Since this is a value obtained by combining a pure parasitic capacitance and a capacitance connected in series with the pure parasitic capacitance, the substantial parasitic capacitance can be reduced.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a plan view of a main portion of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a sectional view of a main portion of the semiconductor integrated circuit device of FIG. 1, and FIG. 3 is a semiconductor integrated circuit of the present embodiment. FIG. 4 is a plan view of an essential part of the device, FIG. 4 is a sectional view of an essential part of the semiconductor integrated circuit device of FIG. 3, and FIG. 5 is a circuit diagram of a basic circuit constituting the semiconductor integrated circuit device of this embodiment.

The semiconductor integrated circuit device of this embodiment is, for example, a semiconductor logic circuit having a predetermined logic function, and is provided with, for example, an ECL circuit 1 as shown in FIG. 5 as a basic circuit.

The ECL circuit 1 includes a differential amplifier circuit section 1a and
And an output circuit section 1b. Differential amplifier circuit section 1a
Is composed of bipolar transistors Q ₁ and Q ₂ . The output circuit section 1b includes load resistors (predetermined conductor patterns) R ₁ and R ₂ , bipolar transistors Q ₃ and
It is composed of Q ₄ and resistors l _{1 to} l ₃ .

The collector of the bipolar transistor Q ₁ is electrically connected to the base of the bipolar transistor Q ₄ and also electrically connected to the ground electrode GND via the load resistor R ₁ . The collector of the bipolar transistor Q ₂ is electrically connected to the base of the bipolar transistor Q ₃ , and the load resistance R
_It is electrically connected to the ground electrode GND via ₂ .
The bases of the bipolar transistors Q ₁ and Q ₂ are electrically connected to the input terminals V _IN1 and V _IN2 .

The emitters of the bipolar transistors Q _{1 to} Q ₃ are electrically connected to the reference electrode VEE of negative potential via the resistors l _{1 to} l ₃ , respectively. The emitter of the bipolar transistor Q _3, Q ₄ is electrically connected to the output terminals V _OUT1, V _OUT2.

Next, FIG. 1 and FIG. 2 show a plan view and a sectional view of the semiconductor substrate in the above-mentioned formation region of the load resistance R ₁ .

The semiconductor substrate 2 of this embodiment is, for example, SOI.
It has a structure. That is, the semiconductor substrate 2 includes the substrate layer 2a, the insulating layer 2b formed thereon, and the insulating layer 2
It is composed of a semiconductor layer 2c formed on b.

The substrate layer 2a is made of, for example, silicon (Si) single crystal. The insulating layer 2b is made of, for example, silicon dioxide (S
iO ₂ ). The semiconductor layer 2c is made of, for example, a Si single crystal, in its place, a semiconductor integrated circuit device such as a bipolar transistor Q ₁ to Q ₄ described above is formed.

The semiconductor substrate 2 having such an SOI structure is
For example, after bonding a first semiconductor substrate having an insulating layer 2b formed on its main surface to another prepared second semiconductor substrate while sandwiching the insulating layer 2b, the first semiconductor substrate or the second semiconductor substrate It is created by a so-called sticking method, which is created by grinding and polishing the back surface.

However, the method for producing the semiconductor substrate having the SOI structure is not limited to the above-mentioned pasting method, and various changes can be made. For example, oxygen (O ₂ ) is ion-implanted at a predetermined position of the semiconductor substrate. After that, the semiconductor substrate is heat-treated to leave a Si layer on the surface of the main surface of the semiconductor substrate, and to add S ₂ to the portion where O ₂ is ion-implanted.
forming an insulating layer made of iO _2, the so-called SIMOX
(Separation by Implanted Oxygen) method may be used.

By the way, in the present embodiment, in the region below the load resistor R ₁ in the semiconductor layer 2c, for example, the first insulating separation portion 3a formed in a plane frame shape so as to surround the load resistor R ₁ is provided. ing. The first insulating separation portion 3a is
For example, the groove 4 reaching the insulating layer 2b from the main surface of the semiconductor layer 2c
An insulating film made of, for example, SiO ₂ is embedded and formed in a.

In addition, the semiconductor layer 2c in the region surrounded by the first insulation separation portion 3a is composed of a plurality of semiconductor layers 2c formed by the second insulation separation portion 3b formed in, for example, a plane lattice shape.
It is separated into the region of c ₁ . The second insulating separation part 3b is also
For example, the groove 4 reaching the insulating layer 2b from the main surface of the semiconductor layer 2c
An insulating film made of SiO ₂ or the like is formed by being embedded in b.

Further, on the semiconductor layer 2c, for example, Si
An insulating film 5a made of O ₂ is deposited. Insulating film 5a
In the above, a connection hole 6a reaching the semiconductor layer 2c is bored on the outer side of the first insulating separation portion 3a, and the electrode 7 made of, for example, an Al-Si-Cu alloy is connected to the semiconductor layer 2c through the connection hole 6a. Is electrically connected to. Electrode 7
Is formed in a frame shape so as to surround the first insulating separation portion 3a, and is electrically connected to, for example, the GND potential (0V).

A load resistor R ₁ made of, for example, polysilicon set to a predetermined resistance value is formed on the insulating film 5a, and is made of, for example, SiO ₂ so as to cover the load resistor R _1. The insulating film 5b is deposited.

As described above, in this embodiment, the capacitance C ₀ formed by the insulating film 5a and the first insulation separation portion 3a and the second insulation separation portion 3b are provided between the load resistance R ₁ and the electrode 7. The formed capacitors C ₁ and C ₂ are the same as the semiconductor layer 2c.
It is in a state of being connected in series via the resistor R ₃ of ₁ .

That is, in this embodiment, since the parasitic capacitance value of the load resistance R ₁ is a value obtained by combining the capacitance C ₀ and the capacitances C ₁ and C ₂ connected in series to the capacitance C ₀ , the load resistance R ₁ is It is possible to reduce the substantial parasitic capacitance of R ₁ . Although not shown, the load resistor R ₂ has a similar structure. Therefore, it is possible to reduce the substantial parasitic capacitance of the load resistance R ₂ .

Next, a plan view and a sectional view of the semiconductor substrate in the region where the bonding pad is formed are shown in FIGS. 3 and 4, respectively.

On the insulating film 5b, a bonding pad (predetermined conductor pattern) 8 for drawing out the electrode of the semiconductor logic circuit formed on the semiconductor layer 2c to the outside is formed. The bonding pad 8 is, for example, Al-Si-
It is made of a Cu alloy, and a part of it is exposed from the surface protective film 5c deposited on the insulating film 5b.

By the way, in this embodiment, as shown in the figure, the bonding pad 8 is formed on the semiconductor layer 2c.
In a region below the same, for example, the first insulating separation portion 3a formed in a frame shape so as to surround the bonding pad 8 is provided, and the semiconductor layer 2c surrounded by the first insulating separation portion 3a is formed. , The plurality of semiconductor layers 2c ₁ are separated by the second insulating separation portion 3b formed in a planar lattice shape.

In this case, also in the first insulating separation portion 3a and the second insulating separation portion 3b, for example, an insulating film made of SiO ₂ or the like is formed in the grooves 4a and 4b reaching the insulating layer 2b from the main surface of the semiconductor layer 2c. It is formed by being embedded.

Therefore, in the present embodiment, the capacitors C ₀₁ and C ₀₂ formed by the insulating films 5a and 5b and the first insulating separation portion 3 are provided between the bonding pad 8 and the electrode 7.
a and the capacitance C formed by the second insulating separation portion 3b
₁ and C ₂ are connected in series via the resistor R ₃ of the semiconductor layer 2c.

That is, in this embodiment, the parasitic capacitance value of the bonding pad 8 is a value obtained by combining the capacitances C ₀₁ and C ₀₂ and the capacitances C ₁ and C ₂ connected in series to them. It is possible to reduce the substantial parasitic capacitance of the bonding pad 8.

As described above, according to this embodiment, the following effects can be obtained.

(1). Load resistances R ₁ and R in the semiconductor layer 2c
_In the region below ₂ , the first insulation separation part 3a is provided so as to surround the load resistances R ₁ and R ₂ , and the semiconductor layer 2c surrounded by the first insulation separation part 3a is formed by the second insulation separation part 2b. It is possible to reduce the substantial parasitic capacitance value formed between the load resistances R ₁ and R ₂ and the semiconductor layer 2c by separating into the region of the semiconductor layer 2c ₁ . Therefore, it is possible to reduce the parasitic capacitance attached to the collector terminals of the bipolar transistors Q ₁ and Q ₂ of the differential amplifier circuit section 1a that constitutes the ECL circuit 1.

(2). In the region below the bonding pad 8 in the semiconductor layer 2c, the first insulating separation portion 3a is provided so as to surround the bonding pad 8, and the semiconductor layer 2c surrounded by the first insulating separation portion 3a. Is separated into regions of the plurality of semiconductor layers 2c ₁ by the second insulating separation portion 2b, so that the bonding pad 8 and the semiconductor layer 2c are separated.
It is possible to reduce the substantial parasitic capacitance value that is formed between and.

(3) By the above (1) and (2), it is possible to improve the operating speed of the semiconductor integrated circuit device.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-described embodiment, the case where the semiconductor layer in the first insulation separation portion is separated into the regions of the plurality of semiconductor layers by the second insulation separation portion has been described, but the present invention is not limited to this, and for example, As shown in FIG. 6, only the first insulating separation portion 3a may be provided in the semiconductor layer below the load resistance R ₁ . Further, the first insulating / separating portion is not limited to a single layer, and may be a double layer as shown in FIG. 7, for example. Although not shown in the drawing, the semiconductor layer below the load resistance may be separated into a plurality of semiconductor layer regions by the grid-like second insulating separation portion.

In the above embodiment, the case where the SOI substrate is used as the semiconductor substrate has been described, but the present invention is not limited to this, and for example, a normal semiconductor substrate may be used.

This case is shown in FIG. A groove 4c is formed in the semiconductor substrate 2. An insulating film 5d made of, for example, SiO ₂ is formed on the side surface and the bottom surface of the groove 4c. The insulating film 5d formed on the side surface of the groove 4c corresponds to the first insulating separation portion of the above-described embodiment. A semiconductor layer 2c made of, for example, polysilicon is embedded in the groove 4c. The semiconductor layer 2c is composed of, for example, a plurality of semiconductor layers 2c formed by the second insulating separation portions 3b formed in a plane lattice shape.
Are separated into areas. The electrode 7 is electrically connected to the semiconductor substrate 2 through a connection hole 6a formed in the insulating film 5a. Also in this case, it is possible to obtain the same effect as that of the above embodiment.

In the above embodiment, the case where the predetermined conductor pattern is the load resistance and the bonding pad has been described. However, the present invention is not limited to this, and various modifications are possible. It may be part of the signal wiring.

In the above description, the invention made by the present inventor is the ECL which is the field of application behind the invention.
The case where the present invention is applied to a semiconductor integrated circuit device having a circuit has been described, but the present invention is not limited to this and various applications are possible.
For example, CMOS (Complimentary MOS) circuit and BiCMO
The present invention can also be applied to other semiconductor integrated circuit devices such as a semiconductor integrated circuit device having an S (Bipolar CMOS) circuit.

[0046]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

According to the first aspect of the present invention, the substantial parasitic capacitance value formed between the predetermined conductor pattern and the semiconductor substrate is the pure parasitic capacitance value formed between the predetermined conductor pattern and the semiconductor substrate. Since this is a value obtained by combining the parasitic capacitance and the capacitance connected in series with this parasitic capacitance, it is possible to reduce the substantial parasitic capacitance. Therefore, the operating speed of the semiconductor integrated circuit device can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of essential parts of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view of main parts of the semiconductor integrated circuit device of FIG.

FIG. 3 is a plan view of a principal portion of the semiconductor integrated circuit device of this embodiment.

FIG. 4 is a cross-sectional view of essential parts of the semiconductor integrated circuit device of FIG.

FIG. 5 is a circuit diagram of a basic circuit constituting the semiconductor integrated circuit device of this embodiment.

FIG. 6 is a plan view of a principal portion of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 7 is a plan view of a main portion of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 8 is a cross-sectional view of essential parts of a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ECL circuit 1a Differential amplifier circuit section 1b Output circuit section 2 Semiconductor substrate 2a Substrate layer 2b Insulating layers 2c, 2c ₁ Semiconductor layer 3a First insulating separation section 3b Second insulating separation section 4a, 4b, 4c Grooves 5a, 5b, 5d insulating film 5c surface protective film 6a connecting hole 7 electrode 8 bonding pad (predetermined conductor pattern) Q ₁ to Q ₄ bipolar transistor R _1, R ₂ load resistor (predetermined conductor pattern) R ₃ resistor l ₁ to l ₃ resistor GND ground electrode VEE reference electrode V _IN1 , V _IN2 input terminal V _OUT1 , V _OUT2 output terminal C ₀ , C ₀₁ , C ₀₂ , C ₁ , C ₂ capacitance

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/822 21/8249 27/06 9170-4M H01L 27/06 321 C

Claims (5)

[Claims] 1. A semiconductor integrated circuit device having a predetermined conductor pattern on an upper layer of a semiconductor layer formed on a semiconductor substrate with an insulating layer interposed between the semiconductor layer and the parasitic capacitance of the predetermined conductor pattern. A semiconductor integrated circuit device characterized in that another capacitance smaller than the capacitance is connected in series. 2. A semiconductor integrated circuit device having a predetermined conductor pattern on an upper layer of the semiconductor layer formed on a semiconductor substrate with an insulating layer interposed between the semiconductor layer below the predetermined conductor pattern and the predetermined conductor pattern. 2. A semiconductor integrated circuit device, comprising: an insulating separation portion that extends from the upper surface of the semiconductor layer to the insulating layer so as to surround the conductor pattern. 3. A semiconductor integrated circuit device having a predetermined conductor pattern on a semiconductor layer formed on a semiconductor substrate with an insulating layer interposed therebetween, wherein the semiconductor layer below the predetermined conductor pattern is the semiconductor layer. A semiconductor integrated circuit device, characterized in that it is divided into a plurality of semiconductor regions by an insulating separation portion reaching from the upper surface of the layer to the insulating layer. 4. A semiconductor integrated circuit device having a predetermined conductor pattern on an upper layer of a semiconductor layer formed on a semiconductor substrate with an insulating layer interposed therebetween, wherein the predetermined layer is formed on the semiconductor layer below the predetermined conductor pattern. A first insulating separation portion reaching the insulating layer from the semiconductor layer is provided so as to surround the conductor pattern of, and a semiconductor layer in the first insulating separation portion reaches a second insulating layer from an upper surface of the semiconductor layer. A semiconductor integrated circuit device characterized by being separated into a plurality of semiconductor regions by an insulating separation section. 5. A semiconductor integrated circuit device, wherein the predetermined conductor pattern according to claim 1, 2, 3 or 4 is a part of a resistance pattern, a bonding pad or a clock signal wiring.