JPH02246259A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To constitute a highly reliable IC in a three-dimensional pattern by sticking one main surface of a first semiconductor wafer on which either of a semiconductor element or a wiring is formed to a second semiconductor wafer. CONSTITUTION:An n-type well 2n and a p-type well 2p are provided on a first wafer 11. A p-channel MOS element 3p is formed on the n-type well 2n on the surface side of the first wafer 11. An n-channel MOS element 3n is formed on the p-type well 2p. Well contacts 4n and 4p for the n-type well 2n and the p-type well 2p are guided out of the surface of the first wafer 11 through grooves 14 which are communicated to the surface from a wirings 13 that are formed at the rear surface of the first wafer 11. The first wafer 11 and a second wafer 12 are bonded through an insulating film 15 comprising an SiO2 film. Thus, the device is constituted in a three-dimensional pattern, while a high integration density can be achieved, the wiring length is shortened, high speed operation can be performed and reliability is improved.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor device having a structure in which two wafers are bonded together and a method for manufacturing the same, with the purpose of three-dimensionally configuring a highly reliable IC. The semiconductor device is characterized by having a structure in which one main surface of a first semiconductor wafer provided with at least one of semiconductor elements or wiring is bonded to a second semiconductor wafer.

In addition, the manufacturing method includes forming at least one of a semiconductor element or wiring on one main surface of a first semiconductor wafer, bonding the one main surface to a second semiconductor wafer, and then bonding the first semiconductor wafer to a second semiconductor wafer. It is characterized in that it includes a step of forming at least either a semiconductor element or wiring on the other main surface.

[Industrial application field]

The present invention relates to a semiconductor device having a structure in which two wafers are bonded together, and a method for manufacturing the same, among semiconductor devices and methods for manufacturing the same.

In recent years, semiconductor devices have become increasingly highly integrated, and three-dimensional (three-dimensional) structures, such as the Sol structure, have been developed using the laser melting method. A semiconductor device with a three-dimensional structure using a substrate is desired.

[Prior Art and Problems to be Solved by the Invention] Conventionally, in semiconductor devices, patterns have been miniaturized to achieve high integration, and this has been the most effective method. However, there is a limit to high integration through pattern miniaturization alone.
For example, an IC (CMO3-I
In C), in order to prevent the substrate potential from floating, it is necessary to make a contact also in the well region, which requires a correspondingly large area. FIG. 7 is a diagram illustrating an example of the conventional problem. In the silicon substrate 1, an n-well 2n is provided to form a p-channel MO3 element 3p, and a p-well 2p is provided to form an O8 element 3n between the n-channels. However, both MO3 elements are well contact)
4n and 4p are required, which requires a larger area.
High integration is impaired.

On the other hand, as mentioned above, a method of stacking up SOI structures three-dimensionally using the laser melting method is known, but even if it is melted and made into a single crystal using the laser melting method, a substrate with sufficiently good crystal quality cannot be produced, resulting in poor reliability. The disadvantage is that a high IC cannot be obtained.

The present invention solves these problems and provides highly reliable I/O.
This paper proposes a semiconductor device and a method of manufacturing the same for the purpose of three-dimensionally configuring C.

[Means to solve the problem]

The problem is, as shown in FIG. 1, that one principal surface of a first semiconductor wafer 11, which has at least one of semiconductor elements or wiring on its opposing bidirectional surfaces, is replaced by a second semiconductor wafer 11,
The problem is solved by a semiconductor device having a structure in which two parts are bonded together.

Further, the manufacturing method includes forming at least one of a semiconductor element or a wiring on one main surface of a first semiconductor wafer, and then bonding the one main surface to a second semiconductor wafer, and then bonding the first semiconductor wafer to a second semiconductor wafer. The method is characterized in that it includes a step of forming at least either a semiconductor element or a wiring on the other main surface.

[For production]

In the present invention, two semiconductor wafers (hereinafter abbreviated as wafers) are bonded together, semiconductor elements and wiring are provided on both the front and back sides of one wafer, and, for example, communicating grooves are used to connect both sides.

By doing so, the quality of semiconductor elements will be improved by using wafers with good crystal quality, and high integration will be possible because semiconductor elements and wiring are formed on both sides of the wafer.Moreover, the wiring can be shortened, so high speeds will be achieved. It also helps with movement.

〔Example〕

Examples will be described in detail below with reference to the drawings.

FIG. 1 shows a cross-sectional view of Example (1) according to the present invention, where 11 is a first wafer, 12 is a second wafer, the first wafer 11 is provided with an n well 2n and a p well 2p,
A p-channel MO3 element 3p is formed in the n-well 2n on the front side of the first wafer 11, and an n-channel MO3 element 3n is formed in the p-well 2p, and well contacts are established between the n-well 2n and the p-well 2p. 4n, 4
This is a structure in which p is led out to the front surface of the first wafer 11 from a wiring 13 (lead wiring) formed on the back surface of the first wafer 11 via a groove 14 communicating with the front surface. Note that the conductive wiring layer on the back surface and in the groove is formed of a conductive polycrystalline silicon film.

Further, the first wafer 11 and the second wafer 12 are Si0
They are bonded via an insulating film 15 made of a (silicon oxide) film. In this way, well contact 4n+ 4
Since p is provided on the back surface and exposed through the insulating film, the area occupied by the device on the front surface is reduced accordingly, making it possible to achieve high integration.

Next, FIGS. 2(a) to 2) show examples (1) according to the present invention.
), and this step is a step-by-step sectional view of the forming method until the well contact 4 is led out from the back surface of the first wafer.

To explain sequentially, FIG. 2(a); The first wafer 11 is thermally oxidized and Stow
After forming a film 16 (insulating film) and opening a window in the Si0g film on the back side of the wafer, a conductive polycrystalline silicon film is deposited on the backside and patterned to form wiring 13 made of the conductive polycrystalline silicon film. Form.

(FIG. 2); Next, a Sing film 15 is deposited on the entire surface of the wafer including the wiring 13 on the back surface thereof, and the wafer is planarized.

At that time, if necessary, polishing, chemical etching, etc. are performed to flatten the surface.

FIG. 2(C); Next, SiO! of the first wafer 11! The back surface covered with the film 15 and the flat surface of the second wafer 12 are bonded. For example, the bonding method includes heat treatment at 1100° C. for 30 to 60 minutes. Then, the H groups and OH groups adhering to the SiO□ film are separated, and the 0 groups are firmly bonded and adhered. Note that even if the adhesion surface of the second wafer 12 is not specially oxidized to create a SiO□ film, a Sing molecule film consisting of a small layer is usually formed on the wafer surface, which contributes to adhesion. do.

Incidentally, the degree of unevenness of the adhesive surface (T T V ; Total T
h1cknessVariation) is desirably 2 pm or less, so that the adhesive strength becomes strong. Further, as the bonding method, in addition to the heat treatment method described above, it is also possible to bond by an electrostatic pressure bonding method.

FIG. 2(d): Next, the surface of the first wafer 11 is polished to a thickness of 3 μm or less.

FIG. 2(e); Next, a groove 14 (trench) is formed at a predetermined position on the first wafer using a known trench forming method.

FIG. 2(f): Next, a Sing film 17 is formed on the inner surface and surface of the groove of the first wafer 11 by thermal oxidation, and then a conductive polycrystalline silicon film is buried in the groove to form a well contact. Derive 4n.

Thereafter, an n-well 2n and a p-well 2p are formed on the first wafer 11 by a known manufacturing method, and a p-channel MO3 element 3p and an n-channel MO3 element 3n are formed on the surface thereof, completing the process as shown in FIG. . Although only the well contact 4n has been illustrated and explained above, the other well contact 4p is also formed at the same time as the well contact 4n.

Next, FIG. 3 shows a cross-sectional view of Example (II) according to the present invention, where 31 is a first wafer, 32 is a second wafer, and an n-channel MO3 element 5n is provided on the back surface of the first wafer 31. The n-channel MO3 element 6n is formed on the front surface, and the source contact 4S and drain contact 4d of the n-channel MO3 element 5n on the back surface are connected to the first wafer 3.
A groove 34 that communicates with the surface from the wiring 33 formed on the back surface of 1.
This is a structure that is led out to the surface of the first wafer 31 via.

In addition, as in FIG. 1, the first wafer 31 and the second wafer 32 are bonded to each other via the Sing film 35, and with this configuration, the element area is reduced to about 172 and the degree of integration is improved. do.

Next, FIGS. 4(a) to 4(b) show examples (
This is a step-by-step sectional view of the forming method II), and this step is a step-by-step drawing mainly showing the forming method up to leading out the source contact 4s from the back surface of the first wafer. To explain sequentially, FIG. 4(a); this figure shows 5iO on both sides of the first wafer 31.
1 film 36 is formed, and an n-channel MO3 element 5n is formed on the back surface of the wafer by a known manufacturing method.
FIG. 3 is a diagram showing the formation of wiring 33 made of a conductive polycrystalline silicon film led out from the source and drain of n.

FIG. 4(b): Next, the wiring 33 on the back side of the wafer
SiO on the entire surface including the top! A film 35 is deposited and planarized.

FIG. 4(C); Next, the back surface of the first wafer 31 on which the Sing film 35 has been planarized is bonded to the flat surface of the second wafer 32, and the surface of the first wafer 31 is further polished to a thickness of 3 μm. to a certain degree. The adhesion method is similar to the method described above.

FIG. 4(B): Next, a groove 34 is formed in the first wafer 31, and the Stow film 3 is formed on the inner surface and surface of the groove by thermal oxidation.
After forming 7 films, a conductive polycrystalline silicon film is buried in the trench to expose the source contact 4S.

After that, an n-channel MO3 element 6n is formed on the surface of the first sea urchin A-31 by a known manufacturing method, and the device is completed as shown in FIG. Note that although only the source contact 4S has been illustrated and explained above, the other drain contacts 4d are also formed at the same time.

Next, FIG. 5 shows a sectional view of the embodiment (1) according to the present invention, in which 51 is a first wafer A+, 52 is a second wafer, and the first wafer 51 is connected to the first wafer 51 through an element isolation band 58. A groove in which two npn type bipolar elements 3b', 3b'' are arranged in parallel and the respective collector contacts 4c + 4c'' of these bipolar elements are communicated with the surface from the wiring 53 formed on the back surface of the first Ueno 1-'51. This is a structure that is led out to the surface of the first wafer 11 via 54.

In this way, collector contacts 4c, 4Crt
Since the elements are exposed through the insulating film from the back surface, the element area is reduced and higher integration can be achieved.

Next, FIGS. 6(a) to (C) show Example C according to the present invention.
DI), which is a step-by-step cross-sectional view of a method for forming DI), and this step is a step-by-step diagram mainly showing forming steps specific to bipolar elements. To explain the outline, FIG. 6(a); in this figure, wiring 53 is formed on the back surface of the first wafer 51, and SiO
□This is an intermediate view of the process in which the film 55 is deposited and flattened, the wafer 51 in FIG. . That is, this figure shows the completed process of FIGS. 2(a) to 2(d).

FIG. 6 O)); Next, impurities are diffused into the surface of the first wafer 51 to make the entire silicon surface of the first wafer an n-type buried layer 59, and then n-type epitaxial growth is performed on the buried layer 59 of the first wafer. Grow layer 60.

FIG. 6(C); Next, an element isolation band 58 is formed, and the groove 5
4 is formed, a conductive polycrystalline silicon film is buried in the groove, and a collector contact 4C'14C'' is led out to the surface of the first wafer 51.

Thereafter, bipolar elements 3b' and 3b'' are formed on the surface of the first wafer 51 by a known manufacturing method, and the fifth
Complete as shown in the diagram.

All of these embodiments have a structure in which two semiconductor wafers are bonded together and semiconductor elements and wiring are provided on both the front and back surfaces of the first wafer. After forming a wafer, the back surface thereof is bonded to a second wafer, and then semiconductor elements and wiring are formed on the front surface of the first wafer.

〔Effect of the invention〕

As is clear from the description of the embodiments above, according to the semiconductor device and manufacturing method of the present invention, semiconductor elements and wiring are provided on a wafer with good crystal quality, so the quality of the semiconductor device is improved. In addition, since semiconductor elements and wiring are formed on both sides of the wafer, it is highly integrated, and the wiring can be shortened, so these effects combine to improve the performance of semiconductor devices such as high-speed operation. It is something.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of Example (I) according to the present invention, Fig. 2 (a) to (f) are cross-sectional views in order of steps of the forming method of Example (I), and Fig. 3 is a cross-sectional view of Example (I) according to the present invention. Cross-sectional view of Example (II), No. 4
Figures (a) to (d) are step-by-step cross-sectional views of the forming method of Example (II); Figure 5 is a cross-sectional view of Example (T[) according to the present invention;
Figures (a) to Sakaki are step-by-step cross-sectional views of the forming method of Example (III), and Figure 7 is a diagram showing the problems of the conventional method. In the figure, 11, 31.51 are the first wafer 12, 32.52 are the second wafer 13, 33.53 are wiring (lead wiring), 14, 34.5
4 is the groove, 15, 35.55 is the SiO□ film (insulating film to be bonded), 3
p is P channel MO3 element, 3n, 5n, 6n are n channel MO3 element, 4n+
4p is a well contact, 4s is a source contact, 4d is a drain contact, 3b' and 3b'' are bipolar elements, and 4c'+4c'' is a collector contact.

Claims (4)

[Claims] (1) A semiconductor device characterized by having a structure in which one main surface of a first semiconductor wafer, which has at least either a semiconductor element or wiring provided on both opposing main surfaces, is bonded to a second semiconductor wafer. (2) A structure characterized in that the wiring provided on one main surface of the first semiconductor wafer is led out to the surface of the first semiconductor wafer via a groove communicating with both main surfaces. 1) The semiconductor device described above. (3) providing a lead-out wiring from the well layer or a lead-out wiring from the buried layer on one main surface of the first semiconductor wafer;
3. The semiconductor device according to claim 2, further comprising a structure for leading out to the other main surface of the first semiconductor wafer via a groove communicating with both main surfaces. (4) After forming at least one of semiconductor elements or wiring on one main surface of the first semiconductor wafer, the one main surface is bonded to a second semiconductor wafer, and then the other main surface of the first semiconductor wafer is bonded to a second semiconductor wafer. 1. A method of manufacturing a semiconductor device, comprising the step of forming at least a semiconductor element or a wiring on a surface.