JPH07105887B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing apparatus, and more particularly, it compares an input image signal with a pattern signal having a predetermined period to perform pulse width modulation.
The present invention relates to an image processing device that outputs a binarized image signal.

[Prior Art] As a method of forming a halftone image by a laser beam printer or the like, converting an input digital image signal into an analog image signal and comparing the analog image signal with a periodic analog pattern signal such as a triangular wave signal. The applicant of the present invention has proposed a method of generating a binarized image signal that is pulse width modulated by the above method. FIG. 4 shows a specific example of this method. In the figure, the 8-bit input digital video signals VD _{0 to} VD ₇ are video clock signals 1 /
It is latched by latch circuit 1 with 2 CLK and synchronized.
Video clock signal 1/2 CLK is the master clock signal CLK
Is a clock signal obtained by frequency-dividing by 2 with a J-K flip-flop 5. Also, the latched video signal is converted into an analog video signal VA by the D / A converter 2, the analog video signal VA is converted into a voltage level by the resistor 3, and then input to one input terminal of the comparator 4. . On the other hand, the master clock signal CLK is divided by n by the frequency divider 6 to become the clock signal 1 / n CLK, and further divided by 2 by the JK flip-flop 8 to obtain a pattern clock with a duty ratio of 50%. It becomes the signal PCLK. Therefore, the pattern clock signal PCLK has a cycle n times that of the video clock signal 1/2 CLK. In addition, the pattern clock signal PCLK
Is input to the integrator circuit consisting of variable resistor 10 and capacitor 11 through buffer 9, and the pattern clock signal PCLK
Triangle wave signal (analog pattern signal) SAW with the same cycle as
Becomes The bias of the triangular wave signal SAW is further adjusted by the capacitor 12 and the variable resistor 13, and the triangular wave signal SAW is input to the other input terminal of the comparator 4 through the protective resistor 14 and the buffer amplifier 15. The comparator 4 compares the analog video signal VA and the triangular wave signal SAW, and the analog video signal VA is pulse width modulated according to its density. Here, in order to obtain high gradation, it is desirable that the level of the analog video signal VA and the level of the triangular wave signal SAW have a relationship as shown in FIG. That is, the maximum level VAmax (for example, black level) of the analog video signal VA and the peak level of the triangular wave signal SAW match, and the minimum level VAmin (for example, white level) of the analog video signal VA matches the bottom level of the triangular wave signal SAW. It is a relationship. This is because the maximum resolution and full-scale linearity are always maintained. Therefore, in order to satisfy the relationship of FIG. 5, the amplitude is adjusted by the variable resistor 10 of the triangular wave signal generating circuit, and the bias component is adjusted by the variable resistor 13.

By the way, images reproduced by such a device have various image tones. For example, in a character image, faithful reproduction of pixels changing from white to black or from black to white is emphasized rather than in halftone reproduction, and in a photographic image, reproduction of halftone is emphasized. Therefore, in the apparatus shown in FIG. 4, the cycle of the pattern clock signal PCLK can be switched depending on which image tone reproducibility is important. That is, the frequency divider 6 can change its frequency division ratio to, for example, 1/1 / n by the cycle switching signal SEL. Thus, in the character image reproduction, the frequency division ratio is set to 1, for example, one pixel of the input digital video signal is pulse-width modulated from one triangular wave signal SAW, and the pixel changing from white to black or black to white is faithfully reproduced. Further, in reproducing a photographic image, the frequency division ratio is set to n, for example, and n pixels of the input digital video signal are pulse-width modulated from one triangular wave signal SAW to reproduce smooth gradation pixels.
However, in the above-mentioned device, the frequency, amplitude and bias of the triangular wave signal SAW are changed by switching the frequency division ratio, so that the relationship in FIG. 5 cannot be satisfied as it is. Therefore, in the apparatus shown in FIG. 4, the adjustment of the variable resistors 10 and 13 had to be adjusted for this purpose. In addition, when characters and photographs are mixed in one image, it is always necessary to sacrifice the image quality of any one of them.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-described conventional example. As in the conventional case, a troublesome pattern signal including image signals, which is necessary when switching pattern signals, An object of the present invention is to provide an image processing device that does not require a setting operation.

Another object of the present invention is to provide an image processing apparatus capable of performing optimum pulse width modulation according to each image tone even if a character image and a photographic image are mixed in one image. is there.

[Means for Solving Problems] In order to achieve the above object, the image processing apparatus of the present invention has the following configuration. That is, the input means for inputting the image signal and the image signal input by the input means are modulated according to the first pattern signal having a predetermined cycle or the second pattern signal having a cycle different from the first pattern signal. Pulse width modulation signal generating means for selectively outputting a pulse width modulation signal, wherein the pulse width modulation signal generating means is preset so that a relative signal level with respect to the image signal becomes constant. It has a pattern signal generation circuit for generating first and second pattern signals.

[Operation] In the above configuration, the image signal input by the input means is modulated in accordance with the first pattern signal having a predetermined cycle or the second pattern signal having a cycle different from the first pattern signal. The width modulation signal is selectively output. Here, the first and second pattern signals have a signal level set in advance so that the relative signal level with respect to the image signal becomes constant.

[Embodiment] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, an outline of the present embodiment will be described before describing the present embodiment. The image information processing apparatus of the embodiment shown in FIG. 1 has a structure in which the input 8-bit digital image signals VD _{0 to} VD ₇
D / A conversion output VA and pattern (triangular wave) signal SAW with a predetermined cycle
An image information processing apparatus which outputs a binarized image signal Pw which is pulse-width modulated by comparing with a comparator 4, the pattern signal generating means 6 to change the cycle of the triangular wave signal SAW without changing the amplitude and bias of the triangular wave signal SAW. Equipped with 15.

In the configuration shown in FIG. 1, for example, the cycle switching signal SEL
Is designated as n, the clock signal from the frequency divider 6 is 1 / n CL
K is output, and the JK flip-flop 8 forms a pattern clock signal PCLK having a duty ratio of 50%.
The pattern clock signal PCLK is simultaneously supplied to the resistors 10-1 to 10-4, and when one of these resistors is connected to the capacitor 11 by the analog switch 16, it forms an integrating circuit having a predetermined time constant. In this case, the resistance value of the connected resistance is determined according to each designated cycle so as to satisfy the amplitude condition of FIG. Further, the integrated signal output from this integrator circuit has the DC component once removed by the capacitor 12,
The bias voltage is determined by the voltage dividing circuit in the subsequent stage. The analog switch 17 includes resistors 13-1 to 13- so that the bias condition shown in FIG. 5 is always satisfied in any specified cycle in the voltage dividing circuit constituted by the resistors 13-1 to 13-5. 5 is connected to any one contact.

First Embodiment FIGS. 1 and 2 relate to a first embodiment of the present invention, and FIG. 1 is a circuit diagram showing an analog image information processing apparatus. The same components as those shown in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 1, 16 and 17 are analog switches, and one of the internal electronic switches is in the "closed" state depending on the state of the select terminals S1 and S2. In this embodiment, a cycle switching signal SEL from a processor (not shown) is connected to the frequency divider 6 and the analog switches 16 and 17. The processor generates the cycle switching signal SEL according to the image tone of the input image data (indicating the characteristic or property of the image). If the cycle switching signal SEL is designated as n, the clock signal 1 / n CLK is output from the frequency divider 6 and the duty ratio of 50 is output by the JK flip-flop 8.
% Pattern clock signal PCLK is formed. The pattern clock signal PCLK passes through the buffer 9 and the resistors 10-1 to 10-1.
Simultaneously supplied to 10-4. When any of these resistors is connected to the capacitor 11, it forms an integrating circuit with a predetermined time constant, and the resistance value that satisfies the amplitude condition of FIG. 5 is determined according to each designated cycle. Has been. Accordingly, by interlocking the analog switch 16 and the frequency divider 6 and connecting a resistance value matching with the analog switch 16 and the capacitor 11 in any designated cycle, the amplitude condition of FIG. 5 can be always satisfied. The DC component of this integrated signal is once removed by the capacitor 12, and the bias component is determined by the voltage dividing circuit in the subsequent stage. The analog switch 17 has a resistor 13-
It is connected to any one contact of the voltage dividing circuit constituted by 1 to 13-5. Similarly, the analog switch 17 is interlocked with the frequency divider 6 and the analog switch 16, and any one of the resistors 13-1 to 13-5 is set so as to always satisfy the bias condition of FIG. 5 at any specified interval. It is connected to one contact. Thus, the above-mentioned amplitude and the bias condition are satisfied at the same time.

2 (a) and 2 (b) show the triangular wave signal SAW and the analog image signal levels VAmax and VAmin when the designated intervals are different.
FIG. 6 is a diagram showing the relationship with the above, and in any case, the conditions of FIG. 5 are satisfied with respect to the amplitude and bias of the triangular wave signal SAW.

[Second Embodiment] FIG. 3 is a block diagram showing another embodiment of the image information processing apparatus in which the function of FIG. 1 is constituted by a digital element. The same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 3, 6'is 2
This is a frequency divider that outputs the 1 / n CLK and k / n CLK of the divided clock signals of various types.The clock signal k / n CLK is always the clock signal 1
/ n There is a relationship that the frequency is k times CLK. Reference numeral 20 denotes an up-down counter, which is connected so as to count up in the first half of the pattern clock signal PCLK having a duty ratio of 50% and count down in the second half. Moreover, the count clock of the up-down counter 20 is the clock signal.
Since it is a clock signal k / n CLK with a frequency of 1 / n CLK, k count-ups are always performed in the first half of the pattern clock signal PCLK and no matter how the cycle SEL is specified. There is a relationship of counting down k. 4 '
Is a digital comparator which compares the 8-bit digital video data VD at the input terminal A with the down counter output DSAW at the input terminal B and outputs a pulse width modulated image signal Pw of HI level when A> B. Thus, the configuration of FIG. 1 is replaced with the digital element of FIG. 3, and the amplitude and bias conditions of FIG. 5 are satisfied.

[Effect] As described above, according to the present invention, it has a circuit for generating the first and second pattern signals preset so that the relative signal level with respect to the input image signal becomes constant. Therefore, it was necessary when switching the first pattern signal obtained from the first pattern signal as in the conventional case,
The troublesome pattern signal setting operation according to the image signal becomes unnecessary, and for example, even if a character image and a photographic image are mixed in one image, pulse width modulation processing by an optimum pattern signal according to each image tone is performed. It can be done in real time.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an analog type image information processing apparatus of the embodiment, and FIGS. 2 (a) and 2 (b) are diagrams showing the relationship between each triangular wave signal and the analog image signal level in FIG. FIG. 3 is a block diagram showing a digital image information processing apparatus of another embodiment, FIG. 4 is a circuit diagram showing a specific example of a pulse width modulation circuit, and FIG. 5 is the triangular wave signal and analog of FIG. It is a figure which shows the relationship with an image signal level. In the figure, 1 ... latch circuit, 2 ... D / A converter, 4, 4 '
…… Comparator, 5,8 …… JK flip-flop,
6,6 ′ …… divider, 16,17 …… analog switch, 20 ……
It is an up-down counter.

Claims (1)

[Claims] 1. A first pattern signal having a predetermined cycle or a second pattern having a cycle different from that of the first pattern signal, the input means inputting an image signal, and the image signal input by the input means. A pulse width modulation signal generating means for selectively outputting a pulse width modulation signal modulated according to a signal, wherein the pulse width modulation signal generating means is configured so that a relative signal level with respect to the image signal becomes constant. An image processing apparatus comprising a pattern signal generation circuit for generating the first and second pattern signals set in advance.