JPH07105455B2 - Method for manufacturing Bi-MIS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for manufacturing a Bi-MIS semiconductor device in which a bipolar transistor and a MIS FET are formed on a single silicon substrate.
The purpose is to make it possible to manufacture a Bi-MIS semiconductor device with excellent high-speed characteristics as an S semiconductor device by a simple manufacturing process.The manufacturing method is that the emitter layer of the bipolar transistor part and the gate electrode of the MIS FET are the same A growth material, for example, silicon carbide, microcrystalline silicon, or the like is used for simultaneous growth and formation.

[Industrial application field]

The present invention relates to a method for manufacturing a Bi-MIS semiconductor device in which a bipolar transistor and a MIS FET are formed on a single silicon substrate.

[Conventional technology]

As a structure of a Bi-MIS semiconductor device, a Bi-MOS semiconductor device in which a MOS transistor using a bipolar transistor and a gate insulating film of a silicon oxide film is formed on a silicon substrate is well known. An example of a structure of a Bi-MOS semiconductor device and a manufacturing method thereof according to a conventional technique will be described with reference to FIG.

In the figure, reference numeral 1 is a p-type silicon substrate, and an n ⁺ -type indentation layer 2 is selectively formed in a transistor formation region.
The type epitaxial layer 3 is laminated. A thermal silicon oxide film and then a silicon nitride film (not shown) are laminated on the surface of the substrate, and the silicon nitride film is removed except on the transistor formation region. A mask using a resist film is selectively formed, and ions of boron (B) and arsenic (As) are sequentially implanted to form the p ⁺ type element isolation region 4 and the collector extraction layer 10.

After forming a thick field oxide film 9 on the element isolation region by the LOCOS thermal oxidation method, silicon oxide and silicon nitride on the substrate are once removed to expose silicon in the transistor formation region. In the figure, 5 is a region for forming an npn type bipolar transistor, and 6 is a region for forming a p type MOS FET.

A new thin thermal oxide film 16 is formed on the transistor formation regions 5 and 6.
And a p-type base layer 7 is formed by ion implantation of boron using a resist mask (not shown) that opens only the formation region of the base layer 7. Next, the silicon substrate in the emitter layer formation region is exposed, polysilicon is laminated on the entire surface of the substrate, and then the polysilicon is removed except the emitter electrode 21 and the gate electrode 17.

The source region 14 and the drain region 15 are formed again by ion implantation of boron using a resist film that opens the source and drain regions as a mask. At this time, the gate electrode to be formed first
17 acts as a mask for the above ion implantation and MOS
The channel region of the FET section is formed in self alignment.

Then, regions other than the emitter electrode 21 are masked with a resist film, and arsenic (As) or phosphorus (P) ions are implanted into the emitter electrode. Further, by heat treatment at 980 ° C., an n-type emitter layer 8 is formed by thermal diffusion from an emitter electrode 21 made of an n-type doped polysilicon material.

After growing an insulating film 23 (for example, an oxide film, a PSG film or the like) on the entire surface of the substrate, a metal film of Al or the like is laminated on the insulating film by opening each electrode contact portion, and patterned to form a collector electrode 11, An emitter wiring 12, a base electrode 13, a source electrode 19, a drain electrode 20, and a gate wiring 25 are formed.

The structure and manufacturing method of the Bi-MOS described above are merely examples, and FIG. 5 shows a simplified structure, and the above-mentioned steps show only main steps. In particular, the method for forming the emitter layer 8 was the method for forming an emitter using doped polysilicon that is applied to form a high speed bipolar transistor. Many other different structures are used. For example, n channel
In the Bi-CMOS structure in which the MOS FET is also formed on the same substrate, it is necessary to form a p well, and a channel cut is usually formed under the field oxide film. For the formation of the emitter layer 8 of the bipolar transistor, a method of directly ion-implanting into a silicon substrate is usually applied, but the emitter formation method using doped polysilicon, which is explained above with the miniaturization of the structure, is accurate in the emitter region. It can be controlled.

[Problems to be Solved by the Invention]

In order to respond to the demand for high-speed operation in Bi-MIS semiconductor devices, the transition frequency f _t of the bipolar transistor section is increased to increase h _FE , while the cut-off frequency f _c of the MIS FET section is increased. Therefore, the gate length L is required to be further shortened.

The polysilicon emitter structure, which uses the polysilicon to form the emitter of the bipolar transistor described in the prior art, has a better pn junction between the emitter and the base than the method of implanting As ions directly into the silicon substrate to form the emitter. It is possible to control the formation more precisely. However, this method also requires heat treatment at 950 ° C. or higher after ion implantation into the polysilicon of the emitter electrode. The high-concentration (1 × 10 ¹⁹ / cm ³ to 1 × 10 ²⁰ / cm ³ ) impurity regions of the source and drain of the MIS FET previously formed by this heat treatment process are laterally diffused to make the gate length accurate. Control becomes difficult, and defects such as punch-through are likely to occur. On the other hand, the source after the formation of the emitter region and a drain region, and vary the depth of the emitter region by the heat treatment f _t
Highly accurate settings cannot be made.

As another means for increasing the transition frequency f _t of the bipolar transistor and increasing the current amplification factor h _FE , a wide-gap emitter transistor structure in which an emitter is formed of a material with a large band gap that heterojunctions with a silicon substrate is known. There is.

Recently, a technique has been developed for reducing the growth of silicon carbide SiC from a high temperature of 1300 ° C in the past to a temperature of 1000 ° C or lower to nearly 800 ° C. It is an object of the present invention to provide a manufacturing method which enables Bi-MIS having excellent high speed characteristics in a simple matching process by applying this technique to the manufacturing process of Bi-MIS.

[Means for Solving the Problems]

The above-mentioned object is to use the same hetero-growth material such as silicon carbide or microcrystalline silicon for the formation of the emitter layer of the bipolar transistor part of the Bi-MIS semiconductor device and the gate electrode of the MIS FET, and to grow them at the same time. It is achieved by the method of doing.

[Work]

A material that forms a heterojunction with silicon.
C) has a bandgap value, Eg = 2.2 eV, and microcrystalline silicon (μc-Si: H) has Eg = 1.5-
1.9 eV, which is significantly higher than the Eg of silicon, 1.08 eV. As a result of using such a material for the emitter of the bipolar transistor, h _FE can be easily improved because the injection efficiency of the emitter can be increased without particularly lowering the impurity concentration of the base. In addition, silicon carbide allows β-SiC doped with a high impurity concentration to be epitaxially grown on a silicon substrate at a temperature close to 800 ° C, and does not require thermal diffusion of impurities from the conventional doped polysilicon at 950 ° C or higher. Therefore, the lateral diffusion of the source and drain regions of the MIS FET portion which occurs when the conventional high temperature diffusion is performed can be prevented, so that a high-speed Bi-MIS semiconductor device can be easily manufactured. Further, since microcrystalline silicon can be grown at an extremely low temperature of 240 to 450 ° C, a similar effect can be obtained. As described above, according to the present invention, since the emitter region can be formed at a temperature lower than 950 ° C., the forming process does not adversely affect the source and drain regions. Furthermore, in the wide-gap-emitter-structure bipolar transistor of the present invention, the impurity concentration in the base region can be increased, so that the base resistance decreases and f _t
Can be raised. In addition, the emitter region is β-SiC
The base width does not change even if a heat treatment for forming the source and drain regions is performed after the formation.

〔Example〕

The manufacturing method according to the present invention will be described in detail with reference to FIGS. FIG. 1 shows a Bi-MIS to which the manufacturing method of the present invention can be applied.
A cross-sectional view of a completed semiconductor device is shown, and FIGS. 2 to 4 are cross-sectional views during the process. The process up to FIG. 2 is not particularly different from the method described in the section of the conventional art. Hereinafter, the same reference numerals denote the same components as those in FIG.

FIG. 2 shows a state in which the base layer 7 and the collector extraction layer 10 are formed in the bipolar transistor formation region 5 of the silicon (100) substrate. With bipolar transistors
After the silicon substrates in the MIS FET formation regions 5 and 6 are washed and exposed, a thin (about 300 Å) thermal oxide film 16 is grown again on the surface. This state is shown in FIG.

The oxide film 16 on the emitter formation region 30 in the base region 7
Are removed by patterning. Then, n-type β-SiC is epitaxially grown on the entire surface of the substrate. RIE using CF ₄ gas for the n-type β-SiC layer, leaving the emitter 26 and gate electrode 27 by photolithography using a resist film.
Remove by method. This allows the emitter 26 and the gate electrode
27 is formed. This state is shown in FIG.

The following materials have been published for the growth of β-SiC.

“Si Heterojunction Bipolar Transistors with Singl
e-Crystal β-SiC Emitters "T. Sugii, T. Ito: J. of the
Electrochemical Society, Vol.134, No.10, 0ct.1987 “B-SiC / Si Heterojunction Bipolar Transistors wi
th High Current Gain "T. Sugii et al: IEEE Electron De
vice Letters, Vol.9, No.2, Feb.1988 “Low-Temperature Heteroepitaxy of β−SiC on Si
(111) Substrates "T. Eshita et al: '88 MRS Spring Mee
ting of Heteroepitaxy on Silicon In the present invention, C ₂ H ₂ , SiHCl ₃ , and H ₂ gas are used to heat the substrate at about 800 ° C.
It was heated to and epitaxial growth was performed. Also, the doping of impurities
This is performed by mixing PH ₃ as a dopant gas.
AsH ₃ can also be used as the dopant gas. In the examples, the impurity concentration used was 1 × 10 ²⁰ / cm ³ . The method of implanting impurities by ion implantation after growing β-SiC requires an annealing step after implantation, and diffusion of impurities occurs at the boundary between the emitter layer and the base layer 7. A method that does not require the annealing step of is suitable.

Next, as shown in FIG. 4, the source region 14 and the drain region 15 of the MIS FET are opened, the other region is covered with a resist film 28, and boron ions are implanted to form the source region 14 and the drain region 15. To do. The impurity concentration of the source and drain regions is 1 × 10 ¹⁹ / cm ³ .

Further, as shown in FIG. 1, a BPSG film is vapor-grown as the insulating film 23 on the entire surface. The BPSG film has a lower annealing temperature than the PSG film and can be annealed at 850 ° C. By this annealing process, activation of impurities in the source and drain regions and reflow of the BPSG film can be completed at the same time. In this case, the annealing temperature is 100 ° C higher than the annealing temperature by the polysilicon emitter method described in the prior art.
Since the temperature is near low, the base width of the bipolar transistor is not changed.

Further, a resist film is formed on the entire surface and a contact formation portion is opened by photolithography. BP in the contact hole
After etching away the SG film, a metal wiring layer such as Al is laminated and patterned to form a collector electrode 11, an emitter wiring 12, a base electrode 13, a source electrode 19, a drain electrode 20, and a gate wiring 25. The Bi-MIS semiconductor device of FIG. 1 is completed.

The above examples describe a manufacturing method for hetero-growing β-SiC on a silicon (111) substrate. In addition to this, various materials are being studied for use as materials having a large band gap value. It is known that the microcrystalline silicon (μc-Si: H) described above can be hetero-grown at an extremely low temperature (240 to 450 ° C.).

For example, the following report has been published.

“A High Current Gain Si HBT with A Hydrogenated M
icro-Crystalline Si emitter "H. Fujioka et al: IEDM, 1
987 “Micro-Crystalline Heterto-Emitter with High In
jection Efficiency for Si HBT "K.Sasaki etal: IEMD 1
987 When using the above μc-Si: H, after forming the emitter and gate electrodes, activation annealing after ion implantation, or vapor phase growth of the BPSG film, etc. Can't do. Therefore, when μc-Si: H is used, when the base region 7 of FIG. 2 is formed, the source region 14 and the drain region 15 of the MIS FET portion are also ion-implanted (shown by dotted lines 14 and 15). It is necessary to complete the formation of the source and drain regions by completing the annealing process. The growth of the insulating film 23 laminated after forming the emitter and the gate electrode by μc-Si: H is performed by the plasma CVD method,
Alternatively, it is performed at a low temperature by a photo CVD method or the like.

〔The invention's effect〕

As a method of manufacturing a Bi-MIS semiconductor device, a material that heterojunctions with silicon according to the present invention is used, and by forming an emitter region of a bipolar transistor section and a gate electrode of a MIS FET section at the same time, a large current amplification factor h _FE can be obtained. In addition, it becomes possible to manufacture a Bi-MIS having a short channel length and excellent high-speed characteristics in a simple process.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of a Bi-MIS semiconductor device according to the present invention at the time of completion, FIGS. 2 to 4 are sectional views in the process of the Bi-MIS of FIG. 1, and FIG. 2 is a cross-sectional view of a completed bi-MIS semiconductor device according to the above technology. In the figure, 1 is a p-type silicon substrate, 2 is an n-type buried layer, 3 is an n-type epitaxial layer, 4 is a p ⁺ type element isolation region, 5 is a bipolar transistor formation region, and 6 is MIS FE.
T formation region, 7 base layer, 8 emitter layer, 9 field oxide film, 10 collector extraction layer, 11 collector electrode, 12 emitter wiring, 13 base electrode, 14 source region, 15 drain Regions, 17 and 27 are gate electrodes, 19 is a source electrode, 20 is a drain electrode, 21 is an emitter electrode, 23 is an insulating film, 25 is a gate wiring, 26 is an emitter, and 28 is a resist film.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/73 29/78 H01L 29/72

Claims (5)

[Claims] 1. A method for manufacturing a Bi-MIS semiconductor device, comprising using a silicon substrate which has undergone a pre-process before forming a collector region and a base region of a bipolar transistor and a pre-process before forming a gate electrode of a MIS-FET. -A step of forming a gate insulating film on the silicon substrate of the FET part, a step of exposing the silicon substrate in the emitter formation region of the bipolar transistor part, a material having a band gap larger than that of silicon and forming a heterojunction with the silicon With transistor area
Vapor growth on the MIS-FET formation region, MI on the emitter formation region of the bipolar transistor section and MI
A method of manufacturing a Bi-MIS, comprising a step of removing the heterojunction material while leaving the channel region of the S-FET to form an emitter layer and a gate electrode. 2. The method for manufacturing a Bi-MIS semiconductor device according to claim 1, wherein silicon carbide or microcrystalline silicon is used as a material for forming a heterojunction with the silicon. 3. When silicon carbide is used as a material that forms a heterojunction with the silicon, the source and drain regions of the MIS-FET are formed by self-aligned ion implantation using the gate electrode as a mask after forming the gate electrode. The method according to claim 2, further comprising a step of
Manufacturing method of Bi-MIS semiconductor device. 4. The Bi-Mis semiconductor device according to claim 3, further comprising a step of annealing at a temperature lower than a growth temperature of the silicon carbide to form source and drain regions after the ion implantation. Manufacturing method. 5. When MIS-FET is used as a material for forming a heterojunction with the silicon, microcrystalline silicon is used.
The method for manufacturing a Bi-MIS semiconductor device according to claim 2, wherein the formation of the source and drain regions of step 1 includes a step performed before the formation of the gate electrode.