JPH07105452B2 - Thin film E 2) PROM and manufacturing method thereof - Google Patents

Description

The present invention relates to a thin film E ² PROM and a manufacturing method thereof.

[Conventional technology]

Recently, as an E ² PROM, a thin film E ² PROM in which a memory transistor and a selection transistor for selecting the memory transistor are formed of thin film transistors has been considered.

Figure 3 is an illustration of a conventional thin film E ² PROM, the thin film E ²
The PROM has a structure in which a memory thin film transistor T1 and a selection thin film transistor T2 are formed on an insulating substrate 1 made of glass or the like. Note that the thin film transistor, a stagger type, reverse stagger type, coplanar type, but there is a reverse coplanar type, a thin film E ² PROM which is an inverted staggered thin film transistor memory and for selection thin film transistor T1, T2 in Fig. 3 Shows. This thin film E ² PROM
Is manufactured by a method in which a thin film transistor T1 for memory is first formed on a substrate 1, and then a thin film transistor T2 for selection is formed on the substrate 1. The thin film transistor T1 for memory is a gate formed on the substrate 1. An electrode G1, a gate insulating film 2 made of SiN having a hysteresis property formed on the gate electrode G1 over the entire surface of the substrate, and an i formed on the gate insulating film 2 so as to face the gate electrode G1. It comprises a -a-Si semiconductor layer 3 and source and drain electrodes S1, D1 formed on the semiconductor layer 3 with an n ⁺ -a-Si contact layer 4 interposed therebetween. The selection thin film transistor T2 includes a gate electrode G2 formed on the gate insulating film 2 of the memory thin film transistor T1.
A gate insulating film 5 made of SiN having no hysteresis property formed on the entire surface of the substrate on the gate electrode G2;
An i-A-S semiconductor layer 6 formed on the gate insulating film 5 so as to face the gate electrode G2, and the semiconductor layer 6
Source and drain electrodes S2 and D2 formed on the n ⁺ -a-Si contact layer 7 via the n ⁺ -a-Si contact layer 7. The source electrode S2 of the selection thin film transistor T2 is the drain electrode D1 of the memory thin film transistor T1. It is connected through the connection wiring 8. The channel portion of the memory thin film transistor T1 is covered with a protective film 9 made of SiN, and the gate insulating film 5 of the selection thin film transistor T2 is formed by etching away the portion overlapping the memory thin film transistor T1. There is. Reference numeral 10 is an upper protective film made of SiN that covers the thin film transistor T1 for memory and the thin film transistor T2 for selection.

[Problems to be Solved by the Invention]

However, the above-mentioned conventional thin film E ² PROM has a problem that the thin film E ² PROM requires a large number of steps for its production because the thin film transistor T1 for memory and the thin film transistor T2 for selection are formed in separate steps. I was there.

As described above, the memory thin film transistor T1 and the selection thin film transistor T2 are formed in separate steps. It is necessary that the gate insulating film 2 of the memory thin film transistor T1 has a hysteresis property in order to have a memory effect. This is because the gate insulating film 5 of the selection thin film transistor T2 needs to have no hysteresis.

Therefore, conventionally, the thin film transistor T1 for memory is first formed on the substrate 1, and then the thin film transistor T2 for selection is formed.
Since T1 and the thin film transistor T2 for selection are formed in different steps, film formation and patterning of a metal film to be a gate electrode, film formation of a SiN film to be a gate insulating film, and i-a to be a semiconductor layer and a contact layer are performed. -Si film and n ⁺ -a-Si
A thin film transistor T1 for memory is formed by depositing a film and patterning it, depositing a metal film to be a source and drain electrode and patterning it, and removing a contact layer of a channel portion, and further repeating the above steps to select a thin film transistor for selection. Since the T2 has to be formed, the conventional thin film E ² PROM described above requires a large number of steps for its production. Moreover, in this thin film E ² PROM, since the selection thin film transistor T2 is formed on the gate insulating film 2 of the memory thin film transistor T1, the selection thin film transistor T2 is formed.
There is also a problem that T2 protrudes above the memory thin film transistor T1 and the entire thickness of the E ² PROM increases.

The present invention has been made in view of the above-mentioned circumstances, and its object is to provide a thin film E ² PROM and a thin film E ² PROM which can be efficiently manufactured with a small number of steps and can be thinned as a whole. The purpose is to provide a method for manufacturing the ladle.

[Means for Solving the Problems]

In order to achieve the above object, the thin film E ² PROM of the present invention uses a common insulating film as the gate insulating film of the memory thin film transistor and the selection thin film transistor, and the gate insulating film is formed of a SiN film having a hysteresis property. At the same time, the region of the SiN film excluding the thin film transistor portion for memory is a non-hysteresis region having no hysteresis property.

Further, the method for manufacturing the thin film E ² PROM of the present invention is a step of simultaneously forming a gate electrode of the memory thin film transistor and the selection thin film transistor, and a SiN film having a hysteresis property over the formation region of the memory thin film transistor and the selection thin film transistor. A step of forming a common gate insulating film consisting of, a step of eliminating the hysteresis property of the region of the gate insulating film excluding the memory thin film transistor portion to form a non-hysteretic property portion, of the memory thin film transistor and the selection thin film transistor. It comprises a step of simultaneously forming a semiconductor layer and a step of simultaneously forming the source and drain electrodes of the thin film transistor for memory and the thin film transistor for selection.

[Action]

That is, the thin film E ² PROM of the present invention is one in which the same thin film is used as the gate insulating film of the memory thin film transistor and the selection thin film transistor, and thus the memory thin film transistor and the selection thin film transistor have the same gate insulating film. Even as an insulating film, if this gate insulating film is formed of a SiN film having a hysteresis property, and a region other than the memory thin film transistor part of the SiN film is a non-hysteresis part that eliminates the hysteresis property by oxidation or nitriding, The gate insulating film of the thin film transistor portion for memory has a hysteresis property, and the gate insulating film of the thin film transistor portion for selection does not have a hysteresis property, so that the thin film transistor for memory and the thin film transistor for selection can have desired functions respectively. . And
In the thin film E ² PROM, since the gate insulating film of the selection thin film transistor and the memory thin film transistor are a common insulating film, it is possible to form the selection thin film transistor and the memory thin film transistor at the same time, thus the thin film E ² The PROM can be manufactured efficiently with a small number of steps, and the total thickness is smaller than that of the conventional thin film E ² PROM in which the gate insulating film without hysteresis and the gate insulating film with hysteresis are formed in two layers. Can be thinned.

Further, the method for manufacturing a thin film E ² PROM of the present invention, the gate insulating film of the memory thin film transistor and the selection thin film transistor, has a hysteresis property over the formation region of the memory thin film transistor and the selection thin film transistor.
Formed in the step of forming a common gate insulating film made of SiN film and eliminating the hysteresis property of the region of the gate insulating film excluding the memory thin film transistor part to form a non-hysteresis part, and the memory thin film transistor and the selection Since the gate electrode, the semiconductor layer, the source, and the drain electrode of the thin film transistor are simultaneously formed, the memory thin film transistor and the selection thin film transistor can be formed at the same time.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

In FIG. 1, 11 is an insulating substrate made of glass or the like, T1 and T2 are thin film transistors for memory and selection formed on the insulating substrate 11, and the thin film transistor T1 for memory and the thin film transistor T2 for selection are reverse staggers, respectively. It is a type. This thin film E ² PROM consists of thin film transistors T1 and T2 for memory and selection on an insulating substrate 11.
Gate electrodes G1 and G2 are formed, and the gate insulating film 12 is formed thereon.
Is formed over the entire surface of the substrate, and ia-Si semiconductor layers 13 and 13 are formed on the gate insulating film 12 so as to face the gate electrodes G1 and G2, respectively. N ⁺ -a-Si contact layers 14, 14 respectively
Source and drain electrodes S1, D1 and S2, D2 are formed via, and the drain electrode D1 of the memory thin film transistor T1 is connected to the source electrode S2 of the selection thin film transistor T2 via the connection wiring 15. The memory thin film transistor T1 and the selection thin film transistor T2 are covered with a protective film 16 made of SiN having no hysteresis.

Further, the gate insulating film 12 is a common insulating film also serving as the gate insulating film of the memory thin film transistor T1 and the gate insulating film of the selection thin film transistor, and the gate insulating film 12 is a SiN film having a hysteresis property. That is, the composition ratio (Si / N) of silicon atom Si and nitrogen atom N is set to a value (Si / N = 0.85 to 1.1) larger than the stoichiometric ratio (0.75).
The region of the SiN film except the thin film transistor T1 for memory is formed of an iN film, and Si / N is formed by oxidation or nitridation.
The non-hysteretic part 12 was made to have a hysteresis property by reducing the value of to almost the same value as the stoichiometric ratio (Si / N = 0.75).
It is said to be a.

That is, in this thin film E ² PROM, the same insulating film 12 is used as the gate insulating film of the memory thin film transistor T1 and the selecting thin film transistor T2, and thus the memory thin film transistor T1 and the selecting thin film transistor T2 gate insulating film are formed. Even if the gate insulating film 12 is used as a common insulating film, the gate insulating film 12 is formed of a SiN film having a hysteresis property and
If the area excluding the memory thin film transistor T1 portion of the iN film is a non-hysteretic portion in which the hysteresis characteristic is eliminated by oxidation or nitriding, the gate insulating film of the memory thin film transistor T1 portion has hysteresis characteristics, and the selection thin film transistor T2 portion Since the gate insulating film does not have a hysteresis property, the memory thin film transistor T1 and the selection thin film transistor T2 can have the respective desired functions.

In this thin film E ² PROM, however, since the gate insulating film of the memory thin film transistor T1 and the selection thin film transistor T2 is the common insulating film 12, the memory thin film transistor T1 and the selection thin film transistor T2 can be formed at the same time. .

That is, FIG. ² shows a manufacturing process of the thin film E ² PROM, and the thin film E ² PROM is manufactured by the following processes.

First, as shown in FIG. 2A, a metal film is formed on the insulating substrate 11, and the metal film is patterned to form gate electrodes G1 and G2 of the memory and selection thin film transistors T1 and T2.
Then, the gate insulating film 1 is formed on the substrate 11 by plasma CVD over the formation region of the memory thin film transistors T1 and T2 (almost the entire surface of the substrate 11).
The SiN film to be 2 is applied. The deposition of this SiN film depends on the flow rate ratio of SiH ₄ and NH ₃ which is the main component gas
The iN film may be selected so that the Si / N value is 0.85 to 1.1. The gate insulating film (SiN
The film 12 has a hysteresis property.

Next, as shown in FIG. 2 (b), a portion of the gate insulating film (SiN film) 12 to be the gate insulating film of the memory thin film transistor T2 is masked by a resist mask 17, and the gate insulating film (SiN film) is removed. ) The exposed portion of 12 is oxidized or nitrided by, for example, a plasma oxidation method or a plasma nitriding method until the Si / N value becomes approximately 0.75, and the area of the gate insulating film (SiN film) 12 excluding the memory thin film transistor T2 portion is removed. , Non-hysteresis part without hysteresis property
12a.

Next, after removing the resist mask 17, an ia-Si film and an n ⁺ -a-Si film are sequentially formed on the gate insulating film 12 and patterned to form a memory and And the ia-Si semiconductor layers 13 and 13 of the selection thin film transistors T1 and T2,
The n ⁺ -a-Si contact layers 14 and 14 are simultaneously formed, and a metal film is deposited on the n ⁺ -a-Si contact layers 14 and 14, and the metal film is patterned to form the source and drain of the thin film transistors T1 and T2 for memory and selection. Electrodes S1, D1 and S2, D
2 is formed at the same time, and unnecessary portions on the channel portion of the contact layers 14 and 14 of the thin film transistors T1 and T2 for memory and selection are removed at the same time.
As shown in, the memory thin film transistor T1 and the selection thin film transistor T2 are formed at the same time.

Next, a metal film is formed thereon and patterned to form a connection wiring 15 for connecting the drain electrode D1 of the memory thin film transistor T1 and the source electrode S2 of the selection thin film transistor T2 in FIG. 2 (d). ), And then a protective film 16 made of SiN is formed thereon to complete the thin film E ² PROM shown in FIG.

Note that the connection wiring 15 is the source and drain electrodes S1, D1 and S of the thin film transistors T1 and T2 for memory and selection.
It may be formed simultaneously with the formation of 2, D2.

As described above, according to the thin film E ² PROM, the thin film transistor T1 for memory and the thin film transistor T2 for selection can be simultaneously formed in the production thereof, and thus the thin film E ² PROM can be efficiently produced with a small number of steps. be able to. Further, in this thin film E ² PROM, since the gate insulating film of the memory thin film transistor T1 and the selecting thin film transistor T2 is the common insulating film 12, a gate insulating film having no hysteresis property and a gate insulating film having hysteresis property are used.
The total thickness can be made smaller than that of the conventional thin film E ² PROM formed in the layer.

Further, the manufacturing method of the thin film E ² PROM, the gate insulating film of the memory thin film transistor T1 and the selection thin film transistor T2, a common SiN film having a hysteresis property over the formation region of the memory and selection thin film transistors T1, T2 The gate insulating film 12 is formed in the process of forming the non-hysteretic portion 12a by eliminating the hysteresis property of the region except the memory thin film transistor T1 part of the gate insulating film 12, and the thin film transistors T1 and T2 for memory and selection. Since the gate electrodes G1 and G2, the semiconductor layer 13 and the contact layer 14, and the source and drain electrodes S1, s2, D1 and D2 are simultaneously formed, the memory thin film transistor T1 and the selection thin film transistor T2 should be formed at the same time. You can

In the above embodiment, the thin film transistor T1 for memory and the thin film transistor T2 for selection are reverse stagger type, but the thin film transistors for memory and selection may be stagger type, coplanar type, reverse coplanar type, in which case Also, if a common thin film is used for the gate insulating film of the memory thin film transistor and the selection thin film transistor, the thin film E ² PROM can be efficiently manufactured with a small number of steps because the thin film E ² PROM can be formed at the same time. It is possible to reduce the thickness. The thin film E ² PROM in which the memory and selection thin film transistors are of a stagger type is the reverse process of the above embodiment, that is, source / drain electrode formation → contact layer and semiconductor layer formation → gate insulating film formation → gate electrode formation. Can be manufactured in the following process. In addition, a thin film E ² PROM having a coplanar type thin film transistor for memory and selection can be manufactured by the steps of forming a semiconductor layer and a contact layer → forming source and drain electrodes → forming a gate insulating film → forming a gate electrode. Thin film E ² PROM with reverse coplanar thin film transistor and selection thin film transistor
Can be manufactured by the steps of gate electrode formation → gate insulating film formation → source and drain electrode formation → contact layer and semiconductor layer formation.

〔The invention's effect〕

The thin film E ² PROM of the present invention uses the gate insulating film of the memory thin film transistor and the selection thin film transistor as a common insulating film, and this gate insulating film is SiN having hysteresis.
Efficiency and forming a film, a region except for the memory TFT portion of the SiN film, since it is obtained by a non-hysteretic unit eliminates the hysteresis properties by oxidation or nitriding, the thin film E ² PROM is a small number of steps It can be manufactured well and the overall thickness can be reduced.

Further, the method for manufacturing a thin film E ² PROM of the present invention, the gate insulating film of the memory thin film transistor and the selection thin film transistor, has a hysteresis property over the formation region of the memory thin film transistor and the selection thin film transistor.
Formed in the step of forming a common gate insulating film made of SiN film and eliminating the hysteresis property of the region of the gate insulating film excluding the memory thin film transistor part to form a non-hysteresis part, and the memory thin film transistor and the selection Since the gate electrode, the semiconductor layer, the source, and the drain electrode of the thin film transistor are simultaneously formed, the memory thin film transistor and the selection thin film transistor can be formed at the same time.

[Brief description of drawings]

1 and 2 show a thin film E ² PR showing an embodiment of the present invention.
Cross-sectional view of OM and its manufacturing process diagram, Fig. 3 shows conventional thin film
It is a sectional view of E ² PROM. 11 ... Insulating substrate, T1 ... Memory thin film transistor, T2
...... Selection thin film transistor, 12 …… Gate insulating film (hysteresis SiN film), 12a …… Non-hysteresis part, 13
...... Semiconductor layer, 14 …… Contact layer, S1, S2 …… Source electrode, D1, D2 …… Drain electrode, 15 …… Connection wiring, 16…
…Protective film.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H01L 29/786 29/788 29/792 9056-4M H01L 29/78 311 C

Claims (2)

[Claims] 1. A thin film E ² PROM in which a memory thin film transistor and a selection thin film transistor are formed on an insulating substrate, wherein a common gate insulating film is used for the memory thin film transistor and the selection thin film transistor, and the gate insulating film is used. A thin film E ² PROM, characterized in that the film is formed of a SiN film having a hysteretic property, and a region of the SiN film excluding the thin film transistor portion for memory is a non-hysteretic property portion having no hysteretic property. ^2. A method of manufacturing a thin film E ² PROM in which a thin film transistor for memory and a thin film transistor for selection are formed on an insulating substrate, a step of simultaneously forming gate electrodes of the thin film transistor for memory and the thin film transistor for selection, and the memory. Forming a common gate insulating film composed of a SiN film having a hysteretic property over the formation region of the thin film transistor for selection and the thin film transistor for selection, and eliminating the hysteresis property in the region of the gate insulating film excluding the thin film transistor for memory And forming a semiconductor layer of the memory thin film transistor and the selection thin film transistor at the same time, and a step of simultaneously forming the source and drain electrodes of the memory thin film transistor and the selection thin film transistor. Method of manufacturing a thin film E ² PROM characterized.