JPS62290166A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS62290166A JPS62290166A JP13170186A JP13170186A JPS62290166A JP S62290166 A JPS62290166 A JP S62290166A JP 13170186 A JP13170186 A JP 13170186A JP 13170186 A JP13170186 A JP 13170186A JP S62290166 A JPS62290166 A JP S62290166A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- layer
- polysilicon layer
- insulating film
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 59
- 229920005591 polysilicon Polymers 0.000 claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 238000002844 melting Methods 0.000 claims abstract description 17
- 230000008018 melting Effects 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
（産業上の利用分野）
この発明は、例えば２層ポリシリコン構造の素子におけ
る２層目ポリシリコンを高抵抗素子として用いる半導体
素子の製造方法に関するものである。[Detailed Description of the Invention] 3. Detailed Description of the Invention (Field of Industrial Application) This invention relates to a method for manufacturing a semiconductor device using, for example, a second layer polysilicon as a high resistance element in an element having a two-layer polysilicon structure. It is related to.
（従来の技術）
第２図は従来の高抵抗素子となる半導体素子を示すもの
で、その製造方法は、まず半導体基板ｆｌｌ上に各々絶
縁膜（２）をＳ！と０２の酸化反応またはＣＶＤ法によ
って１００〜５００人で形成し、その後、絶縁膜（２）
上にＣＶＤ法で５ｉｎ４の熱分解反応により第１Ｍポリ
シリコン（３）を３０００〜４０００人形成し、このポ
リシリコン（３）の全面にリンを４Ｘ Ｉ Ｏ〜６Ｘ１
０ ＋ｏｎｓ／ｃｉｉＪ拡散してシート抵抗値を２０
〜３０Ω／口にする。そして公知のホトリソグラフィ・
エツチング技術により第１層ポリシリコン（３）に所望
のパターン令形成する。かくして、上記半導体基板（１
１および第１層ポリシリコン（３）上に８１と０２の酸
化反応またはＣＶＤ法によって絶縁膜（４）を１０００
〜２０００人形成し、続いて上記第１層ポリシリコン（
３）と第２層ポリシリコン（６）を電気的に接続するた
めのコンタクトホール（５）を絶縁膜（４）にホトリソ
グラフィ・エツチング技術で形成し、その後、高抵抗素
子となる第２層ポリソリコン（６）をＣＶＤ法により５
００〜３０００人で第１層ポリシリコン（３）に接続す
る。そして、このポリシリコン（６）にイオンインプラ
技術によりリンを０〜９ Ｘ １０ １０ ｎ ５ ／
ｃｍ’ ａ度に打込み所望の抵抗値を得、その後、ホト
リソグラフィ・エツチング技術により所望のパターンを
形成する。この時、第２層ポリシリコン（６）は所望の
抵抗値によって膜厚、長さ、幅を決定し、膜厚を薄く長
さを長くそして幅を狭くすることでより高抵抗となる。(Prior Art) Fig. 2 shows a conventional semiconductor element which is a high resistance element, and its manufacturing method is as follows: First, an insulating film (2) is formed on a semiconductor substrate (S!). 02 oxidation reaction or CVD method by 100 to 500 people, and then insulating film (2)
3,000 to 4,000 pieces of 1st M polysilicon (3) are formed on the top by a 5 in 4 thermal decomposition reaction using the CVD method, and phosphorus is applied to the entire surface of this polysilicon (3) in the amount of 4
0 +ons/ciiJ diffusion and sheet resistance value to 20
~30Ω/mouth. And known photolithography
A desired pattern is formed on the first layer polysilicon (3) by etching technology. Thus, the semiconductor substrate (1
1 and the first layer polysilicon (3) by the oxidation reaction of 81 and 02 or the CVD method.
~2000 layers were formed, and then the first layer polysilicon (
A contact hole (5) for electrically connecting 3) and the second layer polysilicon (6) is formed in the insulating film (4) using photolithography and etching techniques, and then the second layer polysilicon (6), which becomes a high resistance element, is formed. Polysolicon (6) is 5 by CVD method.
00 to 3000 people connect to the first layer polysilicon (3). Then, 0 to 9 x 10 10 n 5 / phosphorus is added to this polysilicon (6) using ion implantation technology.
A desired resistance value is obtained by implanting in cm'a degrees, and then a desired pattern is formed by photolithography and etching techniques. At this time, the thickness, length, and width of the second layer polysilicon (6) are determined according to the desired resistance value, and by making the film thinner, the length longer, and the width narrower, the resistance becomes higher.
次にＣＶＤ法によって第２層ポリシリコン（６）上に中
間絶縁膜（７）を５０００〜８０００人形成し、絶縁膜
ｆ４１、（７）にコンタクトホール（８）をホトリソグ
ラフィ・エツチング技術で形成し、コンタクトホール（
８）から金属配線（９ａ）、 （９ｂ）を第１層ポリシ
リコン（３）に接続して外部入力と配線する。Next, an intermediate insulating film (7) of 5,000 to 8,000 layers is formed on the second layer polysilicon (6) by the CVD method, and a contact hole (8) is formed in the insulating film f41 (7) by photolithography and etching technology. and contact hole (
Metal wiring (9a) and (9b) from 8) are connected to the first layer polysilicon (3) and wired to an external input.
（発明が解決しようとする問題点）
しかしながら、上記した製造方法では第１層ポリシリコ
ン（３）中のリンがコンタクトホール（５）を通じて第
２層ポリシリコン（６）中にｖＡ散し、この結果、第２
層ポリシリコン（６）の不純物濃度が増加して抵抗値の
減少が生じろという問題点があった。(Problems to be Solved by the Invention) However, in the above manufacturing method, phosphorus in the first layer polysilicon (3) is dispersed in vA into the second layer polysilicon (6) through the contact hole (5), and this Result, second
There is a problem in that the impurity concentration of the layer polysilicon (6) increases and the resistance value decreases.
この発明は前記従来技術が持っていた問題点としての抵
抗値の減少を解決した半導体素子の製造方法を提供する
ものである。The present invention provides a method for manufacturing a semiconductor device that solves the problem of the prior art, which is the reduction in resistance.
（問題点を解決するための手段）
この発明は前記問題点を解決するために半導体素子の製
造方法において、第１層ポリシリコンと第２層ポリシリ
コンを接続するために絶縁膜に形成したコンタクトホー
ルの第１層ポリシリコン上に高融点金属を生成し、その
後、第２層ポリシリコンを形成するものである。(Means for Solving the Problems) In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device in which a contact is formed in an insulating film to connect a first layer of polysilicon and a second layer of polysilicon. A high melting point metal is generated on the first layer of polysilicon in the hole, and then a second layer of polysilicon is formed.
（作 用）
この発明によれば、以上のような製造方法としたので、
第１層ポリシリコンに生成した高融点金属がポリサイド
化されろことによって第１，２層のポリシリコンのオー
ミックコンタクトが実現でき、さらに高融点金属がバッ
ファーの役割をして第１層ポリシリコン中のリンの第２
層ポリシリコンへの拡散を抑制することができろ。(Function) According to the present invention, since the manufacturing method is as described above,
The high melting point metal generated in the first layer polysilicon becomes polycide, making it possible to achieve ohmic contact between the first and second layer polysilicon. Lin's second
It should be possible to suppress diffusion into layer polysilicon.
（実 施 例）
第１図はこの発明における半導体素子構造を示すもので
、以下製造方法について説明する。まず、従来方法によ
って半導体基板（１１）上に絶縁膜ｆ１２）を形成し、
この絶縁膜（１乃上に第１層ポリシリコン（１濁を形成
しんのち、第１層ポリシリコン（１勇に所望のパターン
を形成する。その後、半導体基板（川および第１層ポリ
シリコン（１勇上に絶縁膜（１４）を形成することは従
来例に説明した方法と同一である。かくして、第１層ポ
リシリコン（ｌ濁と第２層ポリシリコン（Ｉ５）を接続
するためにコンタクトホール（１θを絶縁膜（１４）に
ホトリソグラフィ・エツチング技術によって形成したの
ち、第１層ポリシリコン（１濁上に例えばタングステン
の高融点金属（１ηの選択デポジションによって５００
〜１０００人形成する。その後、第２層ポリシリコン（
Ｉ５）を減圧ＣＶＤ法を用いて生成する。このとき、第
２層ポリシリコン（１５）は高融点金属（１７）が完全
にポリサイド化されないように生成温度が４５０〜６０
０℃でＳｉＨ４の熱分解によって形成される。その後は
従来法と同様に中間絶縁膜（１司を形成し、第１ポリシ
リコン（１勇上に形成したコンタクトホール（１慢を通
じて金属配置 （２０ａ） （２０ｂ）が形成されろ。(Example) FIG. 1 shows the structure of a semiconductor device according to the present invention, and the manufacturing method will be explained below. First, an insulating film f12) is formed on the semiconductor substrate (11) by a conventional method,
After forming a first layer of polysilicon on this insulating film, a desired pattern is formed on the first layer of polysilicon. The method of forming an insulating film (14) on the first layer is the same as that described in the conventional example.In this way, a contact is formed to connect the first layer of polysilicon (I5) and the second layer of polysilicon (I5). After holes (1θ) are formed in the insulating film (14) by photolithography and etching techniques, holes (1θ) are formed on the first layer of polysilicon (14) by selective deposition of a high melting point metal such as tungsten (1η).
~1000 people will be formed. After that, the second layer polysilicon (
I5) is produced using a low pressure CVD method. At this time, the second layer polysilicon (15) is formed at a temperature of 450 to 60°C to prevent the high melting point metal (17) from being completely polycide.
Formed by thermal decomposition of SiH4 at 0°C. Thereafter, as in the conventional method, an intermediate insulating film (20a) (20b) is formed through the contact holes (20a) and (20b) formed on the first polysilicon film.
ここで、中間絶縁膜（旧を形成した後に行われる絶８ｆ
膜７０（２ｆｆＳ度８００〜９５０℃、 Ｎ２Ｑ ｒ
０２゜３０〜６０分）によってコンタクトホール（Ｉｌ
ｉｌにある高融点金属（Ｉ乃がポリサイド化されること
で、第１層ポリシリコン（１勇と第２層ポリシリコン（
１５１とのオーミックコンタクトが行える。また高融点
金属（ｌ乃がバッファーの役割をして第１層ポリシリコ
ン（１勇中のリンが高融点金属（１ηによって第２層ポ
リシリコン（１５１への拡散が抑制される。Here, the isolation 8f performed after forming the intermediate insulating film (old)
Membrane 70 (2ffS degrees 800-950℃, N2Q r
02° 30-60 minutes) to open the contact hole (Il
By polyciding the high melting point metal (I) in il, the first layer polysilicon (1 layer) and the second layer polysilicon (
Ohmic contact with 151 can be made. Further, the high melting point metal (1) acts as a buffer, and the phosphorus in the first layer polysilicon (1) is suppressed from diffusing into the second layer polysilicon (151) by the high melting point metal (1η).
（発明の効果）
以上説明したようにこの発明によれば、第１層ポリシリ
コンと第２層ポリシリコンとの間のコンタクト部に高融
点金属を形成し、ポリサイド化するようにしたので、第
１層、第２府のポリシリコンの接続は十分なオーミック
コンタクトが得られ、第２店ポリシリコンへのりンの拡
散が抑制できるため、第２暦ボリンリコンの不純物濃度
は低下し高抵抗値が安定化する。また、抵抗値の安定化
により高抵抗素子の微細化も可能となる。(Effects of the Invention) As explained above, according to the present invention, a high melting point metal is formed in the contact portion between the first layer polysilicon and the second layer polysilicon and polycide is formed. Sufficient ohmic contact is obtained for the connection between the first and second polysilicon layers, and the diffusion of phosphorus into the second polysilicon can be suppressed, so the impurity concentration of the second polysilicon is reduced and the high resistance value is stable. become Further, by stabilizing the resistance value, it becomes possible to miniaturize high-resistance elements.
第１図はこの発明の〜実砲例による製造方法によって製
造された半導体素子構造を示す拡大断面図、第２図は従
来の製造方法による半導体素子構造の拡大断面図である
。
（１１）半導体基板、（１２１・絶縁膜、（１勇 第
１層ポリシリコン、（１４） 絶縁膜、（囚・第２層
ポリシリコン、（国・コンタクトホール、（１７）
高融点金属、ｆ１８１・・中間絶縁膜、（２０ａ） （
２０ｂｌ ＝金属配線。
２０ｂ
２０σ第１図FIG. 1 is an enlarged cross-sectional view showing a semiconductor element structure manufactured by a manufacturing method according to an actual example of the present invention, and FIG. 2 is an enlarged cross-sectional view of a semiconductor element structure manufactured by a conventional manufacturing method. (11) Semiconductor substrate, (121・Insulating film, (1st layer polysilicon, (14) Insulating film, (Prison・2nd layer polysilicon, (Country・Contact hole, (17)
High melting point metal, f181...intermediate insulating film, (20a) (
20bl = metal wiring. 20b
20σ Figure 1
Claims (1)
形成する工程と、 高抵抗素子となるポリシリコンを生成し、所望のパター
ンを形成する工程と、 その後、絶縁膜を形成し、絶縁膜フローと同時に高融点
金属のポリサイド化をして上記ポリシリコンをオーミッ
クコンタクトさせる工程とからなる半導体の製造方法。[Claims] A method for manufacturing a semiconductor device having a high resistance element, comprising: a step of forming a contact hole on polysilicon; a step of forming a high melting point metal on the polysilicon of the contact hole; and a step of forming a high melting point metal on the polysilicon of the contact hole. The process consists of the steps of generating polysilicon and forming a desired pattern, and then forming an insulating film and simultaneously converting the polysilicon into polycide with a high melting point metal to bring the polysilicon into ohmic contact. Semiconductor manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13170186A JPS62290166A (en) | 1986-06-09 | 1986-06-09 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13170186A JPS62290166A (en) | 1986-06-09 | 1986-06-09 | Manufacture of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62290166A true JPS62290166A (en) | 1987-12-17 |
Family
ID=15064181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13170186A Pending JPS62290166A (en) | 1986-06-09 | 1986-06-09 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62290166A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5168076A (en) * | 1990-01-12 | 1992-12-01 | Paradigm Technology, Inc. | Method of fabricating a high resistance polysilicon load resistor |
| US5172211A (en) * | 1990-01-12 | 1992-12-15 | Paradigm Technology, Inc. | High resistance polysilicon load resistor |
-
1986
- 1986-06-09 JP JP13170186A patent/JPS62290166A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5168076A (en) * | 1990-01-12 | 1992-12-01 | Paradigm Technology, Inc. | Method of fabricating a high resistance polysilicon load resistor |
| US5172211A (en) * | 1990-01-12 | 1992-12-15 | Paradigm Technology, Inc. | High resistance polysilicon load resistor |
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