JPS60187044A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to form a low resistance electrode wiring without lowering workability by a method wherein, after a metal silicide film to be turned to an electrode or a wiring has been formed, a heat treatment is performed, and a polycrystalline Si film is formed on said metal silicide film. CONSTITUTION:The first layer of wiring 23 is formed on an Si substrate 21 through the intermediary of an oxide film 22. Then, after an interlayer insulating film 24 has been formed on a layer 23, a phosphorus-doped polycrystalline Si film 25 and an MoSi2 film 26 are deposited successively on the whole surface. Subsequently, a heat treatment is performed, and the wire at the stepped part of the film 26 id disconnected. Then, a phosphorus-doped polycrystalline Si film 27 is deposited on the whole surface, and the film 26 is buried in the wire- disconnected part. Then, the second layer of wiring is formed by performing a patterning on the films 25 and 26 successively. According to this method, a current runs not only on the film 25 located at the wire-disconnected part of the film 26 but also on the film 27 which is buried in the wire-disconnected part, thereby enabling to prevent the increase in wiring resistance. Also, as the increase in film thickness of the layer 25 is unnecessary, no trouble is generated pertaining to the workability of the device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and is particularly used for manufacturing a semiconductor device using metal silicide as wiring.

[Technical background of the invention and its problems]

Generally, polycrystalline silicon is used for gate electrodes and wiring in semiconductor devices, but as miniaturization and high speed become important requirements for products, the resistance of polycrystalline silicon cannot be ignored. It becomes.

Therefore, metal silicides such as molybdenum silicide and tungsten silicide, which have resistances about an order of magnitude lower than polycrystalline silicon, are attracting attention as new electrode wiring, and are being put to practical use in some products.

Conventionally, when manufacturing a semiconductor device using metal silicide as wiring, first, as shown in FIG. Interlayer insulating film 4 on wiring 3
A molybdenum silicide (M08!l) film 5, for example, which will become a second layer wiring, is further deposited on the entire surface. Thereafter, the Mo5t film 5 is patterned to form electrode wiring. However, when a heat treatment process such as oxidation is performed after depositing Mo8i, $5, the M in the vicinity of the stepped portion corresponding to the shape of the end of the first layer wiring 3 is removed, as shown in FIG. 1(b).
The oSi film 5 is disconnected. This is considered to be because the stress caused by the expansion and contraction of MoSi and the film 5 itself before and after the heat treatment is greatest near the step portion.

Therefore, as a countermeasure against disconnection in the second layer wiring using metal silicide, the second layer wiring is formed into a so-called polycide structure in which polycrystalline silicon and metal silicide are laminated. That is, as shown in FIG. 2, an interlayer insulating film 14 is formed on a first layer wiring 13 formed on a silicon substrate Il via, for example, an oxide film 12, and then a polycrystalline silicon film 15 and Mo8i, Deposit film I6. In this way, by heat treatment, as shown in the figure (M
Even if the oSi film I6 is disconnected, the conductivity can be compensated for by the underlying polycrystalline silicon film I5.

However, in this method, current flows through the polycrystalline silicon film I5 at the disconnection part of the MoSi film I6'', and the current density increases and the resistance value increases.
If there are a number of disconnection points 6, the wiring resistance increases only in the east, and the advantage of using metal silicide as the wiring decreases.

Note that when the above-mentioned polycide structure is used, the wiring resistance depends on the thickness of the polycrystalline silicon film under the metal silicide, and the thicker the film, the lower the resistance value. Therefore, if the thickness of the polycrystalline silicon film is increased, an increase in resistance can be prevented to some extent, but a new problem arises in that the workability of wiring is reduced.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides a method for manufacturing a semiconductor device that can prevent an increase in wiring resistance due to disconnection of metal silicide without reducing workability when metal silicide is used as wiring. This is what I am trying to do.

[Summary of the invention]

The method for manufacturing a semiconductor device of the present invention includes forming a metal silicide film to serve as an electrode or wiring, then heat-treating the metal silicide film to disconnect it at a stepped portion, and then forming a polycrystalline silicon film on the metal silicide film. By embedding the disconnected portion, increase in wiring resistance can be prevented without deteriorating workability.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3 (al, bl) and FIG. 4.

First, a first layer wiring 23 is formed on a silicon substrate 21 with an oxide film 22 interposed therebetween. Next, after forming interlayer insulation @24 on the first layer wiring 23, a phosphorus-doped polycrystalline silicon film 25 with a thickness of 100 mm and a Mo5i21126 with a thickness of 3000λ are sequentially deposited on the entire surface. Subsequently, a heat treatment is performed at, for example, 1000° C. for 10 minutes to disconnect the stepped portion of the MoSi film 26 (see FIG. 2 (at diagram)). Next, a phosphorus-doped polycrystalline silicon film 27 with a thickness of 2 ooi is formed on the entire surface by low-pressure CVD. Deposit Mo8i.

It is embedded in the disconnected part of the membrane 26. Next, polycrystalline silicon@2
7. The MoSi film 26 and the polycrystalline silicon film 25 are sequentially patterned to form a second layer wiring (as shown in the figure (b1)).

According to the method of the present invention, however, as shown by the solid line in FIG. It also flows.

In other words, it is much more efficient than the wiring manufactured by the conventional method as shown by the wiring in FIG. There will be more flowing passes. Therefore, the current density at the disconnected portion of the Mo8 transducer film 26 is lower than in the conventional case, and an increase in wiring resistance can be prevented. In addition, since there is no need to increase the thickness of the second layer wiring (polycide layer), there is no problem in terms of processability. The same effect can be obtained even if a polycrystalline silicon film is not formed under the O film 26. be able to.

Furthermore, when thermal oxidation is performed after depositing MoSi, an oxide film is formed on the surface of the MoSi film 26, but when polycrystalline silicon@2 is deposited directly on the MoSi film 26, an oxide film is formed on the surface of the MoSi film 26.
7, the oxide film on Mo8i and the film 26 may be removed before the polycrystalline silicon film 27 is deposited.

Furthermore, in the above embodiment, the step portion corresponding to the shape of the end of the first layer wiring 23 was explained, but the first layer wiring 23
Of course, the method of the present invention can also be applied to all step portions other than the end portions of No. 3.

〔Effect of the invention〕

As described in detail above, the semiconductor device of the present invention provides remarkable effects such as being able to form electrode wiring with extremely low resistance without deteriorating workability.

[Brief explanation of drawings]

Fig. 1 (al and mountains) is a cross-sectional view showing a conventional wiring forming method, Fig. 2 is a cross-sectional view showing another conventional wiring forming method, and Fig. 3 (a) and (bl) are cross-sectional views showing a conventional wiring forming method. FIG. 4 is an explanatory diagram showing the flow of current in the wiring formed in the example of the present invention, and FIG. 5 is a cross-sectional view showing the method of forming the wiring in the example of the present invention. It is a sectional view showing a formation method. 21... Silicon substrate, 22... Oxide film, 23...
. First layer wiring, 24... Interlayer insulating film, 25.27...
Polycrystalline silicon film, 26...Mo8i, @. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3. Figure 4

Claims (2)

[Claims] (1) In manufacturing a semiconductor device using metal silicide as an electrode or wiring, a metal silicide film is formed, then heat treated, and a polycrystalline silicon film is further formed on the metal silicide film. Production method. (2) After forming a metal silicide film and heat-treating it,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the oxide film on the surface of the metal silicide film is removed and a polycrystalline silicon film is further formed on the metal silicide film. (31) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the polycrystalline silicon film is a low resistance polycrystalline silicon film containing impurities.